SU1564731A1 - Device for detecting errors in equal-weight code k out of n - Google Patents

Abstract

The invention relates to computing. Its use in systems for the transmission and processing of discrete information makes it possible to increase speed. The device contains a generator of 1 clock pulses, a multichannel converter 2 of a parallel code in a sequence of pulses, trigger 3, elements OR 5.11, counting unit 6, reversible drives 7, a group of 8 And elements and And 9.10 elements. Due to the introduction of half-adders 4 and element 12 OR, the speed of the device is increased by up to 30% compared with the prototype. 2 Il.

Description

SP

oh

with

impulses, trigger 3, elements OR 5, 1, counting unit 6, reversible drives 7, group 8 elements AND and elements AND 9, 10. Thanks to the introduction

half-adders 4 and the element OR 12, the speed of the device is increased by up to 30% compared with the prototype. 2 Il.

The invention relates to computing and can be used in the construction of systems for the transmission and processing of discrete information. The purpose of the invention is to increase speed.

FIG. 1 is a block diagram of the device and FIG. 2 shows an embodiment of a reversible accumulator.

The device contains a generator of 1 clock pulses, a multichannel converter 2 of a parallel code in a sequence of pulses, rfep 3, half-adder A. first element OR 5, counting unit 6, reversible accumulators 7, group 8 elements I, first and second elements AND 9 S, second and the third elements are OR 11, 12. In FIG. 1, bus inputs 13, information output 1, and exit 15 of the operation of the device are indicated.

A multichannel converter 2 of a parallel code into a sequence of pulses can be performed, for example, on a pulse distributor, the outputs of which are connected to the first inputs of 2p groups of elements AND (2p is the number of channels of converters 2), the second inputs of elements And of each group are information inputs of the corresponding converter channel 2, and the outputs are connected to the inputs of the OR element, the output of which is the corresponding information output of the channel of converter 2, the pulse input of the pulse distributor n is the clock input of the converter 2, and output of its last bit Yes - stop output transducer (output end of the transducer).

A multichannel converter 2 of a parallel code into a sequence of pulses can also be implemented in the form of 2p shift registers connected by information inputs to the corresponding information inputs of converter 2, clock inputs to its clock input, and transfer outputs to information outputs of the corresponding channels

five

0

five

0

five

0

five

0 i

converter 2, the inverse outputs of each shift register are connected to the inputs of their AND element, and the outputs of the latter are connected to the inputs of the AND element, the output of which is the stop (conversion end) output of converter 2, the write resolution of the shift register registers are connected to the recording inputs of the converter 2.

Trigger 3 is executed as an RS trigger if multichannel converter 2 is executed on shift registers, or on a pulse distributor, the output signal of the stop (end of conversion) of which is synchronized with a pause between clock pulses, or as a counting trigger, and if the converter 2 is implemented on a pulse distributor, the signal at the output of the conversion end of which is synchronized with the clock pulse.

The reversible accumulator 7 can be made (FIG. 2) in the form of a reversible counter 16 on (10

(W + 1) t 3logi (K + 2) C) RazR Dov. the element And 17 and the block 18 forming the threshold. FIG. 2, the subtracting input 19, the first and second summing inputs 20, 21, which are the installation inputs of 1 m, respectively, the first and second bits of the counter 16, and the first to third outputs 22-24, are indicated.

A reversible counter 16 for h bits can be executed (Fig. 2) on the triggers 25, elements OR 26, elements AND 27, and NAND 28 elements. In the initial state, binary 7.1 is recorded in the counter 16 of the accumulator 7.1

The code of q. / 0. The direct outputs of the bits of counter 16 with numbers, different numbers of single bits in the binary code of q ;, and the inverse outputs of the remaining bits are connected to the inputs of the element And 17, the inverse and direct outputs of which are respectively the first and second exits 22, 23 accumulator. Ecryi selected number 1 2 - (K + 1). then the third output 2k is the forward output of the senior discharge of the estimator 16. In all other cases, the direct outputs of the counter 16 are connected to the inputs of the unit 18 implementing the threshold q. + K + 1, FIG. 2 shows the execution of this block on the element OR 29 and the element AND 30. For the case, To the 11.8 general case, the block 18 can be executed as follows.

Let the binary representation a be

and

AND

s

Ь 2

ll-h

Let o (, o ... d e-i O a 1. The inputs of the block, starting from the e-th and up to g-ro (the corresponding outputs of counter bits 16), such that

 ABOUT

o (e - ol a - i ft

connected to the inputs of the element And, the output of which, as well as the inputs of the block, starting with (g + 1) -th and up to h-ro, are THAT o / d + 7 ... o (-h 0.

a t, + 1 1, are connected to the inputs of the OR element, the output of which, as well as the block inputs, start from (h + 1) -th and to the m-th, such that o (+1 g ... / „, 1, a 0, O, are connected to the inputs of the element I, the output of which, as well as the inputs of the block, starting at (t + 1) -th and ending at the entrance with the number S, such that o / t., O (t +. .. 0. ao (s + 1 1, are connected to the inputs of the OR element, and so on until all the inputs of the threshold shaping unit 18 (outputs of the counter 16) are combined. In the particular case of 2P, the threshold shaping unit 18 is in the form of the OR element, connected by inputs to the inputs of the block from (p + 1) -th and to the U-ro. In particular om

case

€ (. S (g

 o / p, 0, and

p rm:

 of p

1, the threshold shaping unit is performed as an AND element connected by inputs to the block inputs from p-th to U-ro. When a, the threshold shaping unit is executed as a communication line from its inlet to the outlet.

Counting unit 6 is performed in a form similar to drive 7, replacing reversible counter 16 with a summing counter and eliminating the inverse output of the AND 17 element, while direct output of the AND 17 element and the output

block 18 are the first and second outputs of the counting block 6, in which 5 code q 77 0 is written in the initial state.

In the device diagram (Fig. 1), it is possible to replace the connection of the output of the first element I 9 with the direct input of the second

Yu element And 10 on the connection of the output of the second element OR 11 with the inverse input of the second element And 10.

The device operates as follows.

15 In the initial state, the multichannel converter 2 of a parallel code into a sequence of pulses, a counting unit 6, reversible accumulators 7 and a trigger 3 are reset. With

20 this, at the output of flip-flop 3, a zero signal that blocks the passage of clock pulses through AND 8 elements. A code of the number q is written to drive 7-i in the initial state. , and in the counting block 6, the code of the number q. When performing multichannel converter 2 on the shift registers, the input code from the input information bus 13 is recorded in these shift registers.

30 At receipt of clock pulses from the generator 1 clock output to the clock input of the multichannel converter 2, the latter converts the number of single signals fed to the group of input information buses 13.1 (inputs of the 1st channel of the converter 2) into the corresponding number of pulses at the output of the 1st information channel .

The pulses from the 1st and (p + 1) -th outputs of the multichannel converter 2 are fed to the inputs of the half-adder k.l. If a pulse arrives at one of its inputs, it causes a pulse.

45 at its output of the sum, connected to the first counting input of the reversible accumulator 7.1 (at 1 p), and through the element OR 5 with the first summing input of the counting block 6 (at 1 p).

50 to the contents of which is added one. If the pulses arrive at both inputs of the half adder

35

40

five

4.1, this causes a pulse at its transfer output connected to the second summing input of the reversible accumulator 7.1 (at 1 p) and the second summing input of the counting unit 6 (at 1 p), to the contents of which is added the number two.

7156

If during the operation of the multichannel converter 2 at least K + 1 pulses arrive at the inputs, then a second signal is generated at the second output of the counting unit 6 through the element OR 12 at the output 15 of the device’s end of operation, indicating that the device has completed the operation cycle, The first output of the counting unit 6 to the output of the element And 10, which is the information output 14 of the device, receives a zero signal. If during the operation of multichannel converter 2 in the counting unit 6 no more K pulses are accumulated, then the operation continues in the order described above until all input information buses are polled, which will require n / 2pC cycles. At the same time, at the end of the operation of the multichannel converter 2, it self-blocks and then does not generate pulses on the information outputs of the channels. In this case, at its output of the conversion end, a single impulse appears, switching trigger 3 (in the pause between clock pulses), at the output of which a single signal appears, allowing the passage of clock pulses through AND 8,

Dal-it is the process of successive recalculation of the contents of the reversible drives 7 into the counting unit 6. Let 7.Ј be the smallest number of the accumulator in which the code other than qr is written, i.e. during the operation of the multichannel converter 2, pulses arrived at its summing inputs. At the same time on the first output of the reversing accumulator}. t - a single signal, and on the second, connected to the inputs of the elements 8. (g + 1) - - 8. (p - 1) And - zero, prohibiting the passage of clock pulses to their outputs.

Thus, at all inputs of element 8.g, both single signals and clock pulses pass through it to the subtracting input of the reversing accumulator 7 g, from the contents of which a unit is subtracted each time, and through the element OR 5 to the first summing input of the counting block 6, to the contents of which is added one. Work continues in this manner until the reversing accumulator 7. g is returned to its original state. At the same time on his

the first output is a zero signal, prohibiting the passage of clock pulses at the output of the element 8.g and, and at the second output - a single signal that permits the passage of clock pulses at the outputs of the elements 8. (g + 1) and - 8. (o - 1 ). Then, the contents of the accumulators 7. (g + 1) - 7. (p 1) are recalculated in a similar way into a counting unit 6.

If a

1. xK, then in some

gi

the moment of time in the counter of the counting unit 6 will be written down the code of the number q + K + 1, where q is the code of the number of the initial state of the counter of the block 6. At the second output of the counting unit 6, a single signal arriving through the OR 12 element at the output 15 the end of the device operation, the certificate of the end of the work cycle, and from the first output of the counting unit 6, a zero signal (control result) is sent to the AND 10 element, causing a zero signal at the output 1 of the device.

one

If X x Ј K, then at the end

recalculating the contents of all reversible accumulators 7 into the counting unit 6 at their second outputs are single signals indicating their return to the initial state, which causes a single signal at the output of the AND 9 element, coming through the element OR 12 to the output 15 v of the device control end, certificate of completion of the work cycle. In this case, from the first release of the counting

block 6 on the element And 10 enters

iп

zero signal if .h.k, and

“- n single signal if%. - K.

Upon receipt of the inputs of some half-adder k + K + 1 or K + + 2 pulses, the counter of the reversing accumulator 7L contains the code of the corresponding number, which causes a single signal at its third output, coming through the elements OR 11 and 12 at the output 15 of the end device operation, certificate of completion of the work cycle. In this case, from the output of the element 10 to the information output 14 of the device receives a zero signal, since

at its input, connected to the output element And 9 - zero signal.

Thus, the output unit signal is generated at the output K of the device only if there is exactly K single signals in the input code.

A device for detecting errors in the reverse code K of n provides an increase in speed of up to 30% compared with the prototype.

Claims (1)

Invention Formula A device for detecting errors in the equilibrium code K of n, containing a multichannel converter of a parallel code in a sequence of pulses, 2p groups (p 2, 3, ...) whose information inputs are the corresponding inputs of the device, a clock generator, the output of which is connected to the first the inputs of the first (p - 1) -th group AND elements and the clock input of the multichannel parallel code converter in a sequence of pulses, the output of the conversion end of which is connected to the trigger input, the output to Secondly, it is connected to the first input of the first element I and the second inputs of the first - (p - 1) -th elements of AND group, the outputs of which are connected to the subtractive inputs of the same-name reversible drives and the corresponding inputs of the first element OR whose output is connected to the first input of the counting unit, the output of which is connected to the first input of the second element five 0 five 0 five 0 that And, the first output of the 1st reversible accumulator (i 1, p-G) is connected to the (i + 2) -th input of the 1st element of the AND group, the second output of the 1st reversing accumulator is connected to (i + + 1) to the input of the first element AND and (i + 2) to the input of the (i + 1) -th - (pl) -rc elements of the AND group, the output of the first AND element connected to the second input of the second AND element, the output of which is informational the output of the device, the third outputs of all reversible drives are connected to the corresponding inputs of the second element OR, characterized in that, in order to improve speed, the device the third element OR and the first are the pth half-adders, the j-th and (p + J) -and information outputs (j 1, p) of the multichannel parallel code converter in the pulse sequence are connected respectively to the first and second inputs of the j-ro half-adder, the outputs of the sum and the pgrenos of the 1st half adder (i 1, p - 1) are connected respectively to the first and second summing inputs of the 1st reversing accumulator, the outputs of the sum and transfer of the pth half adder are connected respectively to the pth input of the first OR element and the second the input of the counting unit, the second output otorrhea and output of the second OR gate are connected to first and second inputs of a third OR gate, the third input of which is connected to the output of the first AND gate, the output of the third OR gate is the output termination operation. Editor M.Tovtin Compiled by (Krevinsky Tehred M.MorgentalKorrektor M.Pogo Order 1166 Circulation 655 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab., D. V5 Production and Publishing Combine Patent - Uzhgorod, Gagarin str., 191 h " I Subscription