SU1383339A1 - Device for modulo m equals two raised to power "n" minus one multiplication - Google Patents

Description

oo with

00

oo with

The invention relates to computing technology and information measuring systems and can be used in digital devices.

signal processing, in particular, for digital image processing, as well as in encoding devices, the principle of action of which is based on the theory of finite rings and Galois fields.

The purpose of the invention is to increase the fastness of the device.

Fig. 1 shows a functional diagram of a device for multiplying by modulus W-2 -1; Fig. 2 shows a functional scheme of a multi-input (p-input) one-bit adder; in fig. 3 is a functional circuit diagram of the switch; FIGS. 4 and 5 are a functional block diagram of the formation of partial products; figure 6 is a functional diagram of the priority node; in fig. 7 Fundamental shift scheme; in fig. 8 - scheme of multipliers per powers of two; Fig. 9 is a functional block diagram of a summation of partial products; in fig. 0 - functional block correction circuit.

The device for multiplying modulo 1 (Fig. 1) contains a group of inputs 1 ,, 1 ,, ..., 1 "of the direct value of the operand b, b, ..., b, group of inputs 2, 2j , ..., 2 inverse value of the operand b, b, ..., b, group of inputs of the charger, 3j, ..., 3 (direct value) of the second operand a

a, commutator A, block 5 of formation of partial products, block 6 of summation of partial products, block 7 of correction, switch 8, multi-pass one-bit adder 9, group of elements NOT 10 ,, 10, ..., 10 out: odes 11 ,, 11, ..., ll ,, The values of the operands can be selected from the registers (with direct and and vertical ones; one register can be connected to the inputs 1, .., 1, u2, 2 ..., 2), and in the register the result value from the outputs 1 1, ..., 11 p. Can be entered. The adder 9 with its inputs 12 ,, 122, ..., 12 “is connected to the inputs 1, ., 1, ..., In and with output 13 of the highest order - with KOhiMyTaTOpoB 4 and 8 are used as control inputs. Switch 4 inputs are connected to inputs 14, 1) AND 2 ,, 22, ..., 2 ", and outputs 14, 14, ..., 14 to the first group the inputs of block 5,

the second group of inputs of which is connected to inputs 3 ,, 32, moves 15 ,, ISj, ..., 15X (where kn, n + 1

, 3, and you

even k

at

n - odd) are connected to the inputs of block 6, outputs 16 ,, 16 ,, ..., 16. Which are connected to the inputs of block 7, outputs 17 |, 17, ..., 17 of which are connected to the inputs of elements NOT Y lOj, ..., 10 "and the first group of information inputs of the switch 8, the second group of inputs of which is connected to the outputs of the elements NOT YOU ,, 10,

   P

Multi-input one-bit sum

Mat 9 (FIG. 2) is built on binary adders 18.

Switch 4 (fig.Z) contains the element And 19 ,, 19, ..., 19 „, 20 ,, 20, ..., 20, OR 21 ,, 21 ,, ..., 21„, NOT 22 Switch 8 is built similarly.,

Block 5 of forming partial products (Figures 4 and 5) contains priority nodes 23, 23, 23, ... 23c, modulo-two adder groups 24, shifters 254, 25c. The sets of nodes 23 and adders 24 determine the control codes that are fed to the transfer codes of the shifters 25, to the informational inputs of which is fed from inputs 3, 3, ..., 3, the operand code a, aj, ..., but". Each S-th node 23 (FIG. 6), where 6 1, 2, ..., k, has inputs 26d ,, ..., 2b and outputs 27, d ..., 27g, j. The node 23d contains the elements NOT 28 ,, ..., 28 ,, And 29,, ..., 29.,.

Each shifter 25 (Fig.7) contains groups of elements And 30, multipliers 31 for powers of two and group of elements OR 32.

Block 6 of summation of partial products (Fig. 9) has k n-bit inputs and contains binary s (mators 33 and node 34 of accelerated transfer.

Correction block 7 (FIG. 10) contains binary adders 35, accelerated transfer node 36, and And 37 element. In total, blocks 6 and 7 Preferred are an adder of k numbers modulo M.

The product of the numbers a and b modulo M Q a-b (mod M) is the remainder of dividing the usual product a b by the value of the module M.

The principle of fast multiplication is as follows.

For M 2 - 1, the equality is: a, i.e. the negative number in the ring 2c (the set of integers Go, 1, 2, ..., M – P with the addition and intelligent modulo M operations considered on it), represented in the binary number system, gets c as a result of the inversion of the corresponding - a positive number to it. Negative numbers appear to be coded integer numbers, large

M,

. For example, for Z, Z- you can write the correspondence:, 1 ,,,, 5 --- 2, b - 1. In the binary number system, these numbers can be represented by three-bit binary numbers: 1 1 O 6; 101 5; 011 100 - 4, so multiplication can be carried out by the following expression:

a-b (mod M) () (mod M). (one)

The result of multiplying modulo M 2 1 has a number of bits equal to the number of bits of each of the factors.

Obviously, the inversion of one of the factors according to (1) is only reasonable if this factor (in the expression (1) is the number b) has more than half of the units in significant digits. The operation of the switch 4 is controlled by a p-input single-bit cummator 9, on which a sum of multiplier multipliers is formed. If the number of units in bits of the multiplier is greater than n / 2, the value of the bit at the output

de adder 9 (t, where

parentheses denote rounding to the nearest larger integer) is one. Junior times are not used. The value of the row of the adder 9 is the control signal for the switch 4. From the outputs of the switch 4, the direct or infused multiplier value is fed to the inputs of block 5, to the other inputs of which is multiplied from inputs 3, 3j, ..., 3 “. Block 5 generates k words of partial products that are output to outputs J 5,, 15, ..., 15, (each output is bitwise). The words of partial works are summarized.

Q

five

0

five

thirty

35

by means of block 6 and corrected by block 7, at the outputs 17, 17, ..., 17j of which the word digits of the sum of partial products are formed. From these outputs, the direct meaning of the word sum of partial products is supplied to the first inputs of the switch 8. In addition, the sum of the partial products is inverted with the help of the elements NOT 10 ,, 10, ..., 10 "and again. given to the second: inputs of the switch 8. The latter is controlled using the same control signal as switch 4. Thus, if the multiplier is inverted using switch 4, the result of the multiplication is inverted using switch 8, as required expression (1). From the outputs of the switch 8, the value of the modulo 2-1 output is fed to the outputs 1 1 of the device.

Example. During the operation of block 5, let it be necessary to multiply two numbers a 1101011 (p 7 and M 2 1) and b 0011011. The multiplication is carried out according to (1). This means that the word a is applied to the inputs 3 ,, 3, ..., 3, the inverse word b 1100100 is fed to the outputs 14j, 14;, ..., 14 ". The first (lower) k bits go to the inputs of node 23. The task of node 23 is to select the unit that is encountered for the first time in a word that goes to the inputs of this node.

50

55

la At the inputs 26 ,,, 26

12

26,

 (7 + 1) / 2 4) node 23, the word 0010 is given. At outputs 27

(k

n

27

14

have 0010 (in this word only one 40 units, therefore the input value

coincides with the weekend). This word is in-. Controller for shift 25,. The first inputs of the adders 24 ,, - 24.5 modulo two are given the word ds 010, and the second inputs of the adders

24 „-24, - word 010 from exits

27,227, node 23,. To the input 26. of node 23, the value of the nth bit is applied, i.e. zero. So on adders 24 - 24, the two words 010 and 010 are modulated together, which results in the word 000. As a result, the inputs and outputs of the node 23j have the zero word 0000, which is also the control for the shifter 25. On the first the inputs of the adders 242, g ° °, the module two is supplied with the word 000 from the outputs of the adders 24.2 and 24.3, the first two bits and the third bit from the output 14c-, the second

the inputs of adders 2A, j-24, the word 000 is fed from the outputs 21 -27,, 4 nodes 23, the value of the sixth digit, i.e. unit. So, adders 24, 24.3 modulo two words 000 and 000, which results in the word 000. As a result, at the inputs of node 23, there is the word 0001 and the output is exactly the same word 0001, which is the control for the shifter 25 ,. On the first inputs of adders 24 ,, -24, modulo two, the word 001 is supplied from the outputs of the adders and the first., Two bits, and the third (k + 2) -ft bit from the output 14g. For the second entrances, the sum is. tors 24 ,, -24.5 is served 00-1 from outputs 27.2, 27.4, node 23 ,. At the entrance 2644, 10

20

This node is given the value of the latter, i.e. Seventh row, equal to one. At adders 24, -24, two words 001 and 001 are modulated, which results in the word 000. As a result, at the inputs of node 23 there are 25 and 25 inputs of the summation unit, partly word 0001 and at the output of exact products, outputs which is the same word 0001, which is the control for the shifter 25.

1. A device for multiplying modulo M 2 - 1, containing a partial product formation unit, a partial product summation unit and a correction unit, wherein a group of inputs of one of the device operands is connected to one of the groups of inputs of a unit of forming partial products, the outputs of which are connected

thirty

The layout of the node 23 performs the function of selecting the first unit in the codeword, which is fed to the inputs 265,,, ..., 26. Multipliers 31 by a power of two multiply by a power of two modulo M, which is the usual cyclic shift and these multipliers are simple wire re-switching. Figure 8 shows such a rewiring for the case of M 2-1. The multiplier 31e multiplies the multiplicand by 2 by the power of two, the multiplier Z. by 2,

35

multiplier

31 - on

i-k-i

Attached to the inputs of the correction unit, characterized in that, in order to improve performance, two switches are introduced into it, a multi-input single-bit adder and a group of elements NOT, and the other group of inputs of the block of formation of partial products is connected to the outputs of the first switch, the first and the second the group of information inputs of which are connected respectively to the group of inputs of the direct value and the group of inputs of the inverse. the value of another operand of the device, in | The inputs of the correction unit are connected to the first group of information inputs of the second switch and the inputs of the corresponding NOT elements of the group, the outputs of which are connected to the second group of information inputs of the second switch, the outputs of which are the device outputs, and the control input connected to the control input of the first switch and the senior output a multi-input single-bit adder, the inputs of which are connected to the first group of inputs of the information inputs of the first switch

the multiplication is carried out modulo M. The result is a cyclic shift of the multiplicand with the help of a control word that arrives at the input of the elements OR 32 ;, 32, -, ..., 32, -. If in the control word the jth bit is one, the element

com and 30, 31,

30, ..., 30й1 multiplier nn is a power of two, which multiplies by. The result of the multiplier is fed to the outputs of the shifter 25 through the elements OR 32. At the outputs of the remaining multipliers by powers of two (multipliers 31sj, 3155, JC) are signals corresponding to the value of the logical zero.

 the inputs of the summation block of partial products whose outputs

Block 6 implements the modulo M operation of kn-bit words of partial products. Correction block 7 eliminates the W ambiguity of the representation of zero O (mod M 2 - I). In the binary number system, zero can be represented by the zero code word 000 ... O, as well as the word 111 ... 1 2 t 1. Correction unit 7 converts the single word to zero.

Claims (1)

1. A device for multiplying modulo M 2 - 1, containing a partial product formation unit, a partial product summation unit and a correction unit, wherein a group of inputs of one of the device operands is connected to one of the groups of inputs of a unit of forming partial products, the outputs of which are connected 5 inputs of the summation block of partial products, the outputs of which 0 five five 0 five Connected to the inputs of the correction unit, characterized in that, in order to improve speed, two switches are introduced into it, a multiple-input single-bit adder and a group of elements NOT, and the other group of inputs of the block of formation of partial products is connected to the outputs of the first switch, the first and the second the group of information inputs of which are connected respectively to the group of inputs of the direct value and the group of inputs of the inverse. the value of another operand of the device, in | 1 moves,. the correction unit is connected to the first group of information inputs of the second switch and the inputs of the corresponding NOT elements of the group, the outputs of which are connected to the second group of information inputs of the second switch, whose outputs are the device outputs, and the control input connected to the control input of the first switch and the higher-order output Yes, a multi-input one-bit adder, the inputs of which are connected to the first group of inputs of the information inputs of the first switch. , 2, The device according to claim. 2, and the fact that the block of formation of partial products contains k priority nodes, (k-1) modulo two adder groups and k shifts (k -5- with n - even 1 , n + 1 K. for n - odd; n is the width of the operands), and the inputs of the first priority node are connected to the inputs of the first group of the block from the first to, the inputs of the priority node (i 2, ..., k) are connected to the outputs. adders modulo two (1-1) -th group and (k + il) -M input of the first group of the block, the first input of the mater modulo two (1-1) -th group (J 1, ..., k- 1) connected to (j + l) -M the output (il) -ro of the priority node, the second input of the modulo two of the second group is connected to) the input of the first group of the block, the second input of the modulo two of the 1st group (r I, ..., k-2 1 "2, ..., k-1) is connected to the output of the (g + 1) -th modulo adder two (1-1) -th groups, the outputs of the priority nodes are connected to the control inputs of the corresponding shifters, whose information inputs are connected to the inputs the second group of the block, and exits - with the block exits. and 9.3 % / J  d Vй L.G l FIG. 7 . th "-N 4 t 2% Vuz.B 9 F “g. YU