SU1236473A1 - Arithmetic unit - Google Patents

Abstract

The invention relates to computing and can be used in the construction of high-speed computing devices. The aim of the invention is to increase the speed. The device contains a multiplicable register, an intermediate register, groups of converters of a binary code to a nonpositional code, an adder, a group of converters of a nonpositional code to a binary code, a shift register of a multiplier, a shift register of partial products, a group of switches, a control unit and corresponding links. 1 hp f-ly, 4 ill. ISD co od co

Description

The invention approaches computing and can be used when building high-speed computing devices.

The aim of the invention is to increase speed.

FIG. 1 shows a diagram of an arithmetic unit; on. FIG. 2 - diagram of the adder; in fig. 3 is a diagram of the multiply operation algorithm; FIG. 4 is a diagram of the addition operation algorithm.

The arithmetic unit (Fig. 1) contains an n-bit binary register 1 of multiplicand, an n-bit binary intermediate register 2f first 3 and BTopiTo 4 groups of m converters of binary code into non-positioned code, t-bit adder 5, group 6 of m converters of nonpositional code into binary code, n-bit binary binary shift register 7 multiplier, (n + 1) -bit binary shift register of 8 partial products, group 9 of t-k-bit switches, firmware control unit 0, inputs 11 and 2 of the first and second operands of the device, outputs 13 and 14 of the high and low bits of the device result.

The discharge of the adder 5 (Fig. 2) contains a node 15 forming a cI- {we node 16 forming an amount increased by unit 5 a node 17 forming an amount reduced by the base of the positional number system, a node 18 forming an amount increased by one and decreasing by base positional number system, circuits 19 and 20 versus constant; the first 2, the second 22, the third 23, the fourth 24, the fifth 25, the sixth 26, the seventh 27 and the eighth 28 elements I, the first 29, the second 30, the third 31, the fourth 32 and the fifth 33 elements of the ISh switch FOR, information inputs 35 and 36, output 37 amounts, transfer input 38, transfer output 39.

The arithmetic unit works as follows.

The multiplication is performed by the lower bits forward by the method of multiple shift and addition of the multiplicable depending on the value of the next bit of the multiplier 5 shifted in the multiplication process (Fig. 3).

The control unit 0 is set to the operation code Multiplication (X), then a Start signal is triggered

control unit 10, which begins to form a sequence. control pulses. The signal from the fourth output of control unit 10 is reset to registers 7 and 8, and the signal from the fifth output is reset to register 2. Signals from the first and second outputs in registers 1 and 7 put the binary multiplicand codes and multiplies .l respectively . The contents of register i multiplied by groups of K-bits on converters of group 4 are converted into a positional residual code

(SU,, W, ..., S), S

20 where r is the number of bases of the SOC, for which a group of K binary bits is represented by the SOC code such that

h

, 2s j p.

| one

From the outputs of converters 4, the position-residual code of the multiplicand enters the first inputs of the corresponding bits of the adder 5, the second inputs of which receive the position-residual code with converter 3 (at the beginning it is zero). The result of the addition from the adder 5 is fed to the corresponding converters of group 6, from the output of which the binary code is fed to the information inputs of the binary shift register 8..

If the least significant bit of the multiplier (register 7) is equal to one, then by the control input the entry from the third output of the control unit 10 information from the information inputs of the register 8 is entered into it, and

The J5 signal from the sixth output of control block 10 arriving at the clock inputs of the shift registers 7 and 8, their contents are shifted by one bit to the right, while the most significant (least) bit of register 8 is zeroed

35

40

Yo

S5

If the low bit of the multiplier (register 7) is zero, then the signal from the sixth output of control block 10 arriving at the clock inputs of the shift of registers 7 and 8, their contents is shifted by one bit to the right, with 3toM the highest (left) bit register 8 is zeroed.

At the next time point, the contents of register 8 arriving at the first information inputs of group switches 9, using the control signal from the seventh code of the control unit G, post their outputs and then the information inputs of the binary intermediate register 2. Thus, the information the inputs of the register 2 is the first partial product, which with the help of the control signal from the fifth output of the control unit 10 is entered into this register

From this moment, the second cycle of the device operation begins, when multiplier multiplies with the first partial product on adder 5. There are as many such cycles as binary bits in the multiplier. At the end of the last cycle, in the register 8, the highest product bits are found (output 13), and on the register. re 7 is the low order of the product (output 14).

Addition (Fig. 4) begins from pdaci to the fourth input of block 10 of the control of the code of the operation of addition (+). A start signal is then given, triggering the control unit 10. Signals from the fourth output of control unit 10 reset registers 7 and 8, and signals from the first and second outputs register binary codes of operands in registers I and 7.

When the signal from the seventh output of control unit 10 is zero, the contents of register 7 are transmitted via the second information inputs of the switches 9 of the group to their output and then to the information inputs of the binary intermediate register 2. The second operand is entered into the register 2 by the signal from the fifth output of control unit 10, from where it goes to converters 3, where it is converted into a position-residual code and goes to the second inputs of the corresponding bits of the adder 5, to the first inputs of which from register I through converters 4 goes first operand in position-residual code.

In adder 5, the sum is formed according to the rule

WITH.

.M and 3j bj- f ..

 l .- b / f ,,,.

0

s

0

five

0

five

five

0

where f is the transfer signal from the low S to the high bit.

The sum from the outputs of the corresponding bits of the adder 5 enters the converters 6, where from the position-residual code is converted into a binary code. From the outputs of the converters 6, the sum in binary code goes to the information inputs of the register 8, and the signal from the third output of the control unit 10 is entered into this register, from the output of which goes to the first 13 output of the device.

Let us consider in more detail the operation of one bit of the adder 5. Nodes 15-18 are modulo, respectively, the summation of values at information inputs 35 and 36, the summation of values at information inputs 35, 36 with one, the summation of values at information inputs 35, 36, and subtraction from the obtained value of the base value of the positional number system, summing up the values at the information inputs 35 and 36 with the unit and subtracting from the obtained value the base value of the positional number system .- Due to the small base size It is advisable to make these nodes of a tabular type based on the ROM.

The comparison circuit 19 with a constant forms a paraphase transfer value, provided that the input value is greater than or equal to the base value of the positional c-number system. The comparison circuit 20 with a constant forms a paraphase transfer value, provided that the input value is equal to the base value of the positional number system, reduced by one. Schemes 19 and 20 with a constant can be implemented on the basis of ROM or combinational logic. The value of the sum in the form of the binary-coded SOK code and the paraphase transfer value are removed from the output of the switch 34 and the elements OR 32 and 33.

The device control unit 10 is a standard firmware control unit, the operation of which is described by algorithms (Figs. 3 and 4).

Claims (2)

Invention Formula . An arithmetic unit containing an n-bit binary multiplicative register, consisting of m-bit groups (), an n-bit binary shift register of a multiplier, consisting of m k-bit groups of an n-bit binary intermediate register, of the mk-bit groups, (n + 1) -bit binary shift register of partial products, consisting of m k-bit junction groups, n-bit totalizer and microprogrammed control unit, with the lower-order outputs and output low-order (n + 1) -discharge binary shift register partial respectively, are the output of the higher bits of the device result and are connected to the high-level shift input of the n-bit binary shift register of the multiplier; the inputs of the first and second operands of the device are connected to the information inputs of the n-bit binary multiplier and shift register of the multiplier, respectively the outputs of which are the output of the lower order bits of the device, the output of the lower bit of the n-bit binary register of the multiplier is connected to the first micro input of the control unit whose second input is the device Start input, the third control unit input is the Device multiplication input, the write inputs are n-bit binary binary multiplicative register and shift register multiplier, and n least-significant bits (n + l)-bit the bottom of the binary shift register of partial products are connected respectively to the outputs of the first, second and third control fields of the microprogrammed control unit, the zero inputs of the n-bit binary register multiplier and () -binary binary About the shift register of partial products are combined and connected to the input of the fourth control field of the microprogram control unit, the input of the entry of the n-bit binary intermediate register is connected to the output of the fifth control field of the microprogram control unit, the clock inputs of the binary binary shift register of the multiplier and (n + 1) -discharge binary shift register of partial products combined and connected to the output of the sixth control five 0 five 0 five 0 five five the field of the firmware control block, the transfer output of the p-th discharge of the adder is connected to the transfer input (pl) -ro () of the totalizer discharge, the transfer output of the senior-discharge accumulator is connected to the information input of the senior discharge (n + 1) -discharge Binary shift register of partial products, characterized in that, in order to improve speed, it contains the first and second groups of hectares of binary code to nonpositional code, a group of m converters of nonpositional code to binary code, a group of mk-day switches, the group of outputs of which are connected respectively to the group of information inputs of the n-bit binary intermediate register, the group of outputs of which are connected respectively to the group of inputs of the binary code converters to the nonpositional code of the first group, the group of outputs of the n-bit binary register of the multiplicand is connected to the group of inputs converters of a binary code into a non-positional code of the second group, the outputs of which are connected to the first information inputs of the corresponding bits of the g-bit sum tori, the second information inputs of which are connected to the outputs of the corresponding binary code converters to the nonpositional code of the first group, the outputs of the n-bit accumulator bits are connected to the inputs of the corresponding converters of the nonpositional code to the binary code of the groups whose outputs are connected to the information inputs of the corresponding groups ( +1) - bit binary shift register of partial products, except for zero bit, the output group of which is connected respectively to the first group of information the inputs of the group switches, the second group of information inputs of which are connected respectively to the group of outputs of the n-bit binary shift register multiplier, the control inputs of the switches of the group connecting the output of the seventh control field of the microprogram control unit, the fourth input of which is the input Addition of the device. 2. A device according to claim 1, characterized in that bit m7 the bit adder contains nodes for forming an amount, an amount increased by one, an amount reduced by the base positional number system, an amount increased by one and reduced by the base positional number system, two comparison schemes with a constant, eight elements AND, five elements OR and a switch, with the switch output being the output of a ha-bit accumulator adder, the information inputs of which are connected to the corresponding inputs of the nodes forming the sum, the sum increased by one, the sum, decrease on the basis of the positional number system, the amount increased by one and reduced on the basis of the positional number system, the outputs of which are connected respectively to the first, second, third and fourth information inputs of the switch, the output of the sum forming node is connected to the inputs of the first and second comparison circuits with a constant, the inverse output of the first comparison circuit with a constant is connected to the first inputs of the elements And from the first to the fourth, the direct output of the first comparison circuit with a constant is connected to the first inputs elements And from the fifth to the eighth, the second inputs of the first, third, fourth, fifth, and seventh elements And are connected to the inverse output of the second ske 364738 we are compared with a constant whose direct output is connected to the second inputs of the second, sixth and eighth elements AND, the third inputs of the first, second, fifth and sixth elements AND are connected to the inverse transfer carry input of the t-bit adder, the direct input transfer of which is connected to the third inputs of the third, 0 of the fourth, seventh and eighth elements AND, the outputs of the first and second elements AND are connected through the first element OR to the first control input of the switch, the second, third 5 and the fourth control inputs of which are connected respectively to the outputs of the third element AND, the second and third elements OR, the outputs of the fourth, fifth and sixth elements AND are connected respectively to the inputs of the second element OR, the outputs of the seventh and eighth elements And are connected respectively to the inputs of the third element 1, the outputs of the first 5 of the OR element and the third AND element are connected respectively to the inputs of the fourth OR element, the output of which is the inverse discharge transfer output of the tp-discharge totalizer, the direct transfer output of which is connected to the output of the fifth OR element, the first and second inputs of which are connected respectively, with the outputs of the second and third elements OR. here 37