SU1305702A1 - Device for generating all possible combinations - Google Patents

Abstract

The invention relates to computing technology and can be used to build computer-aided design systems for electronic and electronic computing equipment. The purpose of the invention is to increase the speed of the device. The goal is achieved by the fact that a second logic block 2, a group of 6 AND elements, a code shifter 7 and an adder 8 are inserted into the device containing the register 1, the second logical block 3, and the impulse generator 9 with the corresponding connections. 1 il. SL

Description

113

The invention relates to computing and can be used to build systems for the automated design of electronic and electronic computing equipment.

The purpose of the invention is to increase the speed of the device.

The drawing shows the functional diagram of the device.

The device contains a register 1, the first and second 2 and 3 logical blocks built on the elements OR

4, 4 And 5, 5, a group of 6 elements And the shifter 7 code, the adder 8 and shaper 9 pulse.

The principle of operation of the device is based on the following algorithm.

The original is a combination in which N units are written in addition in lower order bits (right). The next combination is calculated by the formula

1st

.., + 4 ..,

Where

A,:, m

previous combination; , where L is the number of consecutive zeroes, starting with the least significant bit, up to the first unit in (1-1) -th combination;

K is the number of consecutive units after L zeroes before the first successive zero.

Consider the example of the search combinations with for the case,. The number of such combinations is determined by the formula

( P.

N; (nn)

 ten.

The starting point for this case is the combination A 00111.

We obtain the sequence of all combinations using the specified algorithm, for (00100)

BUT, ,

L (4) ,,

2

then

 L 00111 + 00100 01011,

Similarly, we get all the other combinations:

five

0

five

0

Thus, the enumeration of combinations continues until all units are not in TC in the highest digits.

The device works as follows.

The initial combination, containing N units in lower order bits, is written to register 1 before starting work. As soon as this combination appears at the output of register 1, the formation of the numbers 2 -1 and 2 begins. Consider some intermediate combination recorded in register 1. When the number 2 -1 is formed, unit potentials appear in the inverse outputs of register 1 in those bits to which the corresponding zero-bit bits correspond, elements And 4 select only the next bits in the lower bits of the unit potentials of the inverse outputs of register 1, if clock speeds are available. Moreover, the number of elements AND 4 is equal to p-3, since the greatest number of consecutive zeros in the combination will be at, and the last combination requiring reading of zeros is 010 ... O, therefore the next 5, last, combination not

requires processing. The binary number 2-1 thus generated is fed to the inputs of the elements OR 5, to the other inputs of which this combination is fed from the direct outputs of register 1, and the number 2 to 2 seconds is summed. . For example, if AJ 0110100, 2 -1 0000011, then as a result, at the output of the elements OR 3, we have A, -., +2 -1 0110111.

Moreover, in any case, summing the number 2 –1 does not result in transfer to the higher bits, since the number 2 –1 has unity D 1 in L subgroups of the next bits, starting with the youngest. This circumstance allows the summation of the numbers 2--1 and A- not in the adder, but on the OR element, thus the time of summation is significantly reduced.

Getting the number 2 -1 happens

simultaneously with the formation of the sum r) L

0

five

i

0

2 -1. in the following way.

Using the second logical block 3 and block 6 of the elements I, a connection to the engine inputs 7 of the code (L + K) of the lower bits is provided. Indeed, as soon as the outputs of register 1 have another combination Aj, then the unit potential at the output of the L + K-ro element is AND 4, which blocks the elements of And 6 through the corresponding elements of OR 5, starting with L + K-ro. Therefore, only the first L + K bits of register 1 are selected, which are connected via elements And 6 to the inputs of the code shifter 7. For example, with A ,. OIOJJSS input

to L - shifter 7 code connects lower bits. In order to convert the information received from the outputs of the elements And 6 into binary

code number 2

K-1

her need to shift

on L positions in the direction of younger bits, and then block (K-1) bits, starting with the youngest. From the output of the code shifter 7, the binary code of the number 2 is fed to the inputs of an n-bit asynchronous adder 8 to the other inputs of which the number () + A, is supplied. As a result of the summation, a new combination is formed, and a single potential appears at the signal output of the adder, which through the shaper 9 pulses in the form of a square pulse arrives at the synchronization input of register 1. The combination of this signal is recorded in register 1, and it appears at the output of register 1 after the end of the pulse, i.e. by his

back front. With the appearance of A-on

register output begins a new cycle of the device. The signal for enumeration of combinations is the occurrence of N units in the higher order bits of the combination. In this case, the output elements 4 and zero potentials. This forms a sign of the end of the operation of the device.

All combinations are read from the direct outputs of register 1 using a single clock pulse at output 10.

50

The time required to obtain one combination is the sum of the delay55 signals on the elements and is (.IS + nJ "tj, where n is the number of bits in the code; tj is the delay time on the valve (AND / OR element).

The time of formation of one combination in the known device is (Zn + 9) - tj.

Thus, the marginal gain in speed is

lira

.

Sn + 9 n + 15

 3

five

0

five

five

0

-

0

five

Claims (1)

Invention Formula A device for enumerating combinations containing a n-bit register, the first logical block implementing the function U (... X |) v X,, where Y, X, are Boolean variables:, 4, . . ., 2 (p-2) is the bit number of the input; t y is the output bit number, the I group of elements, the code shifter and the adder, the information output of which is connected to the information input of the register, the direct outputs from the second to the nth bits of which are connected to the first inputs from the first to (n-1 ) -th element and group, respectively, the outputs from the first to (p-2) -and elements and which are connected to the information inputs from the second to (p-1) -th bit of the code shifter, the information input of the first discharge of which is connected to pr my output of the first register bit, inverse outputs from the first to (p-2) -and The poles of which are connected to even-numbered inputs from the second to 2 (p-2) -th bits, respectively, of the first logical block, the output of the (p-1) -th element of the AND group is the output of the sign of the device’s end of operation, characterized in that - the purpose of speeding up, it contains the second logic block that implements the function Y |) ... V Xj, the driver of the pulse g, the output of which is connected to the register synchronization input, the direct outputs from the first to (n-2) -th bits connected to odd inputs from the first to 2 (p-2) -1st bits, respectively, of the first and The second logical block, the inverse outputs from the second to (p-1) -th digit of the register are connected to the even inputs from the second to 2 (p-2) -th bits of the second logical block, respectively, the th outputs of which are connected to the inverse inputs tl ele513057026 cops and groups respectively, you are of the first addend of which the turn of the (n-2) -th bit of the second logical is connected to the output of the n-th bit of the register block is connected to the (n-1) th inverse, the output of the code block is connected the input of the element AND of the group, the output of the second term of the summation bit of the first logical block, the output of the sign of the end of the sum is connected to the input of the first perovodovaniya which is connected to the input adder term, input (t + 1) -th, impulse driver.