SU1564733A1 - Device for revealing errors in parallel code - Google Patents

Abstract

This invention relates to automation and computing. Its use in systems for the transmission and processing of digital information improves speed. The device contains a generator of 1 clock pulses, 2P-channel converter 2 parallel code in a sequence of pulses and blocks 3 counting units. By introducing the summation and control unit 4 and the corresponding connections in the device, parallelization of the conversion process is provided. 9 hp f-ly, 6 ill.

Description

ate

about

4. J

with

00

w 5 .1 5. (p + 1) 52 5 (p + 2)

Rig /

5p 52p

The invention relates to automation and computer technology and may be used for. creating systems for the transfer and processing of digital information.

The purpose of the invention is to increase speed.

FIG. 1 shows a block diagram of the device} in FIG. 2 and 3 embodiments of the unit counting unit; in fig. 4-5 are embodiments of the summation and control node.

The device contains (Fig. 1) a generator of 1 clock pulses, a 2p channel converter 2 of a parallel code into a sequence of pulses, p blocks 3 units of counting and node 4 summation and control. FIG. 1, inputs 5, informational outputs 6, the control output 7 and the output 8 of the termination of work are indicated.

Converter 2, having 2p groups of inputs (p 1,2 ...), provides conversion of the input code, divided into 2p groups of symbols, into 2p sequences of pulses, i the number of which in each sequence is | equal to the number of units in the corresponding with a group of characters. The implementation of the Converter 2 is the same as in the prototype, for example, 2p shift registers.

Unit 3 counting unit — can be implemented (FIG. 2) on counter 9 and half accumulator 10, while its sum and overflow outputs are connected to the estimated inputs of the first and second bits of counter 9, respectively. BJIOK 3 unit counts can be implemented ( Fig. 3) differently on a reversible counter 11 and the first and second elements of the prohibition BAN 12, 13.

The summation and monitoring unit 4 may include (FIGS. 4-6) the summation unit 14, the threshold units 15f of the first and second elements OR 16 17 and the decoder 18.

The summation unit 11 is constructed from adders according to a pyramidal scheme. Moreover, those adders that correspond to the weights W Ј A (A is the threshold of the blocks 15) are the first. the outputs of block 19; outputs of adders with scales W A - second outputs 20,

Counters 9 (for the cases of FIG. 4-6) can also be performed with preset s 0 ,,, where i is the block number 1564/33

n-1 + q "In this case, block 14 is not modular.

In the case where node 4 is configured in FIG. 6, the reversible counter 11 of the block 3.i can be executed with presetting the code of the number of input bits in group 5. (p + i) of the inputs, while the inputs are made with in-jq versions. For modulo K modalities, the summation unit 14 and the reversible counters 11 are functionally modulo K.

The threshold blocks 15 in embodiments 15 of FIG. 4, 5 have a threshold A. If you select the initial state of the counters q. - K - 1, then A, while the threshold blocks 15.i degenerate into the connection from the forward 20 output of the last discharge of counter 9 or 11.

The decoder 18 in the embodiment of FIG. 4 is an AND element, the forward inputs of which are connected to the 25 turns of block 14, the weights of which are equal to the digits of the binary bits of the K + q code weight, and the inverse inputs to the remaining outputs of the 14 block and the OR output 16., d Decoder 18 according to the variants of FIG. 5 and 6 has the same design and connection, except for the connection with element 16 OR.

Node 4 is configured in FIG. 4 at

35

40

ka 3 (i 1, p) ..

- qi (

K +

to p by fig. 5 at 5 K (n - 2p) and in FIG. 6 with K (p-2p), where n is the number of device inputs, K is the weight of the controlled equilibrium code.

The device works as follows.

- In the initial state, the converter 2 and the counters in blocks 3 are reset. In this case, if block 4 is made according to FIG. 4-6, and block 3 of FIG. 2, in the counter 9.i the code qj 7/0 is written down; if block 4 is made of FIG. 6; and block 3 of FIG. 3 then in the reversible counters 11.1 a code of the number of inputs 5 is written. (P + i).

The convertible code is fed to the inputs 5 and, in the case of the conversion of the converter 2 on the shift registers, is written to these. registers.

Upon receipt of the clock pulses from the output of the generator 1 to the clock input of the converter 2, the latter converts the parallel code at input 50

55

five

0

to p by fig. 5 at 5 K (n - 2p) and in FIG. 6 with K (p-2p), where n is the number of device inputs, K is the weight of the controlled equilibrium code.

The device works as follows.

- In the initial state, the converter 2 and the counters in blocks 3 are reset. In this case, if block 4 is made according to FIG. 4-6, and block 3 of FIG. 2, in the counter 9.i the code qj 7/0 is written down; if block 4 is made of FIG. 6; and block 3 of FIG. 3 then in the reversible counters 11.1 a code of the number of inputs 5 is written. (P + i).

The convertible code is fed to the inputs 5 and, in the case of the conversion of the converter 2 on the shift registers, is written to these. registers.

Upon receipt of the clock pulses from the output of the generator 1 to the clock input of the converter 2, the latter converts the parallel code to input 0

five

dah 5.1 and 5- (p + i) in the pulse sequence at their i-th and (p + 1) -th outputs, with the number of pulses equal to the number of ones in the code at the corresponding inputs 5. The specified pair of sequences is fed to the inputs of the 1st block 3 counting units.

If this block 3.1 is executed according to FIG. 2, then when a pulse arrives, only one input of half adder 10 adds one to the contents of counter 9, and when incoming pulses to both inputs of half adder 10 the number two adds to the contents of counter 9.

If block 3 is made of FIG. 3, when a pulse arrives at only one input of a block, it passes through the corresponding element 12 or 13 to the corresponding input of counter 11. If two pulses arrive at block 3-1, then pulses do not pass to counter 11. Codes from the block outputs 3.i arrive at node k, where block k determines the code for the sum of the input codes.

The operation continues in this manner until the conversion of the input code by the converter 2 is completed. If the node 4 is made of FIG. k or 5, this is true for the case when the number of units of the input code does not exceed K. This requires n / 2p operation cycles (n is the number of bits of the input code).

At the end of the conversion, converter 2 is self-blocking and at its output, a single signal appears at the end of the conversion, which, as it passes to output 8, signals the end of work. At outputs 19 of block T, there will be a code of the number of units of the input code. If it is equal to the code of the number. To, then the output 7 will be a single signal, if this code is not equal to the code of the number K - zero. This code is fed to outputs 6.

If the number of units in the input code is greater than K, then the operation ends before the final conversion of the input code. In the embodiment of node 4 of FIG. The operation goes until a single signal appears at the output of at least one threshold block 15.i or at the outputs 20 of block 14 or at the output of block 15. (p + 1). The signal from the element OR 16 passes to the output 8 and locks the decoder 18. In the embodiment, the nodes

733

ten

15

20

la k in fig. 5, the work will go on until a signal appears at the output of block 15 passing to exit 8; At output 7, the signal will be zero. That we will be when the node k in FIG. 6, since at the end of the operation of converter 2 (signal at output 8) at output 7 there will be a zero signal.

When the device operates in the mode of counting the number of units modulo K, it works as follows. In the initial state, the converter 2 and the counters in blocks 3 are reset, while the reversible counters 11.1 are written down, the code for the number of inputs 5- (p + 1) modulo K. At the inputs 5, a controlled code is fed. Upon receipt of clock pulses from generator 1, converter 2 converts a parallel code at inputs 5.1 and 5. (p + 1) into sequences of pulses at their i-th and (p + 1) -th outputs, from which they arrive at the inputs of block 3.1- 25, the latter is performed in FIG. 3. When a pulse is received from the 1st output of the converter 2, a unit is added to the first input of the block 3.1. The pulse of the (p + 1) -th output of the converter 2 is added to the second input of the block 3.1 from the contents of its counter 11. subtract one. If the pulses arrive simultaneously at both inputs of the block 3.1, then the state of its counter 11 does not change. The operation continues until the conversion of the input code by the converter 2 is completed. The codes from the outputs of blocks 3 are summed modulo K in node 4. When the conversion of the input code is completed, the converter 2 self-blocks and a single signal appears at its output of the conversion end 8 which indicates the end of the work. At outputs 6 of block A there will be a code. the numbers of units at the inputs modulo K.

The device can also work in the mode of forming the input code remainder modulo K. To do this, input 5.1 and 5. (p + 1) input bits of the input code are used that have the same value of the modulus K weight balance, and the jth code bit at the outputs of block 3, counting units has a weight (2 JW,) - | modK W-., where W; - the value of the modulo K remainder of the weights of the bits of the input code supplied to the inputs 5-1

thirty

35

40

45

50

7156

and 5- (p + i). In this case, the j-th output of block 3.i is connected to the inputs of block 1 with weights equal to the weights of the unit bits in the binary representation of the number W: Then, when the conversion of the input code is completed by converter 2, the remainder of the modulus K of the input code is generated at the outputs of block 14 .

With a small number of input code bits with identical weights balances modulo K, inputs 5, corresponding to bits with the highest weights balance values, can be connected to the inputs of several groups so that the sum of weights for the K modules for these groups equals the remainder modulo K of the weight of the corresponding input.

Thus, the device allows counting and controlling the number of units of the input code modulo K, as well as generating and controlling the remainder of the input code by

module K, providing increased speed, as it requires I - 1 clock cycles.

Claims (6)

Invention Formula 1. A device for detecting errors in a parallel code, comprising a clock pulse generator, the output of which is connected to a clock input of a 2p-channel converter of a parallel code into a sequence of pulses (p 1,2 ...), the first 3. The device according to claim 1, It is clear that the block for the units of accounts contains a reversible counter and the first and second elements of the BANNER, allowing the first input and prohibiting the input of the second BAN, are the first input of the block, allowing the second input and prohibiting the input of the first element s BAN combined and i are the second input unit, outputs of first and second elements with inverted subkey us to the summing and subtracting input of down counter, the output of which are the outputs. 4. The device according to claim 2, wherein the summation and control node contains the first (PI) th threshold blocks, the decoder, the first and second OR elements, and the first sum block — the p inputs of which are combined with the corresponding inputs of the corresponding 30 (2p) -e informational inputs of which 40 are of the first - pth threshold blocks are the same-named inputs of the device, and the first - the p-th outputs are connected to the first inputs of the first - p-th units of units, characterized in that, in order to improve speed, the unit summation and control is entered into the device, (p + 1) th - (2p) -th outputs of a 2p-channel parallel code converter to a pulse sequence are connected to the second inputs of the first, respectively, p-th units of unit count, the outputs of which and the output of the 2p-channel converter's conversion of a parallel code into the pulses are connected respectively to the first — rm and (p + 1) th inputs of the summation and control node, the first, second and third outputs of which. are respectively the information outputs, the control output and the output end of the operation of the device. 2. The device according to claim 1, about t l and In particular, the unit counting unit contains a counter and a half adder, the first and second inputs of which are the same inputs of the block, the sum and overflow outputs of the half accumulator are connected to the counting inputs of the first and second digits of the counter, respectively, the outputs of which are the outputs of the block. 3. The device according to claim 1, wherein the unit counting unit contains a reversible counter and the first and second BAN elements, allowing the first input and prohibiting the input of the second BAN, are the first input of the block, allowing the second input and the prohibiting input of the first BANKS elements are combined and are the second input of the block, the outputs of the first and second BANKS elements are connected to the summing and subtracting inputs of the reversible counter, the outputs of which are the outputs of the block. 4. The device according to claim. Characterized in that the summation and control node contains the first - (p-I) -th threshold blocks, the decoder, the first and second elements OR, and the first block - the p-e inputs of which are combined with the corresponding inputs first of the first - pth threshold blocks 0 They are the first inputs of the node, the first outputs of the summation unit are connected to the corresponding inputs of the decoder and (p + 1) th threshold block and are the first outputs of the node, the second outputs of the summation unit and the outputs of all threshold blocks are connected to the inputs the first OR element, the output of which is connected to the first input of the second OR element and the gate input of the decoder, the output of which is the second output of the node, the second input and the output of the second OR element are respectively (p + 1) -th input and the third output of the node. 5. The device of claim 1, wherein the summation and control node contains a threshold block, a decoder, an OR element and a summation block, the first of which the p-e inputs are of the same name as the node inputs, the outputs of the sum block The world connections are connected to the corresponding inputs of the decoder and the threshold block and are the first outputs of the node, the output of the decoder is the second output of the node, the output of the threshold block is connected to the first input of the OR element, the second input and output of which are respectively (p + 1) the entrance and the third exit node. 6. The device according to claim 2, wherein the summation and control node comprises a decoder and a summation unit, the first adders connected in a pyramid scheme, the inputs of the adders of the first group are the corresponding inputs of the block, the outputs of the adders of the last group with weights W A, where A - the threshold of the first-- (p + 1) -th threshold block is the first outputs of the block; the outputs of the adders of all groups with weights W A are the second outputs of the block. 8. The device according to PP. 2-5, that is, that the i-th score The tick (i 1, p) is made with a preset of the 5th code 4j I, 5L q - q, A  K + 1 + q. 9. The device according to PP. 3 and 6, t - characterized by the fact that the reverse inputs of which are of the same name counters and summation unit The node's inputs, the outputs of the summation unit are connected to the inputs of the decoder and are the first outputs of the node, the output of the decoder is the second output of the node, the (p + 1) -th input of the node is connected to its third output. 7 о The device according to claim kf differs from the fact that the summation BLk contains Jlog /, p groups , 6 733Yu the adders connected by the pyramid scheme, the inputs of the adders of the first group are the corresponding inputs of the block, the outputs of the adders of the last group with weights W A, where A is the threshold of the first-- (p + 1) th threshold block, are the first outputs of the block, outputs Adders of all groups with weights W A are the second outputs of the block. 8. The device according to PP. 2-5, that is, that the i-th score The tick (i 1, p) is made with a preset of the 5th code 4j I, 5L q - q, A executed modulo K. 10. The device according to PP. 3 and 6 about the fact that the 1st. the reversible counter is made with the presetting of the code of the number (p + i) -x of the information inputs of the 2p-channel converter of the parallel code into a sequence of pulses made inverse. FIG. J rr - T-T FI.5 Compiled by O. Revinsky Editor M.TovtinTehred by M. MorgantalKorrektor O. Kravtsova Order 1166 Circulation 660 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab., K / S Production and Publishing Combine Patent, Uzhgorod, Gagarin st., 101 fit / a 6 Subscription