SU1257637A1 - Dividing device - Google Patents

Abstract

The invention relates to computing and can be used in the construction of high-speed arithmetic devices. operating with binary codes. The aim of the invention is to improve the speed of the device due to the preliminary assessment of individual bits of the quotient with the subsequent correction (if necessary) correction of the bits already found. The device is built on a matrix principle using the division method with restoring the residue. It includes a matrix of operational modules, blocks for determining the private bit and blocks for controlling the correction. New in the device is the presence of blocks for determining private bits and correction control blocks, as well as the fact that each module is equipped with chains to find a row in the matrix of the bit that generates a transfer to the sign bit. 4 pe. (P

Description

I

The invention relates to computing technology and is intended for use in electronic computing devices.

The aim of the invention is to increase the speed of the device for dividing due to preliminary dressing of individual bits of the quotient with subsequent (if necessary) correction of the bits found.

FIG. 1 a, b shows a diagram of a device for dividing for seven-bit operands with the formation of a five-bit private; in fig. 2 - module layout; in fig. 3 is a block definition circuit diagram; in fig. 4 is a diagram of a correction control unit.

The device for dividing (FIG. 1) contains the modules 1, the bit definition blocks 2 (BOR), the correction control blocks 3 (BEECH), the input bus 4 of the device divider, the input bus 5 of the divisible device, bus 6 and 7, respectively, of the logical unit and logical zero device.

The module (Fig. 2) contains the element NOT 8, the adder 9, the elements AND 10-16, the elements OR 17, 8, the element AND 19, the element NOT 20, the element OR 2).

one

BOR (Fig. 3) contains elements AND 22-26, element OR 27, elements AND 28-30, element NOT 31, elements AND 32-34, element OR 35, element And 36, elements OR 37-39, element NOT 40 , element OR 41, element AND 42, elements NOT 43, 44, elements AND 45-49, elements NOT 50.51 ,, elements OR 52-54 element AND 55, element OR 56, element And 57.

BEECH (Fig. 4) contains the element OR 58, the element NOT 59, the element OR 60, the element NOT 61, the elements AND 62-64, the elements OR 65 and 66.

The modules are arranged in rows and columns of the matrix, with the 1st module being the module located in the i-th row and the J-M column of the matrix. Each BOR relates to one row of the matrix of modules, the i-th PBR refers to the i-th row of the matrix of modules and determines the i-th bit of the quotient. Each BEECH refers to one row of the matrix of modules, and the i-th BEECH refers to the i-th row of the matrix of modules and controls the correction of the i-th bit of the quotient.

The proposed device uses a matrix division method with

, four,

2576372

residue recovery based on the following.

Each row of the matrix of operational elements of the modules subtracts the divider value from the result obtained on the previous line, forms the current remainder. In the form of a double code (bit code and bit bit code) and transmits the result of the string or the generated two-order residual code (if the found value of the current bit of a private is equal to one), or the result obtained on the previous line,

15 i.e. reconstructed remainder (if the found value of the current quotient bit is zero). The value of the current bit of a quotient is determined by the sign of the remainder in the corresponding string, which, in turn, is determined by analyzing the four higher bits of the operands arriving at the operating modules of the line, the number of most significant bits includes the sign of the bit and following there are three senior bits).

The decision on the sign of the remainder (or on the value of the current bit of the quotient) is made according to the following rule: if

30 based on the analyzed bits

five

0

five

0

five

it can be argued that the sign of the residual will be negative, then zero is taken as the value of the sought bit of the private number; if on the basis of the bits being analyzed it can be argued that the sign of the remainder is positive, then the unit is taken as the value for the sought-after bit; If it is not possible to speak of the residual sign on the basis of the higher-order bits, and for the final decision it is necessary to take into account the values of the lower-order bits, then the conditional value O is assigned to this bit private and the transition to the definition of the next bit private is made. I

In the row of the matrix, in which the next private bit is assigned the conditional value O, the bits (from the highest to the lowest) of the bit amount and the transfer are searched to find the critical bit, which is the bit at the end of the bit sequence. Dov, skip transfer (times .J

rows of result, for which S @ nj., 1, where Sj and P-., are bits of the sum and

transfer), in which Sj 1; P: 1 (when detecting a critical discharge in a conditionally reliable discharge, a single value is set, the size of the group is determined by the critical discharge number in the residual code) Each module adds three single-bit digits to its inputs, transferring sums to its outputs and the transfer or the result of the addition (if there is a signal at its first information input), or the sum and transfer from the second and third information inputs (if there is no signal at its first information input), In the latter case residue recovery. In addition, the module, in the presence of a signal at the first information input, generates a signal at the output of the critical discharge if S 1 and P., K Sjnj + occur in the module as a result of the addition. P (nj, - bitwise sum and transfer, formed at the outputs of the adder 9), or a signal at the output of the analysis of the critical discharge, if S, ® P, - c 1. In addition.

if s; ® P-4 1. J

the signal at the output of the critical bit is canceled when

A second control input to the module appears.

BEECHES are used to determine the bits of the quotient in which the values of the initial values found are changed.

discharges private. At the same time, the beacon of the first received

the information input, propagates the signal of the end-to-end critical time series (TFR) to all the BEECTS belonging to more senior bits of the private. The TFR signal is perceived by the BEECH group from (i-l) -ro to the K-th bit, where K is the first bit, starting from the i-ro BEEC of which the critical bit analysis (AKP) signal has. Correction blocks from i-ro to (K + 1) -th block the signals at their outputs of blocking the unit, and the Kth block - the SI unit generation unit. Thus, conditions are formed for the inversion of the bits of the entire group from bit i to bit K. In addition, the blocking signal of the unit generates the (i + l) -th beacon. Thus, the signal at the first information input of the i-ro BEECH is formed simultaneously with the signal at the second control input of () -ro BEECH.

637 4

If the i-th ACU receives a signal at the first information input, then the (G + 1) r1-th ACU does not respond to the signal of the end-to-end critical discharge. This is achieved by the fact that the K-th beacon has on its output a blocking correction signal, which extends from (K-l) -ro to the 1st beacon, blocking the response to the signal at its second educational inputs.

BOR forms at its output a private bit value of a private bit based on the analysis of four bits (including the sign bit) of operands arriving at the corresponding row of the matrix. In those cases when, based on the analysis of these higher bits, it is impossible to make a conclusion about the sign of the future (future residue), a zero value is assigned to the discharge value and a signal at the output of the critical discharge analysis is computed.

The presence of the signal of the first blocking or blocking by the critical discharge in i-M BOR blocks in this BOR accounting of the sum and transfer. The presence of a zero-blocking signal blocks the inclusion in the i-M block of determining the discharge of particular unit values from the transfer outputs and the sum (i-l) of the 1st module.

If the operands arriving on the i-th row of the matrix are such that if they are added, the sum will be obtained, .ud

letvor yutsa condition. " “.

(S ,, i® P,.) (8,., ®П.) HPZ; I, where S; j, e. - respectively, the sum and transfer, formed at the output of the adder 9 j, i-ro module;

HPZ; - the initial value of the bit private, formed by the i-m BOR private.

I The first i-ro blocking signal of the BLB Private BL1 is generated when the condition

BL1;

+

"Ss.i S.

SI.M (, 4). ,,;)

P

t:

ABOUT.

The signal at the output of the zero blocking BLO i-ro BOR is formed when the condition

BLO; BL1; BLKR ((S. + P.) +

 tn - S,; nj) О, where BL1, BLKR - value of signals, respectively, at the output of the first blocking and at the first control input i-ro BOR private.

The proposed device works as follows.

In the initial state, a signal is sent to the bus 6 of the logical unit, to the input 5 of the dividend and to the input 4 of the divider the cooTBeTCTBeHHcf code of the dividend and the reverse code of the divider are fed. The division operation in the proposed device is performed over normalized positive operands (the divisor and the dividend are not less than 0.5 and less than 1.0)

The fractional part of the operands is fed to the modules of the first line and is added together. At the same time, the start four bits of the operands are sent to the 1st BOR, which, without waiting for completion of the addition in its own row of the matrix (in this case, the 1st), performs the determination of the value of the first bit of the private ). If based on older

bit sums and bitwise shifts will be generated for which

S.;, - P,.; 0; 5 ,,; П ,,; one.

5 In addition, this signal is generated when there is a signal at the first control input of the i-ro BOR private. The signal at the zero-block output prohibits taking into account the unit values of the first and

10 of the second bits of the information input (i.e., SO and P1) in the analysis of the higher bits of the operands to decide on the value of the bit of the private. The signal at the fifth control input inhibits the inclusion of single values in the third and fourth bits of the information input (i.e., blocks S1 and P2). Codes from the outputs of the modules first

the rows come with a shift by one bit of the operands cannot be set 20 bits to the left (towards the older ones, the remainder,, and, therefore, the digits) to the second row of the matrix, adding the bit of the private, then The codes of the four most significant bits of the small amount and the transfer arrive at the information input BOR of a part of the 25 second line. Line modules form the sum of the

thirty

the row is assigned the value O and a signal is generated at the output of the analysis of the critical discharge. If the bit private is set to 1, then a signal appears at the output of the bit private. In addition, if the found bit of a private is equal to one, then the BOR of a private can generate signals at its outputs of zero block and first block. The signal of the first block is generated when the decision on the sign is made: on the basis of two significant 1x digits, the sum generated in the first line, i.e. the three significant bits of the operands are such that the first three significant bits of the amount received will satisfy the condition

40

the inputs of the operands, and the BSB of the private determines the value of the next bit, producing a corresponding signal. The process then proceeds as it did for the first line.

If there is a signal at the output of the 1st BOR private on the outputs of the modules of the first row of the matrix, the results of summation from the corresponding outputs of the adders 9 modules, i.e. current balance. If the signal at the output of the BOR private is absent, the recovered modules are transferred to the outputs of the modules of the first row of the matrix (for the first row, the dividend).

Where

,; S ,. P

SOH

+ P,

If there is a signal at the output of the 1BOR private on the outputs of the modules of the first row of the matrix, the results of summation from the corresponding outputs of the adders of the 9 modules, i.e. current balance. If the signal at the output of the de BOR private is absent, the output of the modules of the first row of the matrix is transferred to the reconstructed (for the first row, the dividend).

If some i-th BOR private

P,,; P,;, P ,.

, „0; S, i @ n ,,. one;

,,; .

- bitwise the sum of the sign bits of the operands; bit-wise transfers, form-45, at its output, analyzed in the adders 43, respectively, by the first and third modules of the i-th row;

Sj; - the value of the one-time sum of the $ 0 balance formed on the adders of the first and. second modules of the corresponding row of the matrix.

The signal at the output of the zero blocking-55 ki is overlaid when there is a signal of the first lock or when the operands are such that when the signal is summed up critical, the specified signal goes to the corresponding input of the i-ro BEEC and a signal appears on its output lock correction. This signal arrives at the third control input (i -) - ro of the BEECH, which appears at its output and propagates further to 1-g of the BEECH of the particular.

When generating the i-th BOR of a private signal at its output of the analysis of the critical signal discharge, two cases are possible.

bit sums and bitwise shifts will be generated for which

S.;, - P,.; 0; 5 ,,; П ,,; one.

In addition, this signal is generated when there is a signal at the first control input of the i-ro BOR private. The signal at the output of the zero block prohibits taking into account the unit values of the first and

the second bits of the information input (i.e. SO and P1) when analyzing the higher bits of the operands to decide on the value of the bit private. The signal at the fifth control input prohibits the inclusion of single values in the third and fourth bits of the information input (i.e., blocked S1 and P2). Codes from the outputs of the modules first

the inputs of the operands, and the BSB of the private determines the value of the next bit, producing a corresponding signal. The process then proceeds as it did for the first line.

If there is a signal at the output of the 1st BOR private on the outputs of the modules of the first row of the matrix, the results of summation from the corresponding outputs of the adders 9 modules, i.e. current balance. If the signal at the output of the BOR private is absent, the recovered modules are transferred to the outputs of the modules of the first row of the matrix (for the first row, the dividend).

If some i-th BOR private

 To generate a signal at its output of the analysis of the critical discharge, then the specified signal is fed to the corresponding input of the i-ro BEAC and a signal appears at its output of the correction lock. This signal arrives at the third control input (i -) - ro of the BEECH, which appears at its output and propagates further to 1-g of the BEECH of the particular.

When generating the i-th BOR of a private signal at its output of the analysis of the critical signal discharge, two cases are possible.

in the remainder formed on the 1st line, there is no critical bit. In such a situation, the appearance of the signal of the analysis of the critical bit does NOT affect the further course of the division process.

In the remainder formed on the i-th line, there is a critical discharge, i.e. such bit j for which the condition is satisfied

P.,,,; Sj; one; P, „,; @ S ,,; 1 for all K, change yugchis from 1 to j-i

When a critical-bit analysis signal is present, the signal from the BOR output of the critical quotient goes to the 3rd module (to the first control input, it appears at its critical-discharge output, and so it goes to the j-ro module. On entering the jth module i-th line, this signal is generated by the signal at the end-to-end critical discharge output of this module, which is transmitted to the input (jt), () -ro module, from the end-to-end critical discharge output of which the signal goes to the corresponding input (J-2 ), (i + 2) -ro module, etc. up to 3, (j + i-3) -ro module, from end-to-end critical output of which the critical discharge signal is fed to the first control input of (j + i-1) th VOR and to the first information input (i + j-3) -ro of the beacon of the private. In addition, it goes to the second control the input (j + i-2) -ro of the BEECH of the quotient. As a result, the output of the through critical discharge (i + j-3) -ro of the BEECH of the particular appears the signal that arrives at the corresponding input (i + j-4) - ro BEECH and further extends to the 1st BEECH. The end-to-end critical discharge signal is not perceived by the 1- (1-1) th private BEECH, since their third control to these inputs contains signals due to the signal at the first control input of the i-ro private BEECH. Thus, the length of the group of bits of the quotient is specified, in which the already found bits of the quotient are corrected. The correction consists in inverting these bits. This is achieved due to the following: the i-th ACK at its output of generating a unit generates a signal that arrives at the third control input of the i-ro BOR private, which causes a signal at the discharge output of the Part576378

who In (i + l) - (i + j-2) -x BEECH, there are signals at the second information inputs or at the second control inputs of the own blocking of one and there are no signals at the first control and at the first information inputs. Therefore, at the outputs of the blocking unit of these correction blocks, signals appear that

10 are fed to the second control inputs of the corresponding BSR, which causes the elimination of the signal at their outputs of the private discharge.

Invert Bit Value

The 15 quotient in the above described group results in the remainder obtained in the i-th row being transmitted through the (i + 1) - (j + i-2) -e rows of the matrix and arriving at the () -th row. Starting from this row of the matrix, the determination of the remaining quotient bits continues. It should be noted that the presence of a signal at the first control input ;, (j + i-l) -ro of the block defined by the 5 NIN bits blocks accounting for this block of bits SO, П1, arriving at the information inputs of these blocks.

The result is taken from the discharge outputs of the private units for determining the bits of the device for dividing.

Claims (1)

Invention Formula A device for dividing, containing a matrix of n rows and m columns (n is the size of the private, m is the size of the operands), each of the modules contains an adder, the first and second elements are AND, the first element is OR, and the first element is NOT, the first element being The NOT module is connected to the first input of the first element I of the module and is the first information input of the module, the output of the first element I of the module is, connected to the first input of the first element of the OR module, the second input of the first element of the OR module connected to the output of the second element of the AND module, the first The second input of the second element of the module is connected to the output of the first element of the NOT module, the first, second, and third information inputs of the module adder are the second, third, and the number of information inputs of the module, the sum totalizer output of the module is connected to the second input of the first element of the module, output the transfer of the modulator adder is up to the complementary transfer output of the module, the first information input of the module adder is combined with the second input of the second element AND of the module, the output of the first element OR of the module is the output of the sum of the module, the output of the sum of the module of the K-th column of the Nth row of the matrix (K 2,3, .. ,, t; N 1,2, ..., p-) is connected to the second 15 information input (Kl) -ro pillars - 10 dam first and fifth elements AND the (H + 1) -th row of the matrix, the transfer output of the K-th column of the N-th row of the matrix is connected to the fifth information input of the module ( Kl) -ro column of the Nth row of the matrix, the second and third informational inputs of the modulus of the tth column of the pth row of the matrix (p 2,3, ..., n) are connected respectively to the buses of the logical zero and the logical unit of the device, the first the information input of the modulus of the t-th column of the pth row of the matrix is connected to the first information input of the s-ro module of the pth row of the m the matrix {S 1, 2, .. ,, m-l), the first informational and modulation input F-ro column in the first row of the matrix (F 1, 2, ..., n) connected to the first informational-1 input to the modulus of the t-th column of the first row of the matrix, the second information input of the F-ro module of the first row of the matrix of the matrix is connected to the F-th bit of the input bus of the device divider, the third information - 25 thirty the third element OR module, the output of the third element OR module connected to the first input of the seventh element AND module, the third input of the seventh element And module connected to the output of the second element NOT module, the input of the second element NOT module connected to the output of the fifth element And module, output the second element OR module is the transfer output of the module, the first and second inputs of the second element OR module are connected respectively to the outputs of the fourth and third, about the elements AND module, the output of the seventh element AND module is the code of the analysis for the critical discharge of the module, the output of the fourth element OR of the module is the output of the critical discharge of the module, the first input of the fourth element of the OR module is connected to the output of the sixth element of the AND module, and the second input of the fourth element of the OR module is the second control input of the module, and the the input of the modulus of the first column of the first W the transfer of the modulus of the K-th column of the N-th matrix rows are connected to the logic unit of the device, the fourth information input of the F-ro module of the M-th row of the matrix is connected to the F-th bit of the input bus of the device divider, characterized in that, in order to improve speed, n blocks are added to the device definitions of the bit and n blocks of the correction control, and in each matrix module five additional AND elements, three OR elements and the NOT element are additionally entered, the first input of the third element AND the module is connected to the second information input of the adder and the module, the second input of the third element And the module is connected to the first input of the second element And the module, the first input of the fourth element And the module is connected to the first inputs of the third element SH, fifth and sixth elements And the module is the fifth the information input of the module, the second input of the fourth element And the module is connected to the input of the first element NOT the module, the second input of the sixth element And the module is connected to the second input of the seventh element And the module and is the first controlling input of the module, the third input of the sixth element And the module connected to second entrance am of the first and fifth elements And third element OR module, output of the third element OR module connected to the first input of the seventh element AND module, third input of the seventh element AND module connected to the output of the second element NOT module, input of the second element NOT module connected to the output of the fifth element And module, output The second element OR of the module is the transfer output of the module, the first and second inputs of the second element OR of the module are connected to the outputs of the fourth and third, respectively. About the elements of the module, the output of the seventh element of the module AND is the code analysis and the critical discharge of the module, the output of the fourth element OR of the module is the output of the critical discharge of the module, the first input of the fourth element of the OR module is connected to the output of the sixth element of the AND module, and the second input of the fourth element of the OR module is the second control input of the module, and you matrix rows are connected to the third information input of the module (KI) -ro of the column (M + 1) -th row of the matrix, first - “- the control input of the module of the A-th column of the N row of the matrix (A 4,5, .. ... t) is connected to the output of analysis of the critical discharge of the module (AI) -ro of the column of the Nth row of the matrix, the output of the critical discharge of the module of the Ath column of the Nth row of the matrix is connected to the second control input of the module (A-) column of the (N + l) -th row of the matrix, the first control input of the module of the third column of the Nth row of the matrix is connected to the output of the analysis of the critical bit of the N-ro block neither the bit nor the first input of the N-ro correction control unit, the output of the critical bit of the third column of the Nth row of the matrix is connected to the first information input of the N-ro control correction unit, to the second control input (N +) - ro of the correction control unit and to the first control input of the (N + 2) -ro block for determining the discharge, the discharge output of the private p-th block for determining the discharge is connected to the first information module of the F-column module of the pth row of the matrix, the first and second bits dy of the information input of the pth block for determining the discharge under are connected respectively to the output of the sum and the transfer output of the module of the first column (p-1) -th row of the matrix, the third and fourth bits of the information input of the p-th bit definition block are connected to the third and third information inputs of the module of the first column p- the second row of the matrix, the fifth, sixth and seventh bits of the information input of the p-th block of determining the discharge are connected respectively to the second, third and fourth twisted information inputs of the module of the second column of the p-th row of the matrix, the eighth, ninth and tenth bits informational of the p-th bit definition block, respectively, are connected to the second, third and even vertical information inputs of the third column module of the pth row of the matrix, the output of the private first block definition bits of the sub-keys to the first information input of the first column module matrix rows, the third bit of the information input of the first block of definition of the bit is connected to the second information input of the module of the first column of the first row of the matrix, the fifth and seventh bits of the information input of the first block is defined bits are connected respectively to the second and fourth information inputs of the first column module of the second row of the matrix, the eighth and tenth bits of the information input of the first block of the bit definition are connected respectively to the second and fourth fy information inputs of the first column module of the third row matrixes, blocking outputs of the unit, and the inputs (Ml) -ro of the correction control block, quarter control input of the M th bit determining block is connected to the output of the own generation of the M th control block by the correction, the fifth and sixth control inputs of the first bit definition block are connected to the bus a logical unit of the device, the fourth control input of all the correction control blocks is connected to the bus of the logical unit of the device, the outputs of the first and zero locks of the M th bit block Yes, they are connected respectively to the fifth and sixth control inputs of the () th discharge detection unit, the discharge definition block contains ten elements OR, twenty AND elements and six NE elements, the first input of the first element OR b The bit definition loop is the fourth control input of the bit detection unit, the second input of the first element OR the bit detection unit is connected to the output of the first element AND the bit definition unit, the first input of the first element, And the bit definition unit is connected to the output the second element i of the bit definition block, the first inputs of the third and fourth elements OR the bit definition block and the input of the first element are NOT the bit definition block, the output of the first element of the NOT block of the bit definition is connected to The first input of the second element AND the bit definition unit, the second input of the second element AND the bit detection unit is connected to the output of the second element NOT, the nepBEJM inputs of the third, fourth and fifth elements AND block of the definition of the discharge and the second input of the first element AND block of the definition of the discharge , the input of the second element of the NOT block of the definition of the discharge is the second lane of the main input of the block for determining the discharge, the input of the third element of the HE of the block for determining the discharge is the unit of the unit of the Mth block is controlled by the first control input of the block No corrections are connected to the second and third control inputs of the M-th determination block — the discharge, the through-pass critical discharge outputs, and the correction locks of the M-th control block — are more correctly connected to the second information and third control inputs (Ml) -ro the control input, the quarter control input of the M-th bit determining unit is connected to the output of the own generation of the unit of the M-th block of the control control unit, the fifth and sixth control inputs of the first bit determining unit and the fourth control input of all the correction control blocks is connected to the bus of the logical unit of the device, the outputs of the first and zero locks of the M-th bit determining block are connected to the fifth and sixth control inputs of the () -th block, respectively definition of the bit, with the block determining the bit containing ten elements OR, twenty elements AND and the six elements NOT, the first input of the first element OR of the block determining the bit is the fourth control input of the block The discharge bit, the second input of the first element OR of the bit definition block is connected to the output of the first element AND the bit definition block, the first input of the first element, AND the bit definition block is connected to the output of the second element OR of the bit definition block, the first inputs of the third and fourth of the OR elements of the bit definition unit and the input of the first element of the NOT block of the definition of the discharge, the output of the first element of the NOT block of the definition of the discharge is connected to the first input of the second element AND the block of the definition of the discharge, the second input of the second of the second element and the block for determining the bit is connected to the output of the second element NOT, the nepBEJM inputs of the third, fourth and fifth elements AND block determining the discharge and the second input of the first element AND block determining the discharge, the input of the second element NOT block determining the discharge is the second Lying at the main input of the bit definition unit, the input of the third element of the NOT bit definition block is the first control input of the block bit detection, the first input of the sixth element AND the bit determining unit is the sixth control input of the bit determining unit, the first input of the seventh element And the bit determining unit is the fifth control input of the bit determining unit, the output of the fifth element OR the bit definition unit is connected to the second input of the fourth, the first inputs of the eighth and ninth elements AND the bit definition unit and the first input of the sixth OR element of the bit definition unit, the first input of the fifth OR element of the bit definition unit is connected to the tenth output and the second the input of the third element AND the bit definition unit, the second input of the fifth element OR the bit definition unit is connected to the output of the eleventh and the third input of the third element AND the bit definition unit, the output of the seventh element OR block ka definition of discharge is connected to the third input of the fourth and the first input of the twelfth elements AND block definition of discharge, the output of the eighth element OR block of definition of discharge is connected to the second inputs of the fifth, twelfth and ninth elements AND block definition of discharge, first, second and the third inputs of the eighth SHS element of the bit definition unit are connected to the outputs of the thirteenth, fourteenth and fifteenth elements, respectively; AND the bit definition unit, the first, second and third inputs of the ninth element OR block and the bit definitions are connected respectively to the outputs of the eighth, twelfth and ninth elements AND the bit definition block, the fourth input of the ninth element OR of the bit definition block is connected to the output of the sixteenth element And the bit definition block and the second input of the sixth element OR of the definition block the bit, the third input of the nth element AND of the bit definition unit is connected to the output of the sixth element W of the bit definition unit, the fourth input of the fifth element AND of the bit definition unit is connected to the output of the tenth OR element of the bit definition unit and the second input of the eighth element and the block for determining the discharge, the third input of the second element and the block for determining the discharge is under- t is connected to the output of the fourth element of the NOT block for determining the bit, the fourth input of the second element AND of the block for determining the discharge is connected to the second input of the third element OR of the block for determining the discharge and the output of the fifth element of the HE block for determining the discharge, the second input of the fourth element of the OR block bit detection is connected to the fourth input of the first element OR of the bit definition unit, the output of the fourth element k of the bit definition unit and the input of the fifth element of the NOT bit definition unit, the third input of the fourth element OR of the bit definition block is connected to the third inputs of the first and third elements OR of the bit definition block, the output of the third element AND the bit definition block and the input of the fourth element of the NOT block of the discharge definition block, the output of the sixth element of the HE block of the definition of discharge is connected to the fourth input of the fourth the OR element of the bit definition unit and the fifth input of the second element AND the bit definition unit, the input of the sixth element of the NOT bit definition unit is connected to the output of the fifth element AND the bit definition unit the first input of the first element OR of the bit definition unit, the first input of the seventeenth element AND the bit definition unit is connected to the output of the third element W of the bit definition block, the second input of the seventeenth element AND the bit definition unit is connected to the output of the third element, NOT the definition block bit and the second inputs of the sixth and seventh elements AND the block definition of discharge, the output of the first element OR block definition of discharge is the output of the discharge of the private block definition of discharge, the output of the fourth element OR of the bit detection unit is the output of the first lock of the bit detection unit, the output of the seventeenth element AND of the bit detection unit is the output of the zero block of the bit definition unit, the output of the second bit AND element of the bit detection unit is the output of the critical discharge analysis of the definition unit bit, the first and second inputs of the second element OR of the bit definition unit have the first and second bits of the information block of the bit definition unit, the first inputs of the ninth one, one The eighth, eighteenth, nineteenth, twentieth, thirteenth, fourteenth and fifteenth elements AND the bit definition block are the third, fourth, fifth, sixth, seventh, eighth, ninth and tenth respectively. bits of the information input of the bit definition block, the first input of the twentieth element AND the bit definition block is connected to the second input of the eighteenth element AND the bit definition block and the first inputs of the tenth element OR of the bit definition block and sixteenth element AND bit block, first - vm input of the nineteenth and eleventh element And the block for determining the discharge is connected to the second inputs of the twentieth and sixteenth element B and the block for determining the discharge and the second input of the tenth element OR of the block for determining the discharge and, the first input of the eighteenth NAND block determining discharge is connected to a second input of the nineteenth element and a determination unit discharge and third inputs tenth of OR and sixteenth NAND block determining discharge, yield eighteenth NAND block determining discharge connected to the first to the input of the seventh element OR of the block; the control of the input of the control block for the discharge; the second and third inputs of the seventh element of the OR block for determining the discharge; respectively, are connected to the outputs of the nineteenth and of the twentieth element AND block by determination, the output of the second element AND block lag of discharge, the sixth input of the first element OR of the block for determining the discharge is the third control input of the block for determining the discharge, output of the sixth element AND block of definition of the correction control block, expression is connected to the third input of the first element AND block of the definition of discharge, the output of the seventh element AND block of the definition of discharge is connected to the second inputs of the tenth and eleventh elements of the block of definition of discharge, the second the input of the thirteenth element AND the bit determining unit is connected to the first input of the fifteenth element AND of the correction control unit is the output of the own generation of the unit of the correction control unit, the first input is the third element and the correction control unit the first element AND the block definition is 45 connected to the input of the second element is NOT row, the first input of the thirteenth element And the bit definition block is connected to the second input of the four-fold element And the bit definition block, the second input of the fifteenth element And the bit definition block is connected to the first input of the fourteenth element And the bit definition block, the output of the nine of the OR element of the bit definition block to the sixth input of the second element And the block determining the discharge, the third input of the seventeenth element And the block the correction control unit, the second inputs of the first element AND and the second element OR of the correction control unit and is the first control input of the correction control unit, the first input of the fourth element OR the correction control unit is connected to the second input of the second and third input of the first AND elements 55 of the correction control block and is the second information input of the correction control block, the second input of the fourth element OR block bit detection is connected to the output of the fourth SHUI element of the definition block, and the correction control block contains four OR elements, three AND elements and two NOT elements, the output of the first AND element of the correction control block is connected to the first input of the first OR element of the control unit the correction is the output of generating the unit of the correction control block, the first input of the first element AND of the correction control block is connected to the first input of the second element AND the correction control block and the output of the first element OR of the correction control block, the output of the second element OR of the correction control block is the output of the correction block of the correction control block, the first input of the second element OR of the correction control block is connected to the input of the first HE element of the correction control block and is trilling correction, the output of the first element NOT of the Correction Control block is connected to the second input of the first element OR of the correction control block of the correction block is connected to the first th input of the third OR correction control unit, the output of which is output lock edi the stroke of the fourth element OR of the correction control block is the output of the through critical discharge of the block correction control, third output- I its element AND correction control block is the output of the own generation of the correction control block unit, the first input of the third element And the correction control block connected to the input of the second element is NOT the correction control block, the second inputs of the first element AND the second element OR the correction control block and is the first control input of the correction control block, the first input of the fourth element OR the correction control block is connected to the second input of the second and third input of the first AND elements the correction control block is the second information input of the correction control block, the second input of the fourth element OR block 17 control unit is connected to the second input of the third element AND and is the first information input of the correction control unit, the second input of the third element OR of the correction control unit is the second control input of the correction control unit, the fourth control 12 763718 The input of the correction control unit is combined with the fourth input of the first element AND and the third input of the second element AND of the correction control unit; J, the fourth input of the second element AND of the correction control unit is connected to the output of the second element NO of the correction control unit. A / g / a Ty f Phi1.2 62 Sh 66 Compiled by S. Silaev Editor I. Rybchenko Tehred I., Popovich Proofreader I. Muska   1 11 I g and 111.1 I --- 1 and -1 –sh-g - LL Yui I - - - - 11- IL1 - 1 Order 4957/47 Runs .671Subscription VPSHPI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4