JP2592681B2 - Cell synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for digital communication. In particular, the present invention relates to a method of transmitting a cell in which a header is added to an information sequence as an information unit. For more information, see CRC (cyclic redunduncy c
hech) Since the data string with the bit added is divisible by the CRC operation, the CRC bit is added to the header and transmitted.
The present invention relates to a cell synchronization circuit that establishes cell synchronization by regarding a data sequence divisible by a CRC operation on a receiving side as a synchronization pattern.

The present invention enables high-speed operation of a cell synchronization circuit by pipeline processing of a CRC operation, and also facilitates integration.

[Conventional technology]

2. Description of the Related Art In order to perform error detection and error correction of a received signal, a method is known in which a CRC bit is added to an information signal for transmission.

The CRC bit is given as a remainder when the information signal is divided by the generator polynomial. In order to obtain m CRC bits, an m-th generation polynomial is used. The data string to which the CRC bit is added is the same generator polynomial or a polynomial obtained by factoring the polynomial, for example, m−m when the m-th generator polynomial can be separated into two generator polynomials of the first and m−1 orders.
All bits have a property of “0” (divisible) by a CRC operation (division) using a first-order generator polynomial.

FIG. 3 shows an example of using the CRC bit. In this example, when a cell in which a header is added to an information sequence is used as a transmission unit, a signal indicating a destination and a CR obtained from the signal are used as the header.
This uses C bits.

When a cell is transmitted, if a data string to which a CRC bit is added is used as a header, this can be used for cell synchronization. In other words, when the header length is n bits, if there is no bit error on the transmission path, the CRC
Since the remainder obtained by dividing the data sequence having a code length of n bits including bits by the CRC operation circuit becomes all bits "0", this pattern is regarded as a cell synchronization pattern and cell synchronization is achieved.

FIG. 4 is a block diagram showing an example of a CRC operation circuit. Here, generator polynomial shows a general example of a case of ^{x 8 + x 2 + x +} 1. This circuit comprises cascaded flip-flops 30-1 for sequentially shifting input data.
30-8, and flip-flops 30-1, 30-2 and 30
Exclusive OR circuit 31 inserted at each input of -3
-1 to 31-3, and the flip-flop 30-
1 to 30-8 operate with the clock of the input data.

Here, the code length n is assumed to be 40 bits. First, if the contents of the flip-flops 30-1 to 30-8 are all set to "0", the data arranged in the flip-flops 30-1 to 30-8 are subjected to the CRC operation when the input of the 40-bit code is completed. Will be the remainder. The remainder in which all bits are "0" is used as a cell synchronization pattern.

In this system, a 1-bit immediate-shift cell synchronization circuit is usually required to shorten the cell synchronization recovery time. That is, it is necessary to execute the CRC operation for the code length n bits within one clock of the clock of the input data string. For this purpose, the fact that the data finally left in each of the flip-flops 30-1 to 30-8 in the above operation is the accumulated value of the CRC operation for each bit of the 40-bit length code is used. That is, if each bit of the 40-bit length code is represented by D _{1 to} D ₄₀ , the flip-flop 3
Data Z _{1 to} Z ₈ finally remaining in 0-1 to 30-8 are Becomes Here, “+” indicates an exclusive OR. FIG. 5 is a block diagram of a conventional cell synchronization circuit using the equation (1).

The cell synchronization circuit includes a 40-bit shift register 1, an exclusive OR circuit 2, a latch circuit 3, an OR circuit 4, AND circuits 5, 6, a frame synchronization protection circuit 7, a flake counter 8, and an inverter input. AND circuit 9 with
Is provided. Input data 100 and a clock 200 extracted from the input data 100 are input to the shift register 1. The same clock 200 is supplied to the latch circuit 3 and the AND circuit 9.

The shift register 1 shifts data by the clock 200.

Exclusive OR circuit network 2, performs an operation of (1), and outputs the data Z ₁ to Z _8. In the equation (1), D _{1 to} D ₄₀ correspond to the outputs of the flip-flops F 1 to F ₄₀ in the shift register 1.

The frame synchronization protection circuit 7 is constituted by, for example, a reset counting type circuit. In the reset counting type circuit, when "1" is continuously input, the internal state becomes the set state, and the output thereof becomes "1" which indicates the out-of-frame state. When “0” is continuously input,
The internal state is reset, and its output becomes "0" indicating the frame synchronization state.

Here, assuming that the output of the frame synchronization protection circuit 7 is "1", the synchronization recovery operation of this cell synchronization circuit will be described.

First, the shift register 1 shifts input data by a clock and outputs new 40 data. This output is subjected to a CRC operation in the exclusive OR circuit network 2 and the obtained data Z _{1 to} Z ₈ are output to the latch circuit 3. The latch circuit 3
The data Z _{1 to} Z ₈ are taken in at the next clock. At the same time, the shift register 1 shifts the data, and the exclusive OR circuit 2 performs a CRC operation on the new 40 bits.

When the input data of the exclusive OR network 2, that is, the content of the shift register 1 is a correct 40-bit length code including a CRC bit (when a header is input), or a data sequence of the same series Is the data Z _{1 to} Z ₈
Are all "0". However, at most other times, at least one of the data Z _{1 to} Z ₈ is “1”, and the output of the OR circuit 4 is “1”.

When no frame pulse appears in the frame counter 8, the output of the AND circuit 5 becomes "0", so that the output of the AND circuit 6 becomes "0", and a clock is obtained at the output of the AND circuit 9. The frame counter 8 continues the counting operation. When a frame pulse appears at the output of the frame counter 8, the output of the AND circuit 5 becomes "1". Therefore, the output of the OR circuit 4 is output from the next input clock by the AND circuits 6 and 9 by the AND circuits 6 and 9. The counting operation is stopped until “0” is reached, and the state of outputting the frame pulse is maintained.

If the contents of shift register 1 are
When the code has a bit length, the logical sum circuit 4
Becomes “0”, at which point cell synchronization is restored,
The frame counter 8 starts counting operation by the next clock. Thereafter, the OR circuit 4 is used at the frame pulse position.
Is "0", "0" is continuously input to the frame synchronization protection circuit 7, and the frame synchronization protection circuit 7
Becomes synchronous after the reset state.

In this circuit, the latch circuit 3 is used, but the output of the exclusive OR circuit 2 can be directly input to the OR circuit 4.

[Problems to be solved by the invention]

In order for the conventional cell synchronization circuit shown in FIG. 5 to operate normally, the delay between the input of the clock to the shift register 1 and the output of the data and the delay by the exclusive OR circuit 2 are considered. The sum must be less than one clock. When the latch circuit 3 is not used, the value obtained by adding the delay by the OR circuit 4 and the AND circuits 5 and 6 to the sum of the delays described above must be less than one clock.

However, in order for the exclusive OR circuit to perform the CRC operation at a time, it is necessary to pass the signal through the exclusive OR circuit connected in multiple stages. In the example shown in FIG. 5, the signal passes through an exclusive OR circuit having a maximum of five stages. The delay time per one stage of the exclusive OR circuit is equal to or longer than the delay time of the flip-flop which is a component of the shift register and the latch circuit. Therefore, this cell synchronization circuit is not suitable for high-speed operation.

However, it is possible to increase the speed of the cell synchronization circuit shown in FIG. 5 by providing a latch circuit in the middle of the exclusive OR circuit network. However, the amount of hardware increases for that purpose. In the example shown in FIG. 5, the hardware scale of the shift register 1, the exclusive OR circuit network 2 and the latch circuit 3 is assumed to be the same arithmetic circuit, and 89 exclusive OR circuits and 48 flip-flops are used. It is. In order to provide a latch circuit between the fourth and fifth exclusive OR circuits of the exclusive OR network 2 for speeding up, 11 flip-flops are required. In order to provide a latch circuit between the third and fourth exclusive OR circuits to further increase the speed, nine more flip-flops are required.

Further, such an exclusive OR circuit has a drawback that the wiring design becomes difficult when integrated since the connection configuration becomes complicated.

An object of the present invention is to solve the above problems and to provide a cell synchronous circuit which can operate at high speed and is easily integrated.

[Means for solving the problem]

In the cell synchronization circuit of the present invention, the CRC operation means has the same configuration in which an n-bit data sequence to be operated is divided in the input order, and a partial data sequence and a remainder by a generator polynomial for each of the input partial data sequences are obtained. For a plurality of CRC partial calculation means, and for each of the second and subsequent CRC partial calculation means of the plurality of CRC partial calculation means, the remainder obtained in the previous stage and the remainder obtained in that stage are calculated by Means for calculating the remainder of the plurality of input partial data strings by the generator polynomial.

That is, CRC partial operation means for performing parallel processing are cascaded via a latch circuit, and the CRC operation is pipelined.

The cell synchronization circuit of the present invention transmits a cell in which a header having a code length of n bits including an m-bit CRC bit is added to an information sequence as a unit, and detects and detects an error of a signal in the header by the CRC bit on the receiving side. In the transmission method for performing the correction, it is used to establish cell synchronization using the CRC bit.

The CRC partial calculation means respectively uses the m-th order generator polynomial used for obtaining the CRC bits on the transmitting side, or m-th order when this m-order generator polynomial can be separated into the first-order and m-1 order generator polynomials. A CRC operation is performed using a first-order generator polynomial. Hereinafter, the degree of the generator polynomial used by the CRC partial calculation means is represented by “m ′”.

Here, the number of bits processed by each of the CRC partial calculation means is represented by a parallel processing number l, and this value is assumed to be the same for each CRC partial calculation means. However, 1 ≦ l <n. Further, the quotient obtained by dividing n by 1 is [n / l], and the remainder is R.

The data string of the received cell has a length of [n / l] (l-1) +1 when n is divisible by l, and a length of [n / l] (l-1) + R when n is not divisible by l. Is input to the shift register. This shift register operates with the clock of the data string.

A CRC partial operation is performed on each output of the first to first stages from the top of the shift register, and the output of m 'bits is input to the m' flip-flops of the first stage using the clock. A CRC parallel partial operation is again performed on each output of the m ′ flip-flops of the first stage and each output of the 1st to 2l−1th stages from the top of the shift register, and the m ′ outputs are each processed by 2 The clock is input to the m ′ flip-flops in the stage.

Similarly, from the top of the shift register, [n / l] (l
-1) -1 + 2 to [n / l] (l-1) +1 output of each stage and (n / l) -1 each output of m 'flip-flops in the CRC parallel partial operation Then, the m 'outputs are input to the m' flip-flops in the [n / l] stage with the above clock.

If n is not divisible by l, then [n / l] (1-1) -1 to [n / l] (l-l)
1) A CRC parallel partial operation is performed on each output of the + R stage and each output of the m ′ flip-flops in the [n / l] stage, and the m ′ outputs are respectively [n / l] +1 stages The clock is input to the m'th flip-flops of the eye with the clock.

The logical sum of the outputs of the m ′ flip-flops of the final stage obtained in this way is obtained, and the logical product of this logical sum and the output (frame pulse) of the frame counter operated by the clock is protected by frame synchronization. Input to the circuit. When the logical product of this logical product and the output of the frame synchronization protection circuit is "1", the counting operation of the frame counter is stopped for one clock.

(Operation)

In order for the cell synchronization circuit to operate, the delay of each of the CRC partial calculation means for performing the parallel processing may be within one clock. Also, if the number of parallel processes 1 is reduced, the scale of the CRC partial calculation means is reduced, and the delay time is also reduced. Therefore, the operation of the cell synchronization circuit can be speeded up. Further, by appropriately selecting the number of parallel processes, a cell synchronous circuit having a required operation speed can be realized.

If the number of parallel processes is the same, all the CRC partial calculation means have the same configuration. For this reason, design in integration becomes easy.

〔Example〕

FIG. 1 is a block diagram of a cell synchronization circuit according to a first embodiment of the present invention. This example shows a case where the code length n is 40 bits, the generator polynomial of the CRC operation means is x ⁸ + x ² + x + 1, and the number of parallel processes of the CRC partial operation means is 20.

The cell synchronization circuit receives a received cell in which a header including a CRC bit is added to a digital information sequence, and obtains a remainder of a data sequence of the received cell by a generator polynomial equivalent to that used for obtaining the CRC bit. CRC
Exclusive OR circuits 11, 13, and 14 and a latch circuit 12 are provided as operation means, and means for establishing cell synchronization by detecting that the data string is divisible by the generator polynomial from the output of the CRC operation means. , A latch circuit 3, an OR circuit 4, AND circuits 5, 6, a frame synchronization protection circuit 7, a frame counter 8, and an AND circuit 9 with an inverter input.

The shift register 1 is supplied with a data string of the received cells as input data 100, and further receives a clock 200 extracted from the input data 100. The same clock 200 is supplied to the latch circuit 3 and the AND circuit 9.

Here, the feature of the present embodiment is that the CRC operation means divides the input data 100 into a plurality of parts in the input order, and performs exclusive OR operation as a plurality of CRC partial operation means for obtaining the remainder of the generator polynomial in parallel for each of them. Network 11, 13
A latch circuit as means for processing the outputs of the plurality of CRC partial operation means in accordance with the input order and obtaining the remainder of the entire data string by the generator polynomial.
12 and an exclusive OR network 14.

For a circuit configuration for performing CRC calculation by parallel processing, see Parallel Scrambling Techniques for Digital Multiplexers, AT & T Technical Journal, Vol. 65, September / October 1986 (“Parallel s
crambling techniquse for digital multiplexers ", AT
& T technical journal, sep./oct. 1986, Vol. 65) can be obtained in the same manner as the parallelization method of the self-synchronous scrambler.

According to this document, the circuit configuration in the case of a parallel processing number 20 is obtained by determining the T _S ²⁰ from the matrix T _S given by equation (2). T _S ²⁰ is shown in equation (3).

The lower right part of the matrix divided into four parts of equation (2) indicates the next state of each of the flip-flops 30-1 to 30-8 in the CRC operation circuit shown in FIG. For example, the 21st row of the matrix T _S indicates that the next state of the flip-flop 30-1 is the exclusive OR of the input data and the content of the flip-flop 30-8. Similarly, in the 22nd row of the matrix T _S , the next state of the flip-flop 30-2 is the exclusive OR of the content of the flip-flop 30-1 and the content of the flip-flop 30-8, and the 23rd row is the flip-flop. The next state of 30-3 is the exclusive OR of the contents of the flip-flop 30-2 and the contents of the flip-flop 30-8.
The next state of ~ 30-8 is the flip-flop 30-3 ~ 30-7
Is shifted.

Also, when representing the input data D ₁ to D _20, the first 20 columns D ₁
A nineteenth column of D _2, the first column shows each D _20.

Therefore, the flip-flop 30 in the current state
Assuming that the contents of −1 to 30−8 are F _{1 to} F ₈ respectively, the following 20
Flip-flop 30- after bit data is input
The states of 1 to 30-8 are given by Expression (3) obtained by multiplying Expression (2) 20 times. That is, flip-flops 30-1 to 30-30
The contents Z _{1 to} Z ₈ of −8 are obtained from the equation (3). Becomes Here, “+” indicates exclusive OR.

Exclusive OR circuit 11 of the cell synchronization circuit shown in FIG.
In the equation (4), F ₁ = F ₂ = F ₃ = F ₄ = F ₅ = F ₆ = F ₇ =
F ₈ = 0, and D _{1 to} D ₂₀ are 20
This corresponds to the outputs of the flip-flops F1 to F20 up to the first. The exclusive OR circuit 13 has the same circuit configuration as that of the exclusive OR circuit 1 except that its input data is shifted by 19 bits on the shift register 1 (input data is 20 bits). is there. Then, the exclusive OR circuit 14 performs the CR operation on the first 20 bits of data.
Result of the C operation, i.e. the output of the exclusive OR circuit 11 and F ₁ to F _8, the result of CRC calculation for the next 20 bits of data, namely performed operation on an output of the exclusive OR circuit 13. The operation by the exclusive-OR network 14 is, for example, (4)
To explain the Z ₁ of the formula as an example, exclusive for 1,3,5,7,8 bit of the output of the exclusive OR circuit 11 (corresponding to a bit from the top of the latch circuit 12 in FIG. 1) The exclusive OR is obtained, and the exclusive OR with the first bit (D ₄ + D ₅ + D ₆ + D ₁₂ + D ₂₀ ) from the exclusive OR circuit 13 is obtained.

Since the code length is 40 bits, the CRC operation needs to be performed on continuous 40-bit input data. In the present embodiment, each of the exclusive OR circuits 11 and 13 performs a 20-bit operation, and the result is referred to as the exclusive OR circuit.
Process at 14.

That is, the exclusive OR circuit 11 performs a CRC partial operation on each output of the first flip-flop F1 to the twentieth flip-flop F20 of the shift register 1 and inputs the result to the latch circuit 12. At this time, the data of the flip-flops F21 to F39 are
0 to F38, shifted one bit at a time, flip-flop F39
Is input with new data. Exclusive OR network 13
Performs a CRC partial operation on the data of the flip-flops F20 to F39 when new data is input. The distance between the input data positions of the exclusive OR networks 11 and 13 is
19 bits instead of 20 bits.

The exclusive OR circuits 11 and 13 perform a CRC partial operation on new input data at each clock. However, based on the data side, the operation of the exclusive OR network 11 is one clock ahead of the operation of the exclusive OR circuit 13. By storing the output of the exclusive OR network 11 in the latch circuit 12, both timings coincide. The exclusive OR network 14 obtains the remainder of the CRC operation on the entire data string from the output of the latch circuit 12 and the output of the exclusive OR network 13, and outputs the result to the latch circuit 3. Thus, the remainder of the CRC operation is obtained in the latch circuit 3 for each clock.

The operations of the latch circuit 3, the OR circuit 4, the AND circuits 5, 6, the frame synchronization protection circuit 7, the frame counter 8, and the AND circuit 9 are the same as those of the conventional example shown in FIG.

In this embodiment, the latch circuit 3 can be omitted, but in that case, the signal delay time increases.

The exclusive OR networks 11, 13 and
The maximum delay time of 14 is the number of stages of the exclusive OR circuit, which is four stages. Moreover, the shift register 1, the latch circuits 3, 12,
All the hardware amounts of the exclusive OR circuits 11, 13 and 14 are 88 exclusive OR circuits and 55 flip-flops. In the conventional example shown in FIG. The amount of hardware is smaller than when a latch circuit is provided between the fourth and fifth exclusive OR circuits in the OR circuit network.

Further, in the cell synchronization circuit of the present embodiment, the exclusive OR circuits 11, 13 have the same configuration, and the LSI design is easy. Furthermore, since the size of one exclusive OR network is small,
Since the intersection of wiring is reduced and the connection between wiring layers is reduced,
LSI wiring design becomes easy.

FIG. 2 is a block diagram of a cell synchronization circuit according to a second embodiment of the present invention.

This embodiment shows a case where the code length n is 40 bits, the generator polynomial of the CRC operation means is x ⁸ + x ² + x + 1, and the number of parallel processes of the CRC partial operation means is 8. In this embodiment, the code length n is 40
The case where the generator polynomial of bits and CRC calculation is x ⁸ + x ² + x + 1 and the number of parallel processes of CRC calculation is 8 is shown. In this case, since the degree of the generator polynomial is equal to the number of parallel processes, the remainder of the CRC operation on the divided data is the data itself. Therefore, in this embodiment, circuits corresponding to the exclusive OR circuits 11 and 13 in the first embodiment are unnecessary.
Instead, a circuit corresponding to the exclusive OR network 14 is
They are connected in multiple stages with the same configuration. That is, the exclusive OR networks 22, 24, 26, and 28 are respectively connected to the latch circuits 23,
Cascaded via 25 and 27. A latch circuit 21 is provided at an input of the exclusive OR network 22.

The circuit configuration of this embodiment, similarly to the first embodiment is obtained by determining the T _S ⁸ from the matrix T _S. Here, T _S is a matrix for eight parallels. Calculation of T _S ^8, at each stage, for the current state (the output of the previous stage) F ₁ to F ₈ may be obtained an output Z ₁ to Z _8, which is represented by the following formula. _{That, Z 1 = F 1 + F} 7 + F 8 + D 8 Z 2 = F 1 + F 2 + F 7 + D 7 Z 3 = F 1 + F 2 + F 3 + F 7 + D 6 Z 4 = F 2 + F 3 + F 4 + F 8 + D 5 _{Z 5 = F 3 + F 4} + F 5 + D 4 Z 6 = F 4 + F 5 + F 6 + D 3 Z 7 = F 5 + F 6 + F 7 + D 2 Z 8 = F 6 + F 7 + F 8 + D 1 ...... (5) Become. Here, D _{1 to} D ₈ are data serially input from the shift register 1. According to this equation, the maximum number of exclusive OR stages is three, and high-speed operation is possible. The number of required exclusive OR circuits is 84 in total, and the circuit scale is relatively small.

The operation of this embodiment will be described in more detail. Here, S ₁ output signal of the latch circuit 3,27,25,23,21 at time t1, _{respectively, t1, S 2, t1,} S 3, t1, S 4, t1,
S5 _{, t1,} and the output signals of the latch circuits 3, 27, 25, 23, 21 at the time t0 one clock before are S1 _{, t0} , S1 _, respectively.
_{2, t0, S 3, t0} , S 4, t0, S 5, and _t0, the function of the arithmetic processing, except for direct operation between the shift register 1 outputs of the exclusive OR circuitry 28,26,24,22 Assuming that T _S ⁸ is f (), the following equation is established.

S1 _{, t1} = f (S2 _{, t0} ) + f (D29 to D36) S2 _{, t1} = f (S3 _{, t0} ) + f (D22 to D29) S3 _{, t1} = f (S4 _{, t0} ) + f ( D5 to D22) S4 _{, t1} = f (S5 _{, t0} ) + f (D8 to D15) S5 _{, t1} = f (D1 to D8) (6) where f (D29 to D36) is at time t1. This is the output data from F29 to F36 of the shift register 1.
Exclusive OR is not included, only the input order is changed. Further, + indicates an exclusive OR. Although the position of the direct operation with the output of the shift register 1 is performed at the intermediate position of the exclusive OR circuit in the figure, the result of the exclusive OR does not change even if the operation order is changed. The processing related to the remainder of the CRC operation up to the previous stage and the processing for the output of the shift register 1 can be expressed separately.

Similarly, at times t2, t3, t4, and t5, the following equations hold.

S1 _{, t2} = f (S2 _{, t1} ) + f (D30-D37) S2 _{, t2} = f (S3 _{, t1} ) + f (D23-D30) S3 _{, t2} = f (S4 _{, t1} ) + f ( S4 _{, t2} = f (S5 _{, t1} ) + f (D9 to D16) S5 _{, t2} = f (D2 to D9) (7) S1 _{, t3} = f (S2 _{, t2} ) + F (D31-D38) S2 _{, t3} = f (S3 _{, t2} ) + f (D24-D31) S3 _{, t3} = f (S4 _{, t2} ) + f (D17-D24) S4 _{, t3} = f (S _{5, t2} ) + f (D10 to D17) S5 _{, t3} = f (D3 to D10) ... (8) S1 _{, t4} = f (S2 _{, t3} ) + f (D32 to D39) S2 _{, t4} = f _{(S 3, t3) + f} (D25~D32) S 3, t4 = f (S 4, t3) + f (D18~D25) S 4, t4 = f (S 5, t3) + f (D11~D18) S 5 _{, t4} = f (D4 to D11) (9) S1 _{, t5} = f (S2 _{, t4} ) + f (D33 to D40) S2 _{, t5} = f (S3 _{, t4} ) + f (D26 to D33) _{S 3, t5 = f (S} 4, t4) + f (D19~D26) S 4, t5 = f (S 5, t4) + f (D12~D19) S 5, t5 = f (D5~D12) ... (10) Thus, the S _{1, t5} formula (7), (8), (9),
By writing down using (10), the following equation is obtained.

_{S 1, t5 = f (S} 2, t4) + f (D33~D40) = f 2 (S 3, t3) + f 2 (D25~D32) + f (D33~D40) = f 3 (S 4, t2) + f ^{3 (D17~D24) + f 2 (} D25~D32) + f (D33~D40) = f 4 (S 5, t1) + f 4 (D9~D16) + f 3 (D17~D24) + f 2 (D25~D32) + f ^{(D33~D40) = f 5 (D1~D8} )) + f 4 (D9~D16) + f 3 (D17~D24) + f 2 (D25~D32) + f (D33~D40) ...... (11) this equation, The exclusive OR networks 22, 24, 26, and 28 arranged in a pipeline form output the latch circuit 3.
This indicates that the remainder for the 40-bit data has been obtained. Note that f ⁵ (), f ⁴ (), f ³ (),
f ² (), respectively, showing a ^{_{T S 40, T S 32,}} T S 24, T S 16.

Although the amount of hardware required in the present embodiment is increased as compared with the first embodiment, the maximum delay amount of the CRC partial operation is equivalent to three exclusive OR circuits. Therefore, it is suitable for high-speed operation. Further, since the exclusive OR circuits 22, 24, 26, and 28 have the same circuit configuration, the LSI design is facilitated.

Note that the code length is 40 bits, the generator polynomial of the CRC calculation is x ⁸
Under the same condition of + x ² + x + 1, even in the configuration where the number of parallel processes of the CRC partial operation is 10, the maximum delay in the CRC partial operation is equivalent to three stages of the exclusive OR circuit. The hardware amount in this case is 83 exclusive OR circuits and 69 flip-flops. In the conventional example, the condition for providing the same operation speed is when a latch circuit is provided between the third and fourth exclusive OR circuits in the exclusive logic circuit network. And the amount of hardware is small.

In the above description, the code length n is 40, and the generator polynomial is x ⁸ + x ²
+ X + 1, and the code length n has been described as being divisible by the number of parallel processes l. However, the code length is other value, another generator polynomial,
The present invention can be implemented even when n is not divisible by 1.

Further, in the above embodiment, the cell synchronization circuit uses m = 40 bits of a data string including m bits of CRC bits, which is the remainder of division by a generator polynomial of m = 8 degrees.
An example of performing a CRC operation using the following generator polynomial is shown.
However, if the m-th generation polynomial on the transmitting side can be separated into the first-order and m-1-th order polynomials, even if the cell synchronization circuit performs a CRC operation based on the m-1th-order generation polynomial, the present invention can be implemented. It can be implemented similarly. For example, the generator polynomial x ⁸ + x ² + x + 1 is (x
+1) (x ⁷ + x ⁶ + x ⁵ + x ⁴ + x ² +1)
The cell synchronization circuit, the generator polynomial ^{x 7 + x 6 + x 5} + x 4 + x 2 +1
May be used to perform the CRC calculation.

〔The invention's effect〕

As described above, in the cell synchronization circuit of the present invention, an exclusive OR circuit for performing a CRC partial operation by parallel processing is cascaded via a latch circuit, and the CRC operation is realized in a pipeline format. Therefore, by appropriately selecting the number of parallel processes, it is possible to use the 1-bit immediate shift type,
A cell synchronous circuit having a desired operation speed can be realized, and the degree of freedom in design can be increased.

Further, in the case of using an LSI, since a plurality of exclusive OR networks each performing a CRC partial operation have the same configuration, there is an effect that LSI design becomes easy.

Further, since the hardware scale of each circuit for performing the CRC partial operation is reduced, the intersection between the wirings is reduced, and there is an effect that the wiring design of the LSI becomes easy.

[Brief description of the drawings]

FIG. 1 is a block diagram of a cell synchronization circuit according to a first embodiment of the present invention. FIG. 2 is a block diagram of a cell synchronization circuit according to a second embodiment of the present invention. FIG. 3 is a diagram showing a configuration of a cell in which a CRC bit is added to a header. FIG. 4 is a block diagram showing an example of a CRC calculation circuit. FIG. 5 is a block diagram of a conventional cell synchronization circuit. 1, shift register, 2, 11, 13, 14, 22, 24, 26,
28 ... exclusive OR network, 3, 12, 21, 23, 25, 27 ...
... Latch circuit, 4 ... OR circuit, 5, 6, 9 ... AND circuit, 7 ... Frame synchronization protection circuit, 8 ... Frame counter, 30-1 to 30-1, F1 to F40 ... Flip-flop , 31-1 to 31-3 ... exclusive OR circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04Q 3/00 101 9466-5K H04L 11/20 D

Claims (1)

(57) [Claims] 1. A receiving cell in which an n-bit header including a CRC bit is added to a digital information stream is input as a serial data stream, and each time a bit of this serial data stream is input, it is input by that time. CRC operation means for obtaining the remainder by a generator polynomial equivalent to that used to obtain the CRC bits for the n-bit data string, and an n-bit data string divisible by the generator polynomial from the output of this CRC operation means And a means for establishing cell synchronization by detecting the data sequence. The CRC calculating means comprises: a partial data sequence in which an n-bit data sequence to be operated is input as a partial data sequence divided in the input order; A plurality of CRC partial calculation means of the same configuration for obtaining the remainder by the generator polynomial, respectively, and the second and subsequent stages of the plurality of CRC partial calculation means Means for obtaining, from the remainder obtained at the previous stage and the remainder obtained at that stage, the remainder of the plurality of partial data strings input up to that stage by the generator polynomial for each CRC partial operation means. A cell synchronization circuit characterized by the above-mentioned.