GB2373883A

GB2373883A - Logic circuit for performing binary addition or subtraction

Info

Publication number: GB2373883A
Application number: GB0107649A
Authority: GB
Inventors: Dmitriy Rumynin
Original assignee: Automatic Parallel Designs Ltd
Current assignee: Automatic Parallel Designs Ltd
Priority date: 2001-03-27
Filing date: 2001-03-27
Publication date: 2002-10-02
Also published as: GB0107649D0; WO2002077796A1

Abstract

A logic circuit for performing addition or subtraction of two N bit binary numbers forms conditional sum addition by expressing at least some bits as a function of other bits, using a selection circuit and a parallel input interface.

Description

LOGIC CIRCUIT FOR PERFORMING BINARY ADDITION OR SUBTRACTION The present invention generally relates to the design of electronic logic circuits. More particularly, the present invention relates to any circuitry using or implementing addition or subtraction of binary numbers.

Some examples of operations where addition is used are multiplication, division and the Fast Fourier Transform (FFT). The binary operations of addition and subtraction are implemented

in many different applications. Given two binary n-digit numbers (An-l An-2... AI Ao) and (B Bn-2... Bi Bo) it is a requirement of many applications to have a logic circuit which will generate the sum (Sn Sn-t... Si So) which may have up to n + 1 digits. This is a general formulation of the problem. For applications, a particular n (often 16 or 32) is required. For some applications, only n last digits are needed and those can be obtained by reducing logic related to the computation of Sn. For other applications, special numbers can be taken. For instance, the second number may be known in advance so that a circuit should have only n

inputs (An-IAn-2... AIAo). Another example is an addition of an n-digit number with an m-digit number for n > m.

Much effort has been spent on developing architectures for known addition at maximised speed. Among known architectures, the conditional sum adder is known to be optimal (J.

Sklansky, "and evaluation of several two-summand binary adders", IRE trans. electron. comput. EC-9: 213-226 (1960)). In this architecture both sum and carry-out are expressed as functions of carry-in. The input bits are divided consequently into halves. The bits are then selected or multiplexed going over a binary tree from top to bottom. Every step sum and carry bits are chosen according to previous carries. Major shortcomings of this design which are acknowledged in the paper are extensive wiring and fan-out that affect the speed of the system, particularly at the stages where single carry bit is used to choose between many consequent sum and carry bits. The following notation is used for logical operations

A basic prior art method (SSA-simple series adder) proceeds by evaluating Sk as well as carries Cn, Cn-i,... Cl. It starts with

Then computing recursively for each integer k such that n > k > O,

and finally by

The main disadvantage of SSA is its slow speed.

The faster prior art method (CSA-conditional sum adder) as disclosed in the paper by Sklansky is based on evaluating Sk depending on what value Ck may have. In other words, it computes

for all relevant values ofk first. Then it chooses the correct values according to a binary tree.

To describe circuitry for this prior art method the following two blocks, CA (conditional adder) and MU (n, m) (multiplexer) are used. A single conditional adder has two inputs Ak, Bk

and 4 outputs Ack+1 (0), Ck+I (1), Sk (O), Sk (l) that are computed by

A block MU (n, m) has 2n inputs Xi (l), Xi (O),..., Xn (l), Xn (0), m controls C (m-1), C (m-2),..., C (O) and nm outputs Xi (m-l), XI (m-2),..., XI (O),..., Xn (m-l),..., Xn (0) where

These blocks are pictorially represented with rectangles and trapezoids in Figures la and Ib.

A CSA circuit for addition of 8-digit numbers is illustrated in Figure 2 and the table in Figure 3 illustrates the processing carried out by the circuit of Figure 2. While the CSA circuit provides a fast solution to the addition problem, the shortcomings of this prior art method are large area, large fan-out (affecting the speed), and extensive wiring.

It is an object of the present invention to provide an improved logic circuit for performing addition or subtraction of two binary numbers.

In accordance with a first aspect the present invention provides a logic circuit for performing additional subtraction of two N bit binary numbers where N is an integer, in which output bits are generated by logically combining respective bits of the two N bit binary numbers. The inventor has observed that the output of the system consists of the sum bits only: carry bits in the prior art play only a supplemental role. Thus at least one sum bit is generated as a function of the previous sum bit. The sum bits are selected for output sequentially in a binary tree fashion in a similar manner to that disclosed in the Sklansky Paper.

One aspect of the present invention provides a logic circuit for performing addition or subtraction of two N bit binary numbers, where N is an integer, the logic circuit comprising: a 2N bit parallel interface for inputting the bits of the two binary numbers in parallel; bit value generation logic connected to the interface for logically combining bit values of respective kth bits of the two binary numbers to generate bit values, where k is an integer between 1 and N and for additionally logically combining bit values of respective (k-1) 'bits of the two binary numbers for at least one kth bit to generate respective bit values; bit value selection logic

connected to the bit value generation logic for selecting generated bit values and at least one kth bit for k > 1 in dependence upon the bit value for a respective (k-l) th bit ; and an N+1 bit interface for outputting the bits selected by the bit value selection logic.

A further aspect of the present invention provided a logic circuit for performing addition or subtraction of two N bit binary numbers, where N is an integer, the logic circuit comprising: bit value generation logic components having 2N inputs for receiving the two N bit binary numbers and for generating possible output bit values by logically combining bit values of respective bits of the two binary numbers, where k is an integer between kth and N, said bit value generation logic components being arranged to generate possible output bit values for at least one kth bit (where k > 1) by additionally logically combining bit values of respective (k l) tu bits of the two binary numbers ; and selection circuit components having outputs for outputting the binary result of addition or subtraction and for selecting generated bit values for said outputs, said selection circuit components being arranged to select bit values for at least one kith bit where k > 1 in dependence upon the bit value for the respective (k-1) th bit.

In an embodiment of the present invention the selection circuit components comprise a plurality of first level selection circuit modules for receiving generated bit values for even numbered bits and for selecting bit values for the even numbered bits, and a plurality of

further level selection circuit modules for receiving respective outputs from respective

previous level selection circuit modules for bit numbers k > 2'-'where m is an integer denoting the level, and generated bit values for bit numbers k= (2m-lp+l), where p equals 1, 2, 3..., for

selecting bit values for the received bit numbers.

In accordance with this embodiment of the present invention, the sum bits are sequentially selected in a binary fashion i. e. 1 then 2 then 4 then 8 etc using respective level selection circuit modules. Thus in this embodiment of the present invention the further level selection

circuit modules select bit values for the received bit numbers conditional only the selected bit

r" values for bit numbers k = 2*"+ 2 ! where q equals 0, 1, 2....

In a first embodiment of the present invention sum bits can be expressed as a function of respective previous sum bits. Since the carry bits are not used for this block of bits the number of multiplexors or selector circuits are reduced and the wiring is reduced. In such an embodiment the bit value generation logic components can comprise a plurality of logic circuit modules. Each logic circuit module having four inputs for the kth and (k-l) th bits of each of the two binary numbers and one output for the kth output bit conditional on the (k-l) fil output bit being 1 and another output for the kth output bit conditional on the (k-l) th output bit being 0. Thus in these logic circuit modules, there are four inputs and only two outputs: both outputs being conditional on the output of the previous bit and not on any carry bits. Thus an example of such logic circuit modules is described hereinafter and referred to as a"carry killer".

In the embodiment of the present invention, a second logic circuit module can be provided having four inputs for the Nth and (N-1) th bits for each of the two binary numbers, and a first output for the Nth output bit conditional on the (N-l) th output bit being 0 a second output for the Nth output bit conditional on the (N-l) th output bit being 1, a third output for the (N+l) output bit conditional on the (N-l) h output bit being 1. Thus this second logic circuit module conditions the Nth and the (N+l) bit conditional on the (N-l) th output bit. This conditioning of two output bits on one single output bit provides a further logic saving. In the specific embodiment described hereinafter, an example of this second circuit module is termed an "extended carry killer".

In a second embodiment of the present invention an architecture with faster initial blocks is provided compared to the first embodiment. In the architecture half of the sum bits are expressed as functions of previous sum bits and the other half of the sum bits are expressed as functions of carry-in bits. Thus in the sum bit generation stage of the circuit, not just sum bits are generated but also carry-in bits. The carry-in bits are used only in the first level of selection or multiplexing and thereafter disappear. Thus they do not contribute to wiring or fan out since they are not selected. In both of the architectures of the first and second embodiments, there is similar smaller wiring and fan-out than in prior art designs of binary circuits for addition and subtraction.

Thus in this second embodiment of the present invention, carries are generated and used for conditioning a selection of the sum bits in the first level of selection or multiplexing.

Thereafter at the further levels of selection, the sum bits are selected conditional on previous sum bits.

In this embodiment of the present invention the bit value generation logic components can comprise a plurality of first logic circuit modules which each have four inputs for the kth and (k-l) th bits of the each of the two binary numbers, where k is an odd number greater than 1, and the first output for the kth output bit conditional on the (k-1) th bit being 1, a second output

th i-, th bit for the k output bit being conditional on the (k-l) th output bit being 0, a third output for a carrying value for the (k+1) th bit conditional on the carry value for the (k-l) th bit being 0, and a fourth output for a carry value for the (k+lbit conditional on the carry value for the (k-l) th bit being 1. In the specific embodiment described hereinafter the example described of the first circuit module is termed a"sum conditional adder".

In this embodiment of the present invention the bit value generation logic components can also include second logic circuit modules each having two inputs for the kth and (k-l) th bits of each of the two binary numbers, where k is an even number, and a first output for the kth output bit conditional on the carry value for the (k-l) th bit being 0, and a second output for the kth output bit conditional on the carry value for the (k-1)th th bit being 1. Thus the second logic circuit modules have two inputs and two outputs and do not generate carries. In the specific embodiment described hereinafter, an example of a second logic circuit module is described and termed"carry conditional adder". Thus in an embodiment the first and second logic circuit modules are alternated to receive alternate bit numbers for the two binary numbers.

In a specific implementation of the second embodiment, for the Nah bit of each of the two binary numbers, a second logic circuit module can be provided which has a third output for a carry value for the Nth bit conditional on the carry value for the (N-l) th bit being 0, and a fourth output for a carry value for the Nth conditional on the carry value for the (N-1)th bit being 1. In the specific embodiment of the present invention described hereinafter, an example of this type of second logic circuit module is termed a"conditional adder". Such a conditional adder is a conventional adder as used in the arrangement disclosed in the Sklansky Paper. The use of the second logic circuit module having two inputs in four outputs enables the N+1 output to be generated as a carry using the second circuit module for the Nth bit. This provides a reduction of logic compared to the use of two second logic circuit modules having two outputs.

In both of the embodiments, the first sum bit is preferably generated using logic e. g. a logic gate for combining the first bits of the two binary numbers to generate the bit value. This generated bit value is output and also used for conditioning the second bit in the first embodiment. Once the second bit has been conditioned, this can be used to condition the third and fourth bits, once the third and fourth bits have been conditioned, the fourth bit can be used to condition the fifth, sixth, seventh and eighth bits, and so on. In this way the sum bits are conditioned in a binary tree manner.

In the second embodiment of the present invention in which carries are used for conditioning at the first level, the first bit is not used directly and instead a carry is generated from the first bit to be used in the conditioning of the second bit. Thereafter the second bit is used to condition the third and fourth bits and the fourth bit is used to condition the fifth, sixth, seventh and eighth bits and so on.

In the design of logic for addition or subtraction, an important factor which affects speed is the slowest path along which signals propagate in the circuit. This notion is technology dependent. For the addition of large binary numbers it is possible to select the optimum technology using a mix of circuits of the first and second embodiments of the present invention. It is preferable to use a design with faster initial blocks along the critical path and a design with smaller wiring elsewhere. For example, the second embodiment has increase in wiring but provides faster initial logic circuit modules, thus making it more suitable as a block to be used for the initial bits i. e. least significant bits of a circuit. On the other hand the design of the first embodiment of the present invention using no carries, significant reduces the wiring by avoiding the need to pass carries thus making it suitable for the logical summation process for more significant bits of binary numbers.

Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Figure la is a schematic diagram of a conditional adder and a multiplexor for producing one sum conditioned by one carry value in accordance with the prior art, Figure 1 b is a schematic diagram of a multiplexor in which three sum bits are conditioned dependent upon two carry values in accordance with the prior art, Figure 2 is a schematic diagram of a conditional sum adder circuit in accordance with the prior art disclosed in the Sklansky Paper, Figure 3 is a table illustrating the computation process carried out by the prior art circuit of Figure 2, Figure 4a is a schematic diagram of a first circuit module termed a"carry killer"for generating sum bits conditioned on previous sum bits in accordance with the first embodiment of the present invention, Figure 4b is a schematic diagram of a second circuit module termed an"extended carry killer" for generating two adjacent sum bits conditioned on a previous sum bit in accordance with the first embodiment of the present invention, Figure 5 is a logic circuit diagram of the logic within the carry killer logic circuit module of Figure 4a, Figure 6 is a logic circuit diagram of the logic contained within the extended carry killer logic circuit module of Figure 4b, Figure 7 is a schematic diagram of a logic circuit for performing the addition of two 8 bit binary numbers in accordance with the first embodiment of the present invention, Figure 8 is a logic diagram of the logic contained within the multiplexor MU (1, 1) in the circuit diagram of Figure 7, Figure 9 is a logic diagram for logic contained within a multiplexor MU (2,1) in the circuit diagram of Figure 7, Figure 10 is a logic diagram of the logic contained within the multiplexor MU (1,2) in the circuit diagram of Figure 7, Figure 11 is a logic diagram of the logic contained with the multiplexor MU (2,2) used in the circuit diagram of Figure 6, Figure 12 is a logic diagram of the logic contained within the multiplexor MU (2,2) built from multiplexors MU (l, l) used in the circuit diagram of Figure 7, Figure 13 is a logic diagram of the logic contained within the multiplexor MU (3,2) used in the circuit diagram of Figure 7, Figure 14 is a logic diagram of the logic contained within the multiplexor MU (5,1) used in the circuit diagram of Figure 7, Figure 15 is a table illustrating the computation carried out in the circuit of Figure 7, Figure 16 is a schematic diagram of a first part of a logic circuit for adding two binary numbers, Figure 17 is a schematic diagram of an intermediate part of a circuit for adding binary numbers, Figure 18 is a schematic diagram of a final part of a circuit for adding binary numbers, Figure 19 is a schematic diagram illustrating the use of the circuit part illustrated in Figure 16 (NCA-2) and the circuit part illustrated in Figure 18 (NCA-4) for adding to 16 bit numbers, Figure 20 is a schematic diagram of a circuit for adding two 32 bit numbers using the circuit part of Figure 16 (NCA-2), the circuit part of Figure 17 (NCA-3) and the circuit part of Figure 18 (NCA-4); Figure 21 is a logic diagram of a logic contained within the multiplexer MU (4,1) used in the circuit of Figure 16, Figure 22 is a logic diagram of the logic contained within the multiplexer MU (4,2) used in the circuit of Figure 17, Figure 23 is a logic diagram of the logic contained within the multiplexer MU (5,2) made from multiplexers MU (1,1) used in the circuit of Figure 18, Figure 24a is a schematic diagram of a second logic circuit module in accordance with the principles of a second embodiment of the present invention having two inputs and two outputs for generating sum bits conditioned on carries from previous sum bits and termed a carry conditioner adder, Figure 24b is a schematic diagram of a first logic circuit module in accordance with the principles of the second embodiment of the present invention having four inputs and four outputs and termed a sum conditional adder, Figure 25 is a logic diagram of the logic in the carry conditional adder of Figure 24a, Figure 26 is a schematic diagram of the logic within a conditional adder logic circuit module; Figure 27 is a schematic diagram of a logic circuit for adding two 8 bit binary numbers in accordance with the principles of a second embodiment of the present invention, Figure 28 is a table illustrating the computation implemented by the circuit of Figure 27, Figure 29 is a schematic diagram of a logic circuit for adding two 32 bit numbers using the circuit of the first embodiment of the present invention for the first 8 bits and a number of circuits of the second embodiment of the present invention for the remaining 24 bits, Figure 30 is a logic diagram of the logic contained within a carry killer logic circuit module used for subtraction in accordance with an embodiment of the present invention, Figure 31 is a logic diagram for the logic contained within an extended carry killer logic circuit module for subtraction in accordance with an embodiment of the present invention, Figure 32 is a logic diagram of the logic contained within the carry conditional adder logic circuit module used for subtraction in accordance with an embodiment of the present invention, and Figure 33 is a logic diagram of the logic contained within a conditional adder logic circuit module used for subtraction in accordance with an embodiment of the present invention.

The first aspect of the present invention will now be described with reference to Figures 4 to 23. In this aspect of the present invention, the conditioning is performed without using carrys.

Formulas for addition without carries are derived first. In other words, a sum bit value Sk is expressed in terms of a previous bit value Sk-l rather than a carry value Ck. It can be observing that

This can be used to express Ck

Substituting this expression into the formula for Sk gives:

Now, similarly to SSA and CSA, a sequential method of adding numbers without carries will be explained. To summarize binary numbers can be added by computing

first and proceeding recursively for each integer k such that nk > 0,

This method is highly suitable for a conditional design that is called NCA (no carry addition).

For each k,

is computed at the beginning. Then the correct values are chosen according to a binary tree.

To implement this, a block CK (carry killer) shown on Figure 4a is used.

If inputs have n digit numbers then it is advantageous to compute Sn as a function of Son. 2 rather than Son-1. A block ECK (extended carry killer), shown on Figure 3, does this according to formulas

The logic used in the carry killer to implement the logic of equations 15 and 16 is illustrated in Figure 5. Also, the logic of the extended carry killer to implement the logic of equations 16,17, 18 and 19 is illustrated in Figure 6.

A schematic diagram illustrating the circuit with the addition of 8 bit numbers using the nocarry addition (NCA) method is illustrated in Figure 7. As can be seen in the diagram, the circuit has the structural similarity to the circuit of Sklansky. The differences are however that the initial logic circuit modules into which the two binary numbers are input logically combine adjacent binary bit values and output sum bits for conditioning based on previous sum bits. The conditioning is performed by levels of selection circuits or multiplexers (MU).

Figure 8 is a logic diagram illustrating the logic of the multiplexer MU (1,1) used in Figure 7 for the conditioning of the second bit Sl on the basis of the first bit So. Figure 9 is a logic diagram illustrating the logic in the multiplexer MU (2,1) used for conditioning the third and fourth bits S2 and S3 based on the second bit Si in the circuit of Figure 7. Figure 10 is a logic diagram illustrating the logic of multiplexer MU (1,2) used for conditioning the fourth and sixth bits based on the third and fifth bits respectively in the diagram of Figure 7. Figure 11 is a logic diagram of a logic of the multiplexer MU (2,2) used for conditioning the eighth and ninth sum bits S7 and Sg based on the seventh sum bit S6 in the circuit of Figure 7. Figure 12 is a logic diagram of the multiplexer MU (2,2) formed from multiplexers MU (1,1). This form of module design greatly saves on logic. Figure 13 is a logic diagram with a logic of multiplexer MU (3,2) used for conditioning the seventh, eighth and ninth sum bits S6, S7 and Sg based on the sixth sum bit Ss in the circuit of Figure 7. Figure 14 is a logic diagram of the logic of multiplexer MU (5, 1) used for conditioning the fifth, sixth, seventh, eighth and ninth sum bits S4, Ss, S6, S7 and Sg based on the fourth sum bit S4 in the circuit of Figure 7.

Figure 15 is a table illustrating the logic process carried out by the logic circuit of Figure 7 for adding two 8 bit binary numbers 75 and 133 to reach the sum of 208. As can be seen, at the first level some bits are generated conditional on previous sum bits. Clearly for k = 0, there is no previous bit. Thus at the first level of selection by the multiplexers, the even numbered bits are conditioned based on the odd numbered bits. At the output of the first level of selection provided at level 2, conditioning takes place using the two multiplexers MU (3,2) and MU (2,1) based on the second and sixth bit. The output of the second level of selection is shown at level 3 and already the first four bits have been selected for output. At the third level of selection the multiplexer MU (5,1) selects the five sum bits S4 to Sg based on the fourth sum bit S3.

The critical path for fan-out in this NCA circuit usually starts at Al and finishes at S4 through to Ss. Compared to the prior art, there is reduced fan-out along this path, further, another advantage of this NCA circuit is that fewer multiplexers are employed. This also reduces wiring.

To build NCA circuits in accordance with this aspect of the present invention for 2k digit numbers, this can be constructed from 3 slightly modified types of NCA blocks. Figure 16 illustrates a first NCA block (NCA-2) for the first 8 bits (8 least significant bits) of the two binary numbers. It should be noted that the circuit of Figure 16 differs from the circuit of Figure 7 only in that no extended carry killer logic circuit module is used to generate S8.

Figure 17 illustrates an intermediate NCA block (NCA-3) to be used for intermediate bits above 8 and below N-8. It should be noted from the circuit of Figure 17 that this circuit differs from the circuit of Figure 16 in that all of the sum bits are generated using carry killer logic modules. The first carry killer module in the block will receive inputs from the previous bits i. e. A7 and B7. Figure 18 illustrates a third type of NCA block (NCA-4) used for generating the most significant sum bits. It should be noted that this differs from the circuit of Figure 7 in that the least significant bits are generated using a carry killer logic module. The carry killer logic module will receive inputs for previous bits from an adjacent input bit. In the drawings of Figures 16 to 18, a shorthand notation is used for the wiring. For instance, A12-Bll denotes four parallel wires whose values are A12, Bol2, All and Bll. A shorthand notation for outputs is also used so that the output comes as pairs. Outputs start with Sk+8 (1), Sk+8 (0). Then Sk+7 (1), Sk+7 (0) until the outputs end with Sk (1) and Sk (0).

Figure 19 illustrates a NCA circuit for the addition of two 16 bit numbers. The NCA circuit NCA-2 of Figure 16 is used to generate the sum of the first 8 bits So to S7. The NCA circuit NCA-4 is used for the most significant 16 bits to generate sum bits conditional on the previous sum bit S7. The multiplexer MU (9,1) conditions the sums based on the sum of the eighth bit S7 to output sum bits of Sg and Spi6.

Figure 20 is a schematic diagram of a NCA circuit for summing two 32 bit numbers. It can be seen in this diagram that the NCA circuit NCA-2 of Figure 16 is used for the eight least significant bits. Two intermediate NCA circuits NCA-3 illustrated in Figure 17 are used for the intermediate 16 bits and for the 8 most significant bits the NCA circuit NCA-4 illustrated in Figure 18 is used. At the fourth level of selection, the multiplexers MU (9,2) and MU (8, 1) are conditioned by the eighth and twenty fourth sum bit respectively. At the fifth level of selection, the multiplexer MU (17,1) conditions the most significant 16 bits based on the sum bit Sts.

It can thus be seen from this aspect of the present invention that the sum bits are sequentially determined in a binary tree manner.

Figure 21 is a logic diagram of the logic of multiplexer MU (4,1) used in the circuit of Figure 16. Figure 22 is a logic diagram of the logic of multiplexer MU (4,2) used in the circuit of Figure 17. Figure 23 is a logic diagram of the logic of multiplexer MU (5,2) made from multiplexers MU (1,1) used in the circuit of Figure 18.

The second aspect of the present invention will now be described with reference to Figures 24 to 28. In this second aspect of the present invention, carries are used in the first level of multiplexing. Thereafter, carriers are not used thereby bringing about a reduction in wiring.

The use of carriers in the first round of multiplexing increases the speed of the logic. This technique is termed half carry addition (HCA). Half carry addition requires a conditional adder logic circuit module of the prior art as illustrated in Figure la. Also, 2 new logic circuit modules are required: a carry conditional adder (CCA) and a sum conditional adder (SCA).

These are respectively illustrated in Figures 24a and 24b.

The CCA computes a sum bit as a function of carry-in. It has two inputs Ak and Bk and two outputs Sk (l) and Sk (O) computed by

SCA is identical to ECK block but a different name is used since it plays a different role in HCA. SCA computes a sum bit and a carry-out bit as a function of the previous bit. It has four inputs Ak, Bk, Ak-i, Bk-l and four outputs Ck+l (l), Ck+i (0), Sk (l), Sk (O) computed by

Figure 25 is a logic diagram of the logic within the carry conditional adder illustrated in Figure 24a. Figure 26 is a logic diagram with the logic within a conditional adder as illustrated in Figure la. The logic for the sum conditional adder (SCA) is the same as for the ECK and as that illustrated in Figure 6.

A half carry addition circuit illustrated in Figure 27 for adding 2 8 bit binary numbers. It can be seen in Figure 27 that the first bit So is generated by simple logic combination. A carry is generated using an AND gate for the first level of selection for selecting the second bit Si.

The SCA circuits generate carrys for the selection of even numbered bits greater than 2, i. e. 4, 6 and 8. Thus, using the first level of selection, the even numbered bits are conditioned based on carries for odd numbered bits i. e. for proceeding respective bits. Thereafter at the second and third levels of selection conditioning, the process is similar to that described in the first aspect of the present invention. The processing carried out by the circuit of Figure 27 is illustrated in the table of Figure 28. As can be seen, the output of the SCA and CCA circuits generate carries which are used in the first level of selection. Thereafter the selection is carried out conditional on previous sum bits.

In a similar manner to the first aspect of the present invention, HCA circuits can be used in a modular form to build circuits with the addition of large binary numbers.

In accordance with a third aspect of the present invention, it is possible to mix the use of NCA circuits and HCA circuits in accordance with the first and second aspects of the present invention as described hereinabove. The architecture of no carry addition (NCA) employs CK blocks that are larger and slower than CA blocks. The architecture of half carry addition (HCA) uses fast CCA blocks and SCA blocks with first carry bits and slow sum bits in the output. The advantage of both architectures over the prior art conditional sum addition of Sklansky is that the multiplexer part is smaller. Thus an optimal design can be achieved by mixing the NCA and HCA architectures.

The optimal design will depend upon the technology. The inventors have determined by experimentation with different technologies that the critical part of all three conditional designs (CSA, NCA and HCA) is similar in the same technology. Thus, an overall design can be achieved by using the fastest design along the critical path and a design with a smaller multiplexer part off the critical path.

For instance, in TSMC. 25 an 8-bit input CSA is a little faster than 8-bit HCA, while a 8-bit NCA is the slowest. With 32-bit inputs, HCA is faster than CSA and NCA have a similar speed. The inventors have however determined that the fastest 32-bit adder is achieved by mixing designs as shown in Figure 29. As can be seen from Figure 29, a conventional conditional sum adder is used for the first 8-bits and half carry adders are used for the remaining 24-bits.

Thus in this aspect of the present invention only some of the input bits are summed and conditioned based on previous bits. Although the aspect of the present invention have been described hereinabove with reference to addition, these aspects are equally applicable to subtraction. Both NCA and HCA architectures can do subtraction with slight modifications.

Given two binary n-digit numbers (An. An-2... Ai Ao) and (Bn-l Bn-2... Bl Bo), subtract the latter from the former. The difference is given by (Sn... Si So). An NCA circuit can compute the difference if CK blocks are modified. A modified CK block will produce the following two bits.

A signal Sn plays a special role in subtraction. Its being high indicates that the result is negative.

The logic for the CK blocks for subtraction is illustrated in Figure 30.

A modified ECK block computing Sn has a function of Son. 2 is identical to a modified SCA block the logic for which is given below.

The logic diagram for the modified ECK block for performing subtraction is illustrated in Figure 31.

HCA can also compute the difference with slight modifications in SCA blocks. A modified SCA block will produce

The modified CA block computing Sn is:

Figure 32 is a logic diagram illustrating the CCA logic for subtraction and Figure 33 is a logic diagram illustrating the logic for the CCA logic module for performing subtraction.

Although the present invention has been described hereinabove with reference to specific embodiments, it would be apparent to a skilled person in the art that the present invention is not limited to such embodiments and modifications can be made which lie within the spirit and scope of the present invention.

The present invention provides a logic circuit for performing addition or subtraction of two binary numbers in which not all summation bits are expressed as a function of carries.

Expressed in a different way, in the present invention some bits are expressed as a function of previous some bits. Thus the present invention provides CSA logic for subtraction or addition in which sum bits are expressed as a function of other bits.

Claims

CLAIMS: 1. A logic circuit for performing addition or subtraction of two N bit binary numbers, where N is an integer, the logic circuit comprising: bit value generation logic components having 2N inputs for receiving the two N bit binary numbers and for generating possible output bit values by logically combining bit values of respective kth bits of the two binary numbers, where k is an integer between 1 and N, said bit value generation logic components being arranged to generate possible output bit values for at least one kl bit (where k > 1) by additionally logically combining bit values of respective (k-l) th bits of the two binary numbers; and selection circuit components having outputs for outputting the binary result of addition or subtraction and for selecting generated bit values for said outputs, said selection circuit components being arranged to select bit values for at least one kth bit where k > 1, in dependence upon the bit value for the respective (k-l) th bit.
2. A logic circuit according to claim 1, wherein said selection circuit components comprise a plurality of first level selection circuit modules for receiving generated bit values for even numbered bits and for selecting bit values for the even numbered bits, and a plurality of further level selection circuit modules for receiving respective outputs

from respective previous level selection circuit modules for bit numbers k > 2m-', where m is an integer denoting the level, and generated bit values for bit numbers k = (2m lp+1), where p = 1, 2, 3...., and for selecting bit values for the received bit numbers.
3. A logic circuit according to claim 2, wherein the plurality of further level selection circuit modules are arranged to select bit values for the received bit numbers

m conditional on the selected bit values for bit numbers k = 2'"'+ 2 , where q = 0, 1, 2,...
4. A logic circuit according to claim 2 or claim 3, wherein a plurality of said first level section circuit modules are arranged to select bit values for even numbered bits conditional on the generated bit values for odd numbered bits.
5. A logic circuit according to claim 2 or claim 3, wherein a plurality of said first level circuit modules are arranged to select bit values for even numbered bits conditional on a carrier generated for odd numbered bits.
6. A logic circuit according to any preceding claim, wherein said bit value generation logic components comprise: a plurality of logic circuit modules, each logic circuit module having four inputs for the kth and (k-1)th th bits of each of the two binary numbers and one output for the kth output bit conditional on the (k-1)th th output bit being I and another output for the kth output bit conditional on the (k-1)th th output bit being 0.
7. A logic circuit according to any one of claims 1 to 3 or 5, wherein said bit value generation logic components comprise a plurality of first logic circuit modules, each first logic circuit module having four inputs for the kth and (k-l) th bits of each of the two binary numbers, wherein k is an odd number greater than 1, and a first output for the kth output bit conditional on the (k-l) th output bit being 1, a second output for the kth output bit conditional on the (k-l) th output bit being 0, a third output for a carry value for the (k+l) th bit conditional on the carry value for the (k-1)th th bit being 0, and a fourth output

for a carry value for the (k+1) bit conditional on the carry value for the (k-l) th bit being 1.
8. A logic circuit according to claim 7, wherein said bit value generation logic components comprise a plurality of second logic circuit modules, each second circuit module having two inputs for the kth and (k-1)th bits of each of the two binary numbers, where k is an even number, and a first output for the kth output bit conditional on the carry value for the (k-1)th th output bit conditional on the carry value for the (k-1)th th bit being 1.
9. A logic circuit according to claim 8, wherein when N is an even number, and said second logic circuit module for receiving the Nth bit of each of the two binary numbers further comprises a third output for a carry value for the Nth bit conditional on the carry value for the (N-1) th bit being 0, and a fourth output for a carry value for the Nth bit conditional on the carry value for the (N-l) th bit being 1.
10. A logic circuit according to any one of claims 1 to 4, wherein said bit value generation logic components comprise: a plurality of first logic circuit modules, each first logic circuit module having four inputs for the kth and (k-l) th bits of each of the two binary numbers and a first output for the kith output bit conditional on the (k-l) th output bit being 1 and a second output for the kth output bit conditional on the (k-l) th output bit being 0, where k is an integer between 2 and N-1 ; and a second logic circuit module having four inputs for the Nth and (N-1)th bits of each of the two binary numbers, and a first output for the Nth output bit conditional on

the (N-l) th output bit being 0, a second output for the Nah output bit conditional on the (N-l) th output bit being 1, a third output for the (N+l) output bit conditional on the (Nl) th output bit being 0, and a fourth output for the (N+l) output bit conditional on the (N-1)th output bit being 1.
11. A logic circuit according to any preceding claim, wherein said bit value generation logic components include a logic gate for combining the first bits of the two binary numbers to generate the bit value for the first bit and said selection circuit components are arranged to select the bit value for the second bit conditional on the generated bit value for the first bit.
12. A logic circuit according to any one of claims 7 to 9, wherein said bit value generation logic components include a first logic gate for combining the first bits of the two binary numbers to generate the bit value for the first bit, and a second logic gate for generating a carry value for the first bit, and said selection circuit components are arranged to select the bit value for the second bit conditional on the generated bit value for the first bit.
13. A logic circuit according to claim 6 for performing addition, wherein each logic

circuit module comprises logic components to perform the logic :

Sk (l) =AkOBke (Ak-iABk. !), Sk (O) =Ak$Bke (Ak- ! vBk-l) where Sk (l) is the output for the Kth output bit conditional on the (k-1) th output

bit being 1 ; Sk (O) is the output for the kth output bit conditional on the (k-l) th output bit being 0 ; Ak is the kith input bit for a first of the binary numbers ; Bk is the kth input bit for a second of the binary numbers ; ? is the logical exclusive OR operation; A is the logical AND operation.
14. A logic circuit according to claim 10 for performing addition, wherein each first logic circuit module comprises logic components to perform the logic:

and said second logic circuit module comprises logic components to perform the logic:

where Sk(1) is the output for the kth output bit conditional on the (k-1)th th output bit being 1;

Sk (O) is the output for the kth output bit conditional on the (k-l) th output bit being 0 ; SN (1) is the output for the Nth output bit conditional on the (N-2) th output bit being 1 ; SN(0) is the output for the Nth output bit conditional on the (N-2) th output bit being 0; AK is the kth input bit for a first of the binary numbers; BK is the kth input bit for a second of the binary numbers; # is the logical exclusive OR operation; A is the logical AND operation; v is the logical OR operation.
15. A logic circuit according to claim 7 for performing addition, wherein each first logic circuit module comprises logic components to perform the logic:

where Ck+l (l) is the carry value for the (k+1) th bit conditional on the carry value for the kth bit being 1; Ck+1(0) is the carry value for the (k+ l) th bit conditional on the carry value for the kth bit being 0; Sk (I) is the output for the kth output bit conditional on the (k-l) output bit being 1;

Sk (O) is the output for the kth output bit conditional on the (k-l) th output bit being 0 ; Ak is the kth input bit for a first of the binary numbers ; Bk is the kth input bit for a second of the binary numbers ; ? is the logical exclusive OR operation; A is the logical AND operation; v is the logical OR operation.
16. A logic circuit according to claim 8 for performing addition, wherein each second logic circuit module comprises logic components to perform the logic:

where Sk (l) is the output for the kth output bit conditional on the (k-1) th output bit being 1;

Sk (O) is the output for the kth output bit conditional on the (k-1) th output bit being 0 ; Ak is the kth input bit for a first of the binary numbers ; Bk is the kth input bit for a second of the binary numbers ; # is the logical exclusive OR operation.
17. A logic circuit according to claim 9 for performing addition, wherein the second

logic circuit module for receiving the No'bit comprises logic components to perform the logic:

where Sk (l) is the output for the kth output bit conditional on the (k-1)th output bit being 1;

Sk (O) is the output for the kth output bit conditional on the (k-l) th output bit being 0 ; where Ck+l (l) is the carry value for the (k+1) bit conditional on the carry value for the kth bit being 1 ; CK+1(0) is the carry value for the (K+l) th bit conditional on the carry value for the Kth bit being 0; ? is the logical exclusive OR operation; A is the logical AND operation; v is the logical OR operation.
18. A logic circuit according to claim 6 for performing subtraction, wherein each logic circuit module comprises logic components to perform the logic:

where Sk (l) is the output for the kth output bit conditional on the (k-l) th output bit being 1;

Sk (O) is the output for the kth output bit conditional on the (k-l) th output bit being 0 ; Ak is the input bit for a first of the binary numbers ; Bk is the input bit for a second of the binary numbers ; ? is the logical exclusive OR operation ; A is the logical AND operation; v is the logical OR operation; is the logical NOT operation.
19. A logic circuit according to claim 10 for performing subtraction, wherein each first logic circuit module comprises logic components to perform the logic:

and said second logic circuit module comprises logic components to perform the logic:

where Sk (l) is the output for the kth output bit conditional on the (k-l) th output bit being 1 ;

Sk (O) is the output for the kth output bit conditional on the (k-l) th output bit being 0 ; SN (l) is the output for the Nth output bit conditional on the (N-2) th output bit being 1 ; SN (O) is the output for the N output bit conditional on the (N-2) th output bit being 0 ; Ak is the input bit for a first of the binary numbers ; Bk is the input bit for a second of the binary numbers ; ? is the logical exclusive OR operation; A is the logical AND operation; v is the logical OR operation.

# is the logical NOT operation
20. A logic circuit according to claim 7, for performing subtraction, wherein each first logic circuit module comprises logic components to perform the logic:

where Ck+1(1) is the carry value for the (kelp bit conditional on the carry value for the kth bit being 1; Ck+1(0) is the carry value for the (k+1)th bit conditional on the carry value for the kth bit being 0; Sk (l) is the output for the kth output bit conditional on the (k-1)th th output bit being 1;

Sk (O) is the output for the kith output bit conditional on the (k-l) th output bit being 0 ; Ak is the kth input bit for a first of the binary numbers ; Bk is the kith input bit for a second of the binary numbers ; E is the logical exclusive OR operation ; A is the logical AND operation; v is the logical OR operation; --, is the logical NOT operation.
21. A logic circuit according to claim 8 for performing subtraction, wherein each second logic circuit module comprises logic components to perform the logic:

where where Sk (l) is the output for the kth output bit conditional on the (k-1)th output bit being 1 ;

Sk (O) is the output for the kth output bit conditional on the (k-l) th output bit being 0 ; ? is the logical exclusive OR operation ; A is the logical AND operation ; v is the logical OR operation.

- i is the logical NOT operation.
22. A logic circuit according to claim 9 for performing subtraction, wherein the second logic circuit module for receiving the Nth bit comprises logic components to perform the logic: The modified CA block computing Sn is:

where Sk (l) is the output for the kth output bit conditional on the (k-l) th output bit being 1;

Sk (O) is the output for the kith output bit conditional on the (k-l) th output bit being 0 ; where Cl+1 (1) is the carry value for the (k+l) th bit conditional on the carry value for the kth bit being 1;

Ck+I (O) is the carry value for the (k+l)'h bit conditional on the carry value for the kth bit being 0; is the logical exclusive OR operation; A is the logical AND operation; v is the logical OR operation. is the logical NOT operation.
23. A logic circuit for performing addition or subtraction of two N bit binary numbers, where N is an integer, the logic circuit comprising: a 2N bit parallel interface for inputting the bits of the two binary numbers in parallel; bit value generation logic connected to the interface for logically combining bit values of respective kth bits of the two binary numbers to generate bit values, where k is an integer between 1 and N and for additionally logically combining bit values of respective (k-l) th bits of the two binary numbers for at least one kth bit to generate respective bit values; bit value selection logic connected to the bit value generation logic for selecting generated bit values and at least one kth bit for k > l in dependence upon the bit value for a respective (k-1) th bit; and an N+l bit interface for outputting the bits selected by the bit value selection logic.