CN111384944B - Full adder, half adder, data processing method, chip and electronic equipment - Google Patents

Full adder, half adder, data processing method, chip and electronic equipment Download PDF

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CN111384944B
CN111384944B CN201811618768.XA CN201811618768A CN111384944B CN 111384944 B CN111384944 B CN 111384944B CN 201811618768 A CN201811618768 A CN 201811618768A CN 111384944 B CN111384944 B CN 111384944B
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circuit
data
logic
control signal
gating
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CN111384944A (en
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不公告发明人
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Shanghai Cambricon Information Technology Co Ltd
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Shanghai Cambricon Information Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application provides a full adder, a half adder, a data processing method, a chip and an electronic device, wherein the full adder comprises: the circuit comprises a logic circuit, a first gating circuit, a second gating circuit and a selection circuit; the half adder includes: a logic circuit, a gating circuit and a selection circuit; the full adder can selectively close partial circuits in the full adder, so that the power consumption of the full adder is reduced, and the performance of the AI chip is improved; in addition, the half adder can selectively close partial circuits in the half adder, so that the power consumption of the half adder is reduced, and the performance of the AI chip is improved.

Description

Full adder, half adder, data processing method, chip and electronic equipment
Technical Field
The invention relates to the technical field of computers, in particular to a full adder, a half adder, a data processing method, a chip and electronic equipment.
Background
With the rapid development of various Artificial Intelligence (AI) chips, the requirements for high-performance digital systems are increasing. In a digital system, a full adder and a half adder are indispensable components of operation modules such as the full adder, the half adder, a comparator and the like, while a neural network algorithm is one of algorithms widely applied to an intelligent chip, and the operation modules such as the full adder, the half adder, the full adder, the comparator and the like are required to be used for multiple times in the neural network algorithm, so that the performance of the full adder and the half adder on the basis of the neural network algorithm is particularly important for an AI chip.
The existing full adder and half adder are generally formed by combining an exclusive or gate logic circuit, an and gate circuit and an or gate logic circuit. Meanwhile, in the operation process, most of the full adders and the half adders adopt logic gate circuits such as exclusive-or gates for operation, so that the power consumption of the full adders and the half adders is high.
Disclosure of Invention
In view of the above, it is desirable to provide a full adder, a half adder, a data processing method, a chip, and an electronic device.
The embodiment of the invention provides a full adder, which comprises: the circuit comprises a logic circuit, a first gating circuit, a second gating circuit and a selection circuit; the output end of the logic circuit is connected with the input end of the first gating circuit and the first input end of the selection circuit, the output end of the first gating circuit is connected with the input end of the second gating circuit and the second input end of the selection circuit, and the output end of the second gating circuit is connected with the third input end of the selection circuit;
the logic circuit is configured to perform a logic operation on received data to obtain a first control signal, the first gating circuit is configured to determine whether to gate the data according to the first control signal, and perform a combinational logic operation on the data to obtain a second control signal, the second gating circuit is configured to determine whether to gate the data according to the second control signal, and perform an arithmetic operation on the data to obtain an arithmetic operation result, and the selection circuit is configured to determine a target operation result according to the received first control signal, the second control signal, or the arithmetic operation result.
In one embodiment, the logic circuit comprises: an OR gate logic circuit to OR the received data.
In one embodiment, the first gating circuit includes: the output end of the first gating sub-circuit is connected with the input end of the combinational logic sub-circuit;
the first gating sub-circuit is used for judging whether to gate the data according to the received first control signal, and the combinational logic sub-circuit is used for performing combinational logic operation on the data gated by the first gating sub-circuit.
In one embodiment, the combinational logic subcircuit includes: the output end of the AND gate logic unit is connected with the input end of the OR gate logic unit;
the AND gate logic unit is used for carrying out AND logic operation on the data gated by the first gating circuit to obtain an AND logic operation result, and the OR gate logic unit is used for carrying out OR logic operation on the AND logic operation result to obtain the second control signal.
In one embodiment, the second gating circuit includes: the output end of the second gating sub-circuit is connected with the input end of the addition sub-circuit;
the second gating sub-circuit is used for judging whether to gate the data according to the received second control signal, and the adding sub-circuit is used for adding the data gated by the second gating sub-circuit to obtain an addition operation result.
In one embodiment, the adding subcircuit is formed by combining different logic gate units.
In one embodiment, the addition sub-circuit comprises: the output end of the exclusive-OR gate logic unit is connected with the input end of the AND gate logic unit, and the output end of the AND gate logic unit is connected with the input end of the OR gate logic unit;
the exclusive-or gate logic unit is configured to perform exclusive-or logic operation on the received data, the and gate logic unit is configured to perform and logic operation on the received data to obtain an and logic operation result, and the or gate logic unit is configured to perform or logic operation on the and logic operation result.
In one embodiment, the selection circuit comprises: a selection sub-circuit for determining a target operation result according to the received first control signal, the second control signal or the addition operation result.
According to the full adder provided by the embodiment, part of circuits in the full adder can be selectively closed, so that the power consumption of the full adder is reduced, and the performance of an AI chip is improved.
An embodiment of the present invention provides a half adder, including: a logic circuit, a gating circuit and a selection circuit; the output end of the logic circuit is connected with the input end of the gating circuit and the first input end of the selection circuit, and the output end of the gating circuit is connected with the second input end of the selection circuit;
the selection circuit is used for determining a target operation result according to the received first control signal or the received second control signal.
In one embodiment, the logic circuit comprises: an OR gate logic circuit to OR the received data.
In one embodiment, the gating circuit includes: the output end of the gating sub-circuit is connected with the input end of the logic sub-circuit; the gating sub-circuit is used for judging whether to gate the data according to the received first control signal, and the logic sub-circuit is used for carrying out logic operation on the data gated by the gating sub-circuit.
In one embodiment, the logic subcircuit includes: an AND gate logic unit; and the AND gate logic unit is used for carrying out AND logic operation on the data after being gated by the gating circuit to obtain the second control signal.
In one embodiment, the selection circuit comprises: and the selection sub-circuits are used for determining and outputting a target operation result according to the received first control signal or the second control signal.
According to the half adder provided by the embodiment, part of circuits in the half adder can be selectively turned off, so that the power consumption of the half adder is reduced, and the performance of an AI chip is improved.
The embodiment of the invention provides a data processing method, which comprises the following steps:
receiving data to be processed;
performing first logic operation processing on the data to be processed to obtain a first control signal;
and if the data to be processed does not need to be subjected to second logic operation processing according to the first control signal, outputting a target operation result according to the first control signal.
In one embodiment, the method further comprises:
if the data to be processed needs to be subjected to the second logic operation processing according to the first control signal, gating the data to be processed, and performing second logic operation on the data to be processed to obtain a second control signal;
and if the data to be processed does not need to be subjected to arithmetic operation processing according to the second control signal, outputting a target operation result.
In one embodiment, after obtaining the second control signal, the method further includes:
if the data to be processed needs to be subjected to the arithmetic operation processing according to the second control signal, gating the data to be processed, and performing the arithmetic operation on the processing to be processed to obtain an arithmetic operation result;
and outputting a target operation result according to the arithmetic operation result.
According to the data processing method provided by the embodiment, the target operation result can be directly output according to the obtained first control signal, part of circuits in the full adder are selectively closed, the power consumption of the full adder is reduced, and therefore the performance of the AI chip is improved.
The embodiment of the invention provides another data processing method, which comprises the following steps:
receiving data to be processed;
performing OR logic operation processing on the data to be processed to obtain a first control signal;
and if the data to be processed does not need to be subjected to AND logic operation according to the first control signal, outputting a target operation result according to the first control signal.
In one embodiment, the method further comprises:
if the data to be processed needs to be subjected to the AND logic operation processing according to the first control signal, gating the data to be processed, and performing the AND logic operation on the data to be processed to obtain a second control signal;
and outputting a target operation result according to the second control signal.
According to the data processing method provided by the embodiment, the target operation result can be directly output according to the obtained first control signal, part of circuits in the half adder are selectively closed, the power consumption of the half adder is reduced, and therefore the performance of the AI chip is improved.
The machine learning arithmetic device provided by the embodiment of the invention comprises one or more full adders and/or one or more half adders; the machine learning arithmetic device is used for acquiring data to be operated and control information from other processing devices, executing specified machine learning arithmetic and transmitting an execution result to other processing devices through an I/O interface;
when the machine learning operation device comprises a plurality of full adders and/or half adders, the full adders and/or the half adders can be linked through a specific structure and transmit data;
the full adders and/or the half adders are/is connected with each other through a PCIE bus and transmit data so as to support larger-scale machine learning operation; a plurality of full adders and/or a plurality of half adders share the same control system or own respective control systems; the full adders and/or the half adders share a memory or own respective memories; the interconnection mode of the data comparators is any interconnection topology.
The combined processing device provided by the embodiment of the invention comprises the machine learning processing device, the universal interconnection interface and other processing devices; the machine learning arithmetic device interacts with the other processing devices to jointly complete the operation appointed by the user; the combined processing device may further include a storage device, which is connected to the machine learning arithmetic device and the other processing device, respectively, and is configured to store data of the machine learning arithmetic device and the other processing device.
The neural network chip provided by the embodiment of the invention comprises the full adder and/or the half adder, the machine learning arithmetic device or the combined processing device.
The neural network chip packaging structure provided by the embodiment of the invention comprises the neural network chip.
The board card provided by the embodiment of the invention comprises the neural network chip packaging structure.
The embodiment of the invention provides an electronic device which comprises the neural network chip or the board card.
The chip provided by the embodiment of the invention comprises at least one full adder as described in any one of the above and/or at least one half adder as described in any one of the above.
The electronic equipment provided by the embodiment of the invention comprises the chip.
Drawings
Fig. 1 is a schematic structural diagram of a full adder according to an embodiment;
FIG. 2 is a schematic diagram of a half adder according to an embodiment;
fig. 3 is a schematic structural diagram of a full adder according to another embodiment;
fig. 4 is a schematic diagram of a detailed structure of an adder sub-circuit according to another embodiment;
fig. 5 is a schematic structural diagram of a half adder according to another embodiment;
FIG. 6 is a flowchart illustrating a data processing method according to an embodiment;
FIG. 7 is a flowchart illustrating another data processing method according to another embodiment;
FIG. 8 is a block diagram of a combined processing device according to an embodiment;
FIG. 9 is a block diagram of another integrated processing device according to an embodiment;
fig. 10 is a schematic structural diagram of a board card according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The full adder and the half adder provided by the application can be applied to an AI chip, a Field-Programmable Gate Array (FPGA) chip, or other hardware circuit devices for operation processing, and the specific structural schematic diagrams thereof are respectively shown in fig. 1 and fig. 2.
Fig. 1 is a schematic structural diagram of a full adder according to an embodiment. The full adder includes: a logic circuit 11, a first gate circuit 12, a second gate circuit 13, and a selection circuit 14; the output end of the logic circuit 11 is connected to the input end of the first gating circuit 12 and the first input end of the selection circuit 14, the output end of the first gating circuit 12 is connected to the input end of the second gating circuit 13 and the second input end of the selection circuit 14, and the output end of the second gating circuit 13 is connected to the third input end of the selection circuit 14. The logic circuit 11 is configured to perform a logic operation on received data to obtain a first control signal, the first gating circuit 12 is configured to determine whether to gate the data according to the first control signal and perform a combinational logic operation on the data to obtain a second control signal, the second gating circuit 13 is configured to determine whether to gate the data according to the second control signal and perform an arithmetic operation on the data to obtain an arithmetic operation result, and the selection circuit 14 is configured to determine a target operation result according to the received first control signal, the second control signal, or the arithmetic operation result.
Specifically, the full adder may receive three values and perform addition operation on the three values, where the logic circuit 11 may perform logic operation on the received three values to obtain the first control signal. Alternatively, the three values received by the logic circuit 11 may be binary values 0 or 1, and the logic operation may be an or logic operation. In this embodiment, 0 may represent a low level signal, and 1 may represent a high level signal. Alternatively, the first control signal may be a result of a logic operation performed by the logic circuit 11, and the first control signal may be input to the first gating circuit 12 and the selection circuit 14 at the same time. The full adder can select to close the first gating circuit 12 and the second gating circuit 13 according to the first control signal, and directly output the target operation result through the selection circuit 14, or the full adder needs to open the first gating circuit 12 and/or the second gating circuit 13, and only after performing combinational logic operation and/or arithmetic operation on the received three values, can the full adder output the target operation result through the selection circuit 14. Alternatively, the arithmetic operation may be an addition operation.
The first gating circuit 12 determines three values that can be received by the gating logic circuit 11 based on the received first control signal, and performs a combinational logic operation on the three values after gating to obtain a second control signal, and the second control signal can be simultaneously input to the second gating circuit 13 and the selection circuit 14. The full adder may determine to close the second gating circuit 13 according to the second control signal, and directly output the target operation result through the selection circuit 14, or the full adder may further need to open the second gating circuit 13, and only after performing arithmetic operation on the received three values, may output the target operation result through the selection circuit 14. Optionally, the second gating circuit 13 determines, according to the received second control signal, that the three values received by the first gating circuit 12 can be gated, and performs arithmetic operation on the three values after gating to obtain an arithmetic operation result, meanwhile, the second gating circuit 13 may input the arithmetic operation result to the selection circuit 14, and the selection circuit 14 outputs the arithmetic operation result as a target operation result. Alternatively, the arithmetic operation result may include a sum signal and a carry signal obtained by adding three values.
Optionally, the logic circuit 11 includes: or gate logic circuitry 111, said or gate logic circuitry 111 for performing an or logic operation on said received data.
The first gating circuit 12 may include a combinational logic sub-circuit, which may be a circuit combining an and gate logic circuit and an or gate logic circuit, and the second gating circuit 13 may include a combinational logic sub-circuit, which may be a circuit combining an xor gate logic circuit, an and gate logic circuit, and an or gate logic circuit. Alternatively, the gating circuit 14 may include a plurality of data processing sub-circuits having the same function, and the circuit structures of the data processing sub-circuits having the same function may be the same. Optionally, the two signals in the target operation result may be different from the two signals in the arithmetic operation result, or may be different.
Alternatively, the three values received by the logic circuit 11 may include all 0's and at least one 1's. If all three values received by the logic circuit 11 are 0 and the first control signal is 0, the first control signal may be input to the first gating circuit 12 and the selection circuit 14; at this time, the selection circuit 14 may directly output the target operation result, and close the first gating circuit 12 and the second gating circuit 13, where both signals in the target operation result are 0; if at least one 1 exists in the three values received by the logic circuit 11, the first control signal may be 1, and the first control signal may be input to the first gating circuit 12 and the selection circuit 14, at this time, after the first gating circuit 12 needs to be turned on to gate the three values, the three values are subjected to combinational logic operation, and a second control signal may be obtained.
In the full adder provided by this embodiment, a logic circuit performs logic operation on received data to obtain a first control signal, and determines whether other circuits in the full adder can be turned off according to the first control signal, and directly outputs a target operation result through a selection circuit, if not, the full adder needs to perform combinational logic operation and/or arithmetic operation on the received data through a first gating circuit and/or a second gating circuit to obtain a target operation result, and this process may selectively turn off some circuits in the full adder, reduce power consumption of the full adder, and thereby improve performance of an AI chip.
Fig. 3 is a schematic structural diagram of a full adder according to another embodiment, where the full adder includes the first gating circuit 12, and the first gating circuit 12 includes: a first gating sub-circuit 121 and a combinational logic sub-circuit 122, wherein the output end of the first gating sub-circuit 121 is connected with the input end of the combinational logic sub-circuit 122; the first gating sub-circuit 121 is configured to determine whether to gate the data according to the received first control signal, and the combinational logic sub-circuit 122 is configured to perform combinational logic operation on the data gated by the first gating sub-circuit 121.
Specifically, if the first control signal received by the first gating circuit 12 is 1, the full adder starts the first gating circuit 12 to gate three values, and performs combinational logic operation on the three values through the combinational logic sub-circuit 122, where the three values after gating by the first gating circuit 12 may be the same as the three values received by the logic circuit 11.
Optionally, the combinational logic sub-circuit 122 includes: a plurality of and gate logic units 1221 and 1222, wherein the output terminals of the and gate logic units 1221 are connected to the input terminal of the or gate logic unit 1222; the plurality of and gate logic units 1221 are configured to perform an and logic operation on the data gated by the first gating circuit 12 to obtain an and logic operation result, and the or gate logic unit 1222 is configured to perform an or logic operation on the and logic operation result to obtain the second control signal.
It should be noted that, if there is at least one 1 in the three values received by the logic circuit 11, this case may also include a case where there is one 1 in the three values, a case where there are two 1 s, and a case where there are three 1 s. Optionally, the combinational logic sub-circuit 122 may include three and gate logic units 1221 and one or gate logic circuit 1222, where functions and internal circuit structures of the three and gate logic units 1221 are the same, and each and gate logic unit 1221 may receive any two values of the three values gated by the first gating sub-circuit 121, and it may be further understood that the three values are arranged and combined, and each group selects two values, so that three groups of data may be obtained by waiting for the three groups of data to be respectively input to the three and gate logic units 1221 to respectively perform an and logic operation, and the three and logic operation results are input to the or gate logic unit 1222 to perform an or logic operation, so as to obtain the second control signal.
For example, if there is one 1 and two 0 in three values gated by the first gating sub-circuit 121, the combinational logic sub-circuit 122 may perform an and logic operation on every two of the three values to obtain three and logic operation results, which may be all 0, and perform an or logic operation on the three results to obtain a second control signal, which may be 0, at this time, the second control signal may be input to the second gating circuit 13 and the selection circuit 14, the full adder may close the second gating circuit 13, and the selection circuit 14 may directly output a target operation result according to the received second control signal, where the target operation result has a neutral bit output signal of 1 and a carry output signal of 0; if two 1 s or one 0 s or three 1 s exist in the three values received by the logic circuit 11, performing an and logic operation on every two of the three values to obtain three and logic operation results, and performing an or logic operation on the three operation results to obtain a second control signal, where the second control signal may be 1, at this time, the second control signal may be input to the second gating circuit 13 and the selection circuit 14, and the full adder starts the second gating circuit 13 to perform subsequent processing on the three values to obtain a target operation result. Optionally, the value of the carry signal and the value of the sum signal in the target operation result may be determined according to the three values received by the full adder, and the determination rule may refer to the logic relation truth table shown in table 1, where the carry input signal C in The summand A and the summand B can be three values received by the full adder, and the sum signal S and the carry signal C out Can be used as the sum signal and the carry signal in the target operation result.
TABLE 1 full adder truth table
Figure BDA0001926387750000101
In the full adder provided in this embodiment, if the first gating circuit determines, according to the first control signal, that the full adder needs to be turned on, the first gating circuit may perform a logic operation on data received by the full adder to obtain a second control signal, and determine whether to directly output a target operation result according to the second control signal, and if not, the data needs to be input to the second gating circuit to perform an arithmetic operation to obtain a target operation.
Fig. 3 is a schematic structural diagram of a full adder according to another embodiment, where the full adder includes the second gating circuit 13, and the second gating circuit 13 includes: a second gating sub-circuit 131 and an adding sub-circuit 132, wherein the output end of the second gating sub-circuit 131 is connected with the input end of the adding sub-circuit 132; the second gating sub-circuit 131 is configured to determine whether to gate the data according to the received second control signal, and the adding sub-circuit 132 is configured to add the data gated by the second gating sub-circuit 131 to obtain an addition operation result.
Specifically, if the second control signal received by the second gating circuit 13 is 1, the full adder starts the second gating circuit 13 to gate three values, and performs logic operation on the three values through the adding sub-circuit 132 to implement addition processing, where the three values gated by the second gating sub-circuit 131 may be the same as the three values received by the logic circuit 11.
Alternatively, the summing sub-circuit 132 may be formed by combining different logic gate units.
Optionally, fig. 4 is a schematic diagram of a specific structure of the adding sub-circuit 132, where the adding sub-circuit 132 may include: an exclusive-or gate logic unit 1321, an and gate logic unit 1322 and an or gate logic unit 1323, wherein the output ends of the exclusive-or gate logic units 1321 are connected with the input end of the and gate logic unit 1322, and the output end of the and gate logic unit 1322 is connected with the input end of the or gate logic unit 1323; the plurality of xor gate logic units 1321 are configured to perform an xor logic operation on the received data, the plurality of and gate logic units 1322 are configured to perform an and logic operation on the received data to obtain an and logic operation result, and the or gate logic unit 1323 is configured to perform an or logic operation on the and logic operation result.
It should be noted that only when more than two values among the three values received by the full adder are 1, the full adder may turn on the second gating circuit 13, gate the three values through the second gating sub-circuit 131 in the second gating circuit 13, and perform combinational logic operation on the received three values through the adding sub-circuit 132 to implement addition processing. Optionally, as shown in fig. 4, the first stage xor gate logic unit 1321 may receive any two of the three values to perform an xor operation to obtain an xor operation result, and then the second stage xor gate logic unit 1322 may perform an xor operation on the xor operation result and one of the three values that is not subjected to the first stage xor operation to obtain a sum bit output signal obtained by adding the three values. In addition, one of the and logic units 1322 may perform an and logic operation on the two values received by the first stage xor gate logic unit 1321 to obtain an and logic operation result, the other and logic unit 1322 may perform an and logic operation on the xor logic operation result obtained by the first stage xor gate logic unit 1321 and one of the three values that is not subjected to the and logic operation, so as to obtain another and logic operation result, and finally, the or logic unit 1323 may perform an or logic operation on the two and logic operation results to obtain a carry output signal obtained by adding the three values.
In the full adder provided in this embodiment, the full adder may selectively turn off a part of circuits in the full adder according to the obtained second control signal, so as to reduce power consumption of the full adder and improve performance of the AI chip.
As one embodiment, with continued reference to fig. 3, a full adder includes a selection circuit 14, the selection circuit 14 including: and a plurality of selection sub-circuits 141, wherein the plurality of selection sub-circuits 141 are configured to determine a target operation result according to the received first control signal, the second control signal, or the addition operation result.
Specifically, the selection circuit 14 may include two selection sub-circuits 141, the functions of the two selection sub-circuits 141 may be the same, and the internal circuit configuration may also be the same. Optionally, one of the selection sub-circuits 141 may include four input terminals, one of which may receive the first control signal output by the logic circuit 11, the other of which may receive the second control signal output by the second gating circuit 12, one of the other two of which may receive the value 0, and the other of which may receive the carry output signal output by the addition sub-circuit 132; however, another selection sub-circuit 141 may include five input terminals, one of which may receive the first control signal output by the logic circuit 11, another of which may receive the second control signal output by the second gating circuit 12, two of which may receive the value 0 and the value 1, respectively, and an input terminal which may receive the sum bit output signal output by the addition sub-circuit 132.
It should be noted that, when the first control signal output by the logic circuit 11 is 0, it indicates that the three values received by the full adder are all 0, at this time, both the two selection sub-circuits 141 can gate the value 0 to be respectively used as a carry signal and a sum signal in the target operation result, and when the first control signal output by the logic circuit 11 is 1, it indicates that at least one 1 exists in the three values received by the full adder, and at this time, the first gating circuit 12 needs to be started to perform subsequent processing on the three values to obtain the target operation result; when the second control signal output by the first gating circuit 12 is 0, it indicates that there is one 1 in the three values received by the full adder, at this time, the selection sub-circuit 141 may gate the value 1 as a sum signal in the target operation result, and the other selection sub-circuit 141 gates the value 0 as a carry signal in the target operation result; in addition, when the second control signal output by the first gating circuit 12 is 1, it indicates that at least two 1 values exist in the three values received by the full adder, and at this time, the full adder may start the second selection circuit 13 to perform subsequent processing on the three values, perform addition processing on the three values through the addition sub-circuit 132 to obtain a sum output signal and a carry output signal, and output the two signals as a target operation result.
Optionally, the first control signals received by the two selection sub-circuits 141 in the selection circuit 14 may be the same, and may receive the first control signals at the same time, and in addition, the second control signals received may be the same, or may receive the second control signals at the same time.
In the full adder provided in this embodiment, the full adder may determine whether a part of circuits may be turned off according to the obtained first control signal and the second control signal, and the selection circuit may determine the target operation result according to the received first control signal and the second control signal, and the process may selectively turn off a partial product circuit in the full adder, directly output the target operation result, and reduce power consumption of the full adder, so as to improve performance of the AI chip.
Fig. 2 is a schematic structural diagram of a half adder according to an embodiment. The half adder includes: a logic circuit 21, a gate circuit 22, and a selection circuit 23; the output terminal of the logic circuit 21 is connected to the input terminal of the gating circuit 22 and the first input terminal of the selection circuit 23, and the output terminal of the gating circuit 22 is connected to the second input terminal of the selection circuit 23. The logic circuit 21 is configured to perform a logic operation on received data to obtain a first control signal, the gating circuit 22 is configured to determine whether to gate the data according to the first control signal and perform a logic operation on the data to obtain a second control signal, and the selection circuit 23 is configured to determine a target operation result according to the received first control signal or the received second control signal.
Specifically, the half adder may receive two values and perform an addition operation on the two values, where the logic circuit 21 may perform a logic operation on the received two values to obtain the first control signal. Alternatively, both values received by the logic circuit 21 may be binary values 0 or 1, and the logic operation may be an or logic operation. Alternatively, the first control signal may be a result of a logic operation performed by the logic circuit 21, and the first control signal may be input to the gate circuit 22 and the selection circuit 23 at the same time. The half adder may determine to turn off the gate circuit 22 according to the first control signal, and directly output the target operation result through the selection circuit 23.
In addition, if the gating circuit 22 determines that two values can be gated according to the received first control signal, and performs a logic operation on the two values to obtain the second control signal, the second control signal may be a result of the logic operation performed by the gating circuit 22, and the second control signal may be input to the selection circuit 23, and the selection circuit 23 may determine an output target operation result according to the received second control signal.
Optionally, the logic circuit 21 includes: an OR gate logic circuit 211, the OR gate logic circuit 211 for OR-ing the received data.
It should be noted that the gating circuit 22 may include a plurality of data processing sub-circuits with different functions, and the circuit structures of the data processing sub-circuits with different functions may be different. Optionally, the target operation result may include a sum signal and a carry signal obtained by adding two values.
Alternatively, the two values received by the logic circuit 21 may include all 0's and at least one 1's. If the two values received by the logic circuit 21 are all 0 and the first control signal is 0, the first control signal may be input to the gating circuit 22 and the selection circuit 23, at this time, the selection circuit 23 may directly output a target operation result, the gating circuit 22 is turned off, and both signals in the target operation result are 0; if at least one of the two values received by the logic circuit 21 has 1, the first control signal may be 1, and the first control signal may be input to the gating circuit 22 and the selection circuit 23, at this time, after the gating circuit 22 needs to be turned on to gate the two values, the two values are subjected to logic operation, so as to obtain a second control signal.
According to the half adder provided by the embodiment, the logic operation is performed on the received data through the logic circuit to obtain the first control signal, whether the gating circuit in the half adder can be closed is judged according to the first control signal, the target operation result is directly output through the selection circuit, if not, the half adder needs to perform the logic operation on the received data through the gating circuit to obtain the second control signal, and then the target operation result is obtained according to the second control signal.
Fig. 5 is a schematic diagram of a specific structure of a half adder according to another embodiment, where the half adder includes the gating circuit 22, and the gating circuit 22 includes: a gating sub-circuit 221 and a logic sub-circuit 222, wherein the output end of the gating sub-circuit 221 is connected with the input end of the logic sub-circuit 222; the gating sub-circuit 221 is configured to determine whether to gate the data according to the received first control signal, and the logic sub-circuit 222 is configured to perform a logic operation on the data gated by the gating sub-circuit 221.
Specifically, if the first control signal received by the gating circuit 22 is 1, the half adder turns on the gating circuit 22 to gate two values, and performs a logic operation on the two values through the logic sub-circuit 222, where the two values gated by the gating circuit 22 and the two values received by the logic circuit 21 may be the same.
Optionally, the logic sub-circuit 222 includes: and gate logic unit 2221; the and gate logic unit 2221 is configured to perform an and logic operation on the data gated by the gating circuit 22 to obtain the second control signal.
It should be noted that, if there is at least one 1 in the two values received by the logic circuit 21, this case may also include a case where there is one 1 in the two values and a case where there are two 1 s. Optionally, the logic sub-circuit 222 may include an and gate logic unit 2221, and the and gate logic unit 2221 may receive two values gated by the gating sub-circuit 221, and perform an and logic operation on the two values to obtain the second control signal.
For example, if there is one 1 and one 0 in the two values received by the logic circuit 21, the and logic operation result obtained after performing the and logic operation on the two values may be 0, and the and logic operation result may be the second control signal, in this case, the second control signal may be input to the selection circuit 23, and the selection circuit 23 may output the target operation result according to the second control signal. Optionally, the value of the carry signal and the value of the sum signal in the target operation result may be determined according to two values received by the half adder, and the determination rule may refer to a truth table of logic relationship shown in table 2, where the summand a and the summand B may be used as two values received by the half adder, the sum signal S and the carry signal C out Can be used as the sum signal and the carry signal in the target operation result.
TABLE 2 half adder truth table
Figure BDA0001926387750000151
According to the half adder provided by the embodiment, if the gating circuit judges that the half adder needs to open the gating circuit according to the first control signal, the gating circuit can perform logic operation on data received by the half adder to obtain the second control signal, and determines an output target operation result according to the second control signal.
Continuing with reference to fig. 5, as one embodiment, the half adder includes a selection circuit 23, the selection circuit 23 including: and a plurality of selection sub-circuits 231, wherein the plurality of selection sub-circuits 231 are used for determining and outputting a target operation result according to the received first control signal or the second control signal.
Specifically, the selection circuit 23 may include two selection sub-circuits 231, the functions of the two selection sub-circuits 231 may be the same, and the internal circuit configuration may also be the same. The two selection sub-circuits 231 may have four input terminals, two of the input terminals may receive the second control signal output by the and logic unit 2221 of the logic sub-circuit 222 and the first control signal output by the logic circuit 21, respectively, and the other two input terminals may receive the values 0 and 1. Alternatively, the two selection sub-circuits 231 may determine, according to the received first control signal or the received second control signal, whether to receive the value 0 or receive the value 1 to output as the target operation result, and a signal output by one of the selection sub-circuits 231 is a carry signal in the target operation result, and a signal output by the other selection sub-circuit 231 is a sum signal in the target operation result.
It should be noted that, when the first control signal output by the logic circuit 21 is 0, it indicates that the two values received by the half adder are both 0, at this time, both the two selection sub-circuits 231 may gate the value 0 as a carry signal and a sum signal in the target operation result, and when the first control signal output by the logic circuit 11 is 1, it indicates that at least one 1 exists in the two values received by the half adder, and at this time, the gating circuit 22 needs to be turned on to perform subsequent processing on the two values to obtain the target operation result; when the second control signal output by the gating circuit 22 is 0, it indicates that there is one 1 in the two values received by the half adder, and at this time, the selection sub-circuit 231 outputting the sum bit signal may gate the value 1 as the sum bit signal in the target operation result, and the other selection sub-circuit 231 gates the value 0 as the carry signal in the target operation result; in addition, when the second control signal output by the gating circuit 22 is 1, it indicates that the two values received by the half adder are both 1, and at this time, the selection sub-circuit 231 outputting the sum bit signal may gate the value 0 as the sum bit signal in the target operation result, and the other selection sub-circuit 231 may gate the value 1 as the carry signal in the target operation result.
In the half adder provided by this embodiment, the half adder may determine whether a part of circuits may be turned off according to the obtained first control signal and the second control signal, and the selection circuit may determine the target operation result according to the received first control signal and the second control signal, and this process may selectively turn off a partial product circuit in the half adder, directly output the target operation result, and reduce power consumption of the half adder, so as to improve performance of the AI chip.
Fig. 6 is a flowchart illustrating a data processing method according to an embodiment, which may be processed by the full adder shown in fig. 1 and fig. 3, where the embodiment relates to a process of adding data. As shown in fig. 6, the method includes:
s101, receiving data to be processed.
Specifically, the logic circuit, the first gating circuit and the second gating circuit in the full adder may all receive three data to be processed, and each data to be processed may be a binary value 0 or 1.
S102, performing first logic operation processing on the data to be processed to obtain a first control signal.
Specifically, the logic circuit may perform a first logic operation on the three data to be processed to obtain a first control signal. Optionally, the first control signal may be a high-level signal 1, and may also be a low-level signal 0.
Alternatively, the first logical operation processing may include or gate logical operation processing.
S103, if the data to be processed does not need to be subjected to second logic operation processing according to the first control signal, gating the data to be processed, and carrying out AND logic operation on the data to be processed to obtain a second control signal.
Specifically, the full adder may determine that the three pieces of data to be processed do not need to perform the second logic operation according to the first control signal obtained by the logic circuit, and then the two selection sub-circuits in the selection circuit may determine the strobe value 0 as the target operation result according to the received first control signal, at this time, the first control signal may be the low level signal 0. Optionally, the target operation result may include a carry signal and a sum signal.
Optionally, the second logical operation processing may include: and gates and or gates combine logical operations.
In the data processing method provided by this embodiment, to-be-processed data is received, a first logic operation process is performed on the to-be-processed data to obtain a first control signal, and if it is determined that the to-be-processed data does not need to undergo a second logic operation process according to the first control signal, a target operation result is output according to the first control signal.
In one embodiment, the method further comprises:
s105, if the data to be processed needs to be subjected to the second logic operation processing according to the first control signal, gating the data to be processed, and performing second logic operation on the data to be processed to obtain a second control signal.
Specifically, if the full adder determines that the second logic operation processing needs to be performed on the three data to be processed according to the first control signal obtained by the logic circuit, the first gating sub-circuit in the first gating circuit may gate the three data to be processed, and perform the and logic operation on the three data to be processed through the combinational logic sub-circuit in the first gating circuit, and then perform the or logic operation on the result of the and logic operation, and use the result of the or logic operation as the second control signal. Alternatively, the second control signal may be a high-level signal 1, and may also be a low-level signal 0.
It should be noted that, if there is at least one 1 in the three pieces of data to be processed received by the logic circuit, this case may also include a case where there is one 1, a case where there are two 1 s, and a case where there are three 1 s in the three pieces of data to be processed. Optionally, the full adder performs combinational logic operation on the three data to be processed through three and gate logic units and one or gate logic circuit included in the combinational logic sub-circuit to obtain the second control signal.
Illustratively, ifIf one 1 or two 0 exists in the three data to be processed received by the logic circuit, performing and logic operation on the three data to be processed to obtain three and logic operation results which may be all 0, and performing or logic operation on the three results to obtain a second control signal, where the second control signal may be 0, at this time, the second control signal may be input to the second gating circuit and the selection circuit, and the selection circuit may directly output a target operation result, where a neutralization bit signal in the target operation result may be 1, and a carry signal is 0; if two 1 s and one 0 s exist in the three data to be processed received by the logic circuit, or the three data to be processed are all 1 s, performing and logic operation on the three data to be processed to obtain three and logic operation results, and performing or logic operation on the three operation results to obtain a second control signal, wherein the second control signal can be 1, at the moment, the second control signal can be input to the second gating circuit and the selection circuit, and the full adder performs subsequent processing on the three data to be processed by starting the second gating circuit to obtain a target operation result. Optionally, the value of the carry signal and the value of the sum signal in the target operation result may be determined according to three to-be-processed data received by the full adder, and the determination rule may refer to a logic relation truth table shown in table 1, where the carry input signal C is a carry input signal in The summand A and the summand B can be used as three data to be processed received by a full adder, a sum signal S and a carry signal C out Can be used as the sum signal and the carry signal in the target operation result.
And S106, if the data to be processed does not need to be subjected to arithmetic operation processing according to the second control signal, outputting a target operation result.
Specifically, the full adder may determine, according to the second control signal obtained by the first gating circuit, that the three pieces of to-be-processed data received by the full adder do not need to be subjected to arithmetic operation processing operation, at this time, the second control signal may be a low level signal 0, and it is described that one 1 or two 0 s exist in the three pieces of to-be-processed data received by the full adder, and at this time, the selection circuit may output a carry signal in the target operation result as the low level signal 0 and a bit signal as the high level signal 1.
In the data processing method provided in this embodiment, if the full adder needs to perform the second logic operation, the data to be processed is gated, and the second logic operation is performed on the data to be processed to obtain the second control signal, and if it is determined that the data to be processed does not need to be subjected to the arithmetic operation processing according to the second control signal, the target operation result is output.
In one embodiment, after the step of obtaining the second control signal in S105, the method further includes:
s1061, if the data to be processed needs to be subjected to the arithmetic operation processing according to the second control signal, gating the data to be processed, and performing the arithmetic operation on the processing to be processed to obtain an arithmetic operation result.
Alternatively, the arithmetic operation processing may include an exclusive or logic operation, an and logic operation, and or logic operation.
It should be noted that, when more than two pieces of data to be processed are 1 in the three pieces of data to be processed received by the full adder, the full adder may gate the three pieces of data to be processed through the second gating sub-circuit in the second gating circuit, and perform logical operation on the three pieces of data to be processed received through the adding sub-circuit to implement addition processing, so as to obtain an arithmetic operation result. For example, the addition sub-circuit may perform an exclusive or operation on any two data to be processed of the three data to be processed to obtain an exclusive or operation result, and then perform an exclusive or operation on the exclusive or operation result and another data to be processed that is not subjected to the exclusive or operation again to obtain an arithmetic operation result, which may be a sum bit output signal of the addition process. In addition, the two data to be processed which are subjected to the first exclusive-or logic operation are subjected to and logic operation to obtain an and logic operation result, and the and logic operation result and the result of the first exclusive-or logic operation are subjected to and logic operation to obtain an arithmetic operation result, wherein the arithmetic operation result can be a carry output signal of addition processing.
And S1062, outputting a target operation result according to the arithmetic operation result.
Optionally, the sum bit output signal obtained by the adding sub-circuit may be used as the sum bit signal in the target operation result, and the carry output signal obtained by the adding sub-circuit may be used as the carry signal in the target operation result.
In the data processing method provided by this embodiment, if the full adder needs to perform the arithmetic operation, the data to be processed is gated, and the arithmetic operation is performed on the data to be processed to obtain an arithmetic operation result, and a target operation result is output according to the arithmetic operation result.
Fig. 7 is a flowchart illustrating a data processing method according to an embodiment, which may be processed by the half adder shown in fig. 2 and fig. 5, where the embodiment relates to a process of adding data. As shown in fig. 7, the method includes:
s201, receiving data to be processed.
Specifically, the logic circuit and the gating circuit in the half adder can simultaneously receive two data to be processed, and each data to be processed can be a binary value of 0 or 1.
S202, performing OR logic operation processing on the data to be processed to obtain a first control signal.
Specifically, the logic circuit may perform an or logic operation on two data to be processed to obtain the first control signal. Optionally, the first control signal may be a high-level signal 1, and may also be a low-level signal 0.
S203, if the data to be processed does not need to be subjected to AND logic operation according to the first control signal, outputting a target operation result according to the first control signal.
It should be noted that, if the first control signal received by the gating circuit and the selection circuit is a low level signal 0, it indicates that the two pieces of data to be processed received by the half adder are both 0, at this time, the selection circuit may output a target operation result, where a carry signal in the output target operation result may be a low level signal 0, and a bit signal may also be a low level signal 0.
In the data processing method provided by this embodiment, to-be-processed data is received, or logic operation is performed on the to-be-processed data to obtain a first control signal, and if it is determined that the to-be-processed data does not need to perform and logic operation according to the first control signal, a target operation result is output according to the first control signal.
In one embodiment, the method further comprises:
s204, if the data to be processed needs to be subjected to the AND logic operation processing according to the first control signal, gating the data to be processed, and performing the AND logic operation on the data to be processed to obtain a second control signal.
Specifically, if the half adder needs to perform and logic operation on two pieces of data to be processed, the full adder may start the gating circuit to gate the two pieces of data to be processed, and perform and logic operation on the two pieces of data to be processed to obtain the second control signal. Alternatively, the second control signal may be a high-level signal 1, and may also be a low-level signal 0.
And S205, outputting a target operation result according to the second control signal.
It should be noted that, if the second control signal output to the selection circuit by the gating circuit in the half adder is a low-level signal 0, then one 0 and one 1 are correspondingly input to the half adder, at this time, the selection circuit may output a target operation result, where a sum bit signal in the target operation result may be 1, and carry signals may all be 0; if the second control signal output to the selection circuit by the gating circuit in the half adder is a high-level signal 1, two 1 s are correspondingly input to the half adder, and at this time, the selection circuit can output a target operation result, wherein the sum signal in the target operation result can be 0, and the carry signal can be 1.
In the data processing method provided by this embodiment, if the half adder needs to perform the and logic operation, the data to be processed is gated, and the and logic operation is performed on the data to be processed to obtain the second control signal, and the target operation result is output according to the second control signal.
The embodiment of the application also provides a machine learning arithmetic device which comprises one or more full adders and/or half adders mentioned in the application and is used for acquiring data to be operated and control information from other processing devices, executing specified machine learning arithmetic and transmitting the execution result to peripheral equipment through an I/O interface. Peripheral devices such as cameras, displays, mice, keyboards, network cards, wifi interfaces, servers. When more than one full adder and/or half adder is included, the full adder and/or half adder can be linked and transmit data through a specific structure, for example, through the PCIE bus to interconnect and transmit data, so as to support larger-scale machine learning operations. At this time, the same control system may be shared, or there may be separate control systems; the memory may be shared or there may be separate memories for each accelerator. In addition, the interconnection mode can be any interconnection topology.
The machine learning arithmetic device has higher compatibility and can be connected with various types of servers through PCIE interfaces.
The embodiment of the application also provides a combined processing device which comprises the machine learning arithmetic device, the universal interconnection interface and other processing devices. The machine learning arithmetic device interacts with other processing devices to jointly complete the operation designated by the user. Fig. 8 is a schematic view of a combined treatment apparatus.
Other processing devices include one or more of general purpose/special purpose processors such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), neural network processors, and the like. The number of processors included in the other processing devices is not limited. The other processing devices are used as interfaces of the machine learning arithmetic device and external data and control, and comprise data transportation to finish basic control of starting, stopping and the like of the machine learning arithmetic device; other processing devices can cooperate with the machine learning calculation device to complete calculation tasks.
And the universal interconnection interface is used for transmitting data and control instructions between the machine learning arithmetic device and other processing devices. The machine learning arithmetic device obtains the required input data from other processing devices and writes the input data into a storage device on the machine learning arithmetic device; control instructions can be obtained from other processing devices and written into a control cache on a machine learning arithmetic device chip; the data in the storage module of the machine learning arithmetic device can also be read and transmitted to other processing devices.
Alternatively, as shown in fig. 9, the configuration may further include a storage device, and the storage device is connected to the machine learning arithmetic device and the other processing device, respectively. The storage device is used for storing data in the machine learning arithmetic device and the other processing device, and is particularly suitable for data which is required to be calculated and cannot be stored in the internal storage of the machine learning arithmetic device or the other processing device.
The combined processing device can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video monitoring equipment, the core area of a control part is effectively reduced, the processing speed is increased, and the overall power consumption is reduced. In this case, the generic interconnect interface of the combined processing device is connected to some component of the apparatus. Some parts are such as camera, display, mouse, keyboard, network card, wifi interface.
In some embodiments, a chip is also claimed, which includes the above machine learning arithmetic device or the combined processing device.
In some embodiments, a chip package structure is provided, which includes the above chip.
In some embodiments, a board card is provided, which includes the above chip package structure. As shown in fig. 10, fig. 10 provides a card that may include other kits in addition to the chip 389, including but not limited to: memory device 390, receiving device 391, and control device 392;
the memory device 390 is connected to the chip in the chip package structure through a bus for storing data. The memory device may include a plurality of groups of memory cells 393. Each group of the storage units is connected with the chip through a bus. It is understood that each group of the memory cells may be a DDR SDRAM (Double Data Rate SDRAM).
DDR can double up the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the storage device may include 4 sets of the storage unit. Each group of the memory cells may include a plurality of DDR4 particles (chips). In one embodiment, the chip may internally include 4 72-bit DDR4 controllers, and 64 bits of the 72-bit DDR4 controller are used for data transmission, and 8 bits are used for ECC check. It can be understood that when DDR4-3200 particles are adopted in each group of memory cells, the theoretical bandwidth of data transmission can reach 25600 MB/s.
In one embodiment, each group of the memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. And a controller for controlling DDR is arranged in the chip and is used for controlling data transmission and data storage of each memory unit.
The receiving device is electrically connected with the chip in the chip packaging structure. The receiving device is used for realizing data transmission between the chip and an external device (such as a server or a computer). For example, in one embodiment, the receiving device may be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through a standard PCIE interface, so that data transfer is realized. Preferably, when PCIE 3.0X 16 interface transmission is adopted, the theoretical bandwidth can reach 16000 MB/s. In another embodiment, the receiving device may also be another interface, and the present application does not limit the concrete expression of the other interface, and the interface unit may implement the switching function. In addition, the calculation result of the chip is still transmitted back to an external device (e.g., a server) by the receiving apparatus.
The control device is electrically connected with the chip. The control device is used for monitoring the state of the chip. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may include a single chip Microcomputer (MCU). The chip may include a plurality of processing chips, a plurality of processing cores, or a plurality of processing circuits, and may carry a plurality of loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation and control of the working states of a plurality of processing chips, a plurality of processing andor a plurality of processing circuits in the chip.
In some embodiments, an electronic device is provided that includes the above board card.
The electronic device may be a data processor, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.
The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.
It should be noted that, for simplicity of description, the foregoing method embodiments are described as a series of circuit combinations, but those skilled in the art should understand that the present application is not limited by the described circuit combinations, because some circuits may be implemented in other ways or structures according to the present application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are all alternative embodiments, and that the devices and modules referred to are not necessarily required for this application.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (25)

1. A full adder, comprising: the circuit comprises a logic circuit, a first gating circuit, a second gating circuit and a selection circuit; the output end of the logic circuit is connected with the input end of the first gating circuit and the first input end of the selection circuit, the output end of the first gating circuit is connected with the input end of the second gating circuit and the second input end of the selection circuit, and the output end of the second gating circuit is connected with the third input end of the selection circuit; the first gating circuit includes a combinational logic sub-circuit including: the second gating circuit comprises a second gating sub-circuit and an addition sub-circuit, the addition sub-circuit comprises a logic gate unit, the output end of the AND gate logic unit is connected with the input end of the OR gate logic unit, and the output end of the second gating sub-circuit is connected with the input end of the addition sub-circuit;
the logic circuit is configured to perform a logic operation on received data to obtain a first control signal, the first gating circuit is configured to determine whether to gate the data according to the first control signal, and perform a combinational logic operation on the data to obtain a second control signal, the second gating circuit is configured to determine whether to gate the data according to the second control signal, and perform an arithmetic operation on the data to obtain an arithmetic operation result, and the selection circuit is configured to determine a target operation result according to the received first control signal, the second control signal, or the arithmetic operation result.
2. The full adder according to claim 1, wherein the logic circuit comprises: an OR gate logic circuit to OR the received data.
3. The full adder according to claim 1, wherein the first gating circuit further comprises: the output end of the first gating sub-circuit is connected with the input end of the combinational logic sub-circuit;
the first gating sub-circuit is used for judging whether to gate the data according to the received first control signal, and the combinational logic sub-circuit is used for performing combinational logic operation on the data gated by the first gating sub-circuit.
4. The full adder according to claim 3, wherein the AND gate logic unit is configured to perform an AND logic operation on the data gated by the first gating circuit to obtain an AND logic operation result, and the OR gate logic unit is configured to perform an OR logic operation on the AND logic operation result to obtain the second control signal.
5. The full adder according to claim 1, wherein the second gating sub-circuit is configured to determine whether to gate the data according to the received second control signal, and the adding sub-circuit is configured to add the data gated by the second gating sub-circuit to obtain an addition result.
6. The full adder according to claim 1, wherein the adder sub-circuit is formed by combining different logic gate units.
7. The full adder according to claim 6, wherein the adder sub-circuit comprises: the output end of the exclusive-OR gate logic unit is connected with the input end of the AND gate logic unit, and the output end of the AND gate logic unit is connected with the input end of the OR gate logic unit;
the exclusive-or gate logic unit is configured to perform exclusive-or logic operation on the received data, the and gate logic unit is configured to perform and logic operation on the received data to obtain an and logic operation result, and the or gate logic unit is configured to perform or logic operation on the and logic operation result.
8. The full adder according to claim 6, wherein the selection circuit comprises: a selection sub-circuit for determining a target operation result based on the received first control signal, second control signal, or addition operation result.
9. A half adder, comprising: a logic circuit, a gating circuit and a selection circuit; the output end of the logic circuit is connected with the input end of the gating circuit and the first input end of the selection circuit, and the output end of the gating circuit is connected with the second input end of the selection circuit;
the selection circuit is used for determining a target operation result according to the received first control signal or the received second control signal.
10. The half-adder of claim 9, wherein the logic circuit comprises: an OR gate logic circuit to OR the received data.
11. The half-adder according to claim 9, wherein the gating circuit comprises: the output end of the gating sub-circuit is connected with the input end of the logic sub-circuit; the gating sub-circuit is used for judging whether to gate the data according to the received first control signal, and the logic sub-circuit is used for carrying out logic operation on the data gated by the gating sub-circuit.
12. The half-adder of claim 11, wherein the logic subcircuit comprises: an AND gate logic unit; and the AND gate logic unit is used for carrying out AND logic operation on the data after being gated by the gating circuit to obtain the second control signal.
13. The half-adder according to claim 9, wherein the selection circuit comprises: and the selection sub-circuits are used for determining and outputting a target operation result according to the received first control signal or the second control signal.
14. A method of data processing, the method comprising:
receiving data to be processed;
performing first logic operation processing on the data to be processed to obtain a first control signal;
if the data to be processed does not need to be subjected to second logic operation processing according to the first control signal, outputting a target operation result according to the first control signal;
the second logic operation processing comprises AND gate and OR gate combined logic operation processing; the steps in the data processing method are implemented by a full adder according to any of claims 1 to 8.
15. The method of claim 14, further comprising:
if the data to be processed needs to be subjected to the second logic operation processing according to the first control signal, gating the data to be processed, and performing second logic operation on the data to be processed to obtain a second control signal;
and if the data to be processed does not need to be subjected to arithmetic operation processing according to the second control signal, outputting a target operation result.
16. The method of claim 15, wherein after obtaining the second control signal, further comprising:
if the data to be processed needs to be subjected to the arithmetic operation processing according to the second control signal, gating the data to be processed, and performing arithmetic operation on the data to be processed to obtain an arithmetic operation result;
and outputting a target operation result according to the arithmetic operation result.
17. A method of data processing, the method comprising:
receiving data to be processed;
performing OR logic operation processing on the data to be processed to obtain a first control signal;
if the data to be processed does not need to be subjected to AND logic operation according to the first control signal, outputting a target operation result according to the first control signal;
wherein the steps in the data processing method are implemented by a half-adder according to any of claims 9-13.
18. The method of claim 17, further comprising:
if the data to be processed needs to be subjected to the AND logic operation processing according to the first control signal, gating the data to be processed, and performing the AND logic operation on the data to be processed to obtain a second control signal;
and outputting a target operation result according to the second control signal.
19. A machine learning operation device, wherein the machine learning operation device comprises one or more full adders according to any one of claims 1 to 8 and/or one or more half adders according to any one of claims 9 to 13, and is configured to acquire input data and control information to be operated from other processing devices, execute a specified machine learning operation, and transmit the execution result to other processing devices through an I/O interface;
when the machine learning operation device comprises a plurality of full adders and/or half adders, the full adders and/or the half adders can be connected through a specific structure and transmit data;
the full adders and/or the half adders are/is connected with each other through a PCIE bus and transmit data so as to support larger-scale machine learning operation; a plurality of full adders and/or a plurality of half adders share the same control system or own respective control systems; the full adders and/or the half adders share a memory or own respective memories; the interconnection mode of the full adders and/or the half adders is any interconnection topology.
20. A combined processing apparatus, characterized in that the combined processing apparatus comprises the machine learning arithmetic apparatus according to claim 19, a universal interconnect interface and other processing apparatus;
and the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user.
21. The combined processing device according to claim 20, further comprising: and a storage device connected to the machine learning arithmetic device and the other processing device, respectively, for storing data of the machine learning arithmetic device and the other processing device.
22. A neural network chip comprising a machine learning computation device according to claim 19 or a combined processing device according to claim 20 or a combined processing device according to claim 21.
23. An electronic device comprising the neural network chip of claim 22.
24. The utility model provides a board card, its characterized in that, the board card includes: a memory device, a receiving device and a control device and a neural network chip as claimed in claim 22;
wherein the neural network chip is respectively connected with the storage device, the control device and the receiving device;
the storage device is used for storing data;
the receiving device is used for realizing data transmission between the chip and external equipment;
and the control device is used for monitoring the state of the chip.
25. The board of claim 24,
the memory device includes: a plurality of groups of memory cells, each group of memory cells is connected with the chip through a bus, and the memory cells are: DDR SDRAM;
the chip includes: the DDR controller is used for controlling data transmission and data storage of each memory unit;
the receiving device is as follows: a standard PCIE interface.
CN201811618768.XA 2018-11-30 2018-12-28 Full adder, half adder, data processing method, chip and electronic equipment Active CN111384944B (en)

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Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0098692A3 (en) * 1982-07-01 1986-04-16 Hewlett-Packard Company Apparatus for adding first and second binary operands
JPS60247734A (en) * 1984-05-24 1985-12-07 Toshiba Corp Logical arithmetic circuit
JPH05233219A (en) * 1992-02-18 1993-09-10 Nec Ic Microcomput Syst Ltd Carry prefetching circuit for semiconductor integrated circuit
JPH07191831A (en) * 1993-12-27 1995-07-28 Fujitsu Ltd Arithmetic unit
JPH08161151A (en) * 1994-12-01 1996-06-21 Mitsubishi Electric Corp Adder
GB2373883A (en) * 2001-03-27 2002-10-02 Automatic Parallel Designs Ltd Logic circuit for performing binary addition or subtraction
US7653677B1 (en) * 2005-01-26 2010-01-26 Xilinx, Inc. Digital logic circuit for adding three binary words and method of implementing same
US8521801B2 (en) * 2008-04-28 2013-08-27 Altera Corporation Configurable hybrid adder circuitry
CN105468330A (en) * 2015-11-17 2016-04-06 绵阳市维博电子有限责任公司 16-bit adder based on conditional carry selection principle

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