CN111381803A

CN111381803A - Data comparator, data processing method, chip and electronic equipment

Info

Publication number: CN111381803A
Application number: CN201811625330.4A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Cambricon Information Technology Co Ltd
Current assignee: Shanghai Cambricon Information Technology Co Ltd
Priority date: 2018-12-28
Filing date: 2018-12-28
Publication date: 2020-07-07
Also published as: CN117519637A

Abstract

The application provides a data comparator, a data processing method, a chip and an electronic device, wherein the data comparator comprises: the output end of the zero value judging circuit is connected with the input end of the sign bit comparing circuit, the output end of the sign bit comparing circuit is connected with the input end of the data comparing circuit, and the data comparator can reduce the operation amount and save the operation time; in addition, the data comparator can compare and operate floating points, and the universality of the data comparator is improved.

Description

Data comparator, data processing method, chip and electronic equipment

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a data comparator, a data processing method, a chip, and an electronic device.

Background

With the continuous development of digital electronic technology, the rapid development of various Artificial Intelligence (AI) chips has increasingly high requirements for high-performance digital comparators. The neural network algorithm is one of algorithms widely applied to intelligent chips, and a data comparator is required to be used for data size comparison operation for many times.

Generally, a data comparator mainly performs comparison operation on some floating point numbers and fixed point numbers, but cannot perform comparison operation on floating point type data, that is, the data comparator cannot perform comparison operation on other types of data except the floating point numbers and the fixed point numbers, so that the universality of the data comparator is low.

Disclosure of Invention

In view of the above, it is desirable to provide a data comparator, a data processing method, a chip and an electronic device.

An embodiment of the present invention provides a data comparator, where the data comparator includes: the output end of the zero value judging circuit is connected with the input end of the sign bit comparing circuit, and the output end of the sign bit comparing circuit is connected with the input end of the data comparing circuit;

the zero value judging circuit is used for judging whether zero values exist in received first data and second data or not and splitting the first data and the second data to obtain first sign bit data, first exponential bit data and first mantissa bit data in the first data and second sign bit data, second exponential bit data and second mantissa bit data in the second data, the sign bit comparing circuit is used for comparing the sizes of the received first sign bit data and the received second sign bit data, and the data comparing circuit is used for comparing the sizes of the received exponential bit data and/or mantissa bit data.

In one embodiment, the zero value judging circuit includes: a data input port, a sign bit output port, a first mantissa bit output port, a first exponent bit output port, and a zero value judgment result output port;

wherein, the data input port is configured to input first data and second data, the sign bit output port is configured to output the zero value judging circuit, split the first data and the second data to obtain first sign bit data in the first data and second sign bit data in the second data, the first mantissa bit output port is configured to output the zero value judging circuit, split the first data and the second data to obtain first mantissa bit data in the first data and second mantissa bit data in the second data, and the first exponent bit output port is configured to output the zero value judging circuit, split the first data and the second data to obtain first exponent bit data in the first data, and the zero value judgment result output port is used for outputting the judgment result of the zero value judgment circuit.

In one embodiment, the sign bit comparison circuit includes: sign bit input port, first mantissa bit input port, first exponent bit input port, sign bit logic judgment signal output port, second mantissa bit output port, second exponent bit output port, sign bit comparison result output port;

wherein the sign bit input port is configured to receive the first sign bit data and the second sign bit data input by the zero value judging circuit, the first mantissa bit input port is used for receiving the first mantissa data and the second mantissa data input by the zero value judging circuit, the first exponent bit input port is used for receiving the first exponent bit data and the second exponent bit data input by the zero value judging circuit, the sign bit logic determination signal output port is configured to output a logic determination signal, the second mantissa bit output port is configured to output the first mantissa data and the second mantissa data, the second exponent bit output port is configured to output the first exponent data and the second exponent data, the sign bit comparison result output port is configured to output a magnitude comparison result of the first sign bit data and the second sign bit data.

In one embodiment, the data comparison circuit includes: the device comprises a highest nonzero digit comparison module, an exponent digit comparison module and a mantissa digit comparison module, wherein the output end of the highest nonzero digit comparison module is connected with the input end of the exponent digit comparison module, and the output end of the exponent digit comparison module is connected with the input end of the mantissa digit comparison module;

the exponent bit comparison module is configured to compare the first exponent bit data and the second exponent bit data, and the mantissa bit comparison module is configured to compare the first mantissa bit data and the second mantissa bit data.

In one embodiment, the highest non-zero bit compare module comprises: a second mantissa bit input port, a second exponent bit input port, a highest non-zero logic judgment signal output port and a highest non-zero comparison result output port;

the second mantissa bit input port is configured to receive the first mantissa data and the second mantissa data input by the sign bit comparison circuit, the second mantissa bit input port is configured to receive the first exponent data and the second exponent data input by the sign bit comparison circuit, the highest nonzero-bit logic judgment signal output port is configured to output a logic judgment signal, and the highest nonzero-bit comparison result output port is configured to output a comparison result of a highest nonzero bit size in the first mantissa data and the second mantissa data.

In one embodiment, the exponent bit comparison module includes: a third mantissa data input port, a third exponent data input port, a fourth mantissa data output port, an exponent bit logic judgment signal output port and an exponent bit comparison result output port;

the third mantissa data input port is configured to receive the highest nonzero-bit comparison module, the first mantissa data and the second mantissa data, the third exponent data input port is configured to receive the highest nonzero-bit comparison module, the first exponent data and the second mantissa data, the fourth mantissa data output port is configured to output the first mantissa data and the second mantissa data, the exponent data logic judgment signal output port is configured to output a logic judgment signal, and the exponent data comparison result output port is configured to output a size comparison result of the first exponent data and the second mantissa data.

In one embodiment, the mantissa bit comparison module comprises: a fourth mantissa data input port and a mantissa comparison result output port; the fourth mantissa data input port is configured to receive the first mantissa data and the second mantissa data input by the exponent data comparing module, and the mantissa data comparison result output port is configured to output a size comparison result of the first mantissa data and the second mantissa data.

In the data comparator provided by this embodiment, the zero value judging circuit judges whether zero values exist in the received first data and second data, if zero values exist in the received first data and second data, the judging result of the zero value judging circuit is yes, at this time, the operation is finished to obtain an operation result, the operation of the data comparing circuit is not required, the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can also perform comparison operation on the floating point number, so that the universality of the data comparator is improved.

The embodiment of the invention provides a data processing method, which comprises the following steps:

receiving data to be processed;

judging whether a zero value exists in the data to be processed through a zero value judging circuit;

if the data to be processed does not have a zero value, the zero value judgment circuit splits the data to be processed to obtain sign bit data, exponent bit data and mantissa bit data in the data to be processed, and the sign bit comparison circuit compares whether the sign bit data are equal in size or not;

if the sign bit data are equal, the sign bit comparison circuit inputs the exponent bit data and the mantissa bit data into a data comparison circuit, and the data comparison circuit compares the size of the highest nonzero digit in the mantissa bit data, the exponent bit data and/or the mantissa bit data to obtain an operation result.

In one embodiment, after the determining, by the zero value determining circuit, whether a zero value exists in the data to be processed, the method further includes: and if zero exists in the data to be processed, obtaining an operation result and finishing the operation.

In one embodiment, after the comparing, by the sign bit comparing circuit, whether the sign bit data magnitudes are equal, the method further includes: and if the sign bit data are not equal, obtaining an operation result and finishing the operation.

In one embodiment, the sign bit comparison circuit inputs the exponent bit data and the mantissa bit data to a data comparison circuit, and compares the bit of the highest nonzero digit in the mantissa bit data, the exponent bit data and/or the mantissa bit data size by the data comparison circuit to obtain an operation result, including:

judging whether the digit size of the highest nonzero digit is equal in the mantissa digit data through a highest nonzero digit comparison module;

if the digit size of the highest nonzero digit is equal, judging whether the exponent digit data size is equal through an exponent digit comparison module;

if the exponent data are equal in size, judging whether the mantissa data are equal in size through a mantissa data comparison module;

if the mantissa bit data are not equal in size, an operation result is obtained, and the operation is finished.

In one embodiment, after the determining, by the highest nonzero-bit comparison module, whether the bit sizes of the highest nonzero bits in the mantissa data are equal to each other further includes: if the digit sizes of the highest nonzero digit are not equal, obtaining an operation result and finishing the operation.

In one embodiment, after the determining, by the exponent data comparing module, whether the exponent data magnitudes are equal, the method further includes: if the exponent bit data are not equal in size, an operation result is obtained, and the operation is finished.

In one embodiment, after the determining, by the mantissa bit comparing module, whether mantissa data in the to-be-processed data are equal in size, the method further includes: if the mantissa bit data are equal in size, an operation result is obtained, and the operation is finished.

According to the data processing method provided by the embodiment, the received floating point number can be compared and operated, and the universality of the data comparator is effectively improved.

The machine learning arithmetic device provided by the embodiment of the invention comprises one or more data comparators; the machine learning arithmetic device is used for acquiring data to be operated and control information from other processing devices, executing specified machine learning arithmetic and transmitting an execution result to other processing devices through an I/O interface;

when the machine learning arithmetic device comprises a plurality of data comparators, the data comparators can be linked and transmit data through a specific structure;

the data comparators are interconnected through a PCIE bus and transmit data so as to support larger-scale machine learning operation; the data comparators share the same control system or own respective control systems; the data comparators share a memory or own respective memories; the interconnection mode of the data comparators is any interconnection topology.

The combined processing device provided by the embodiment of the invention comprises the machine learning processing device, the universal interconnection interface and other processing devices; the machine learning arithmetic device interacts with the other processing devices to jointly complete the operation designated by the user; the combined processing device may further include a storage device, which is connected to the machine learning arithmetic device and the other processing device, respectively, and is configured to store data of the machine learning arithmetic device and the other processing device.

The neural network chip provided by the embodiment of the invention comprises the data comparator, the machine learning arithmetic device or the combined processing device.

The neural network chip packaging structure provided by the embodiment of the invention comprises the neural network chip.

The board card provided by the embodiment of the invention comprises the neural network chip packaging structure.

The embodiment of the invention provides an electronic device which comprises the neural network chip or the board card.

An embodiment of the present invention provides a chip, including at least one data comparator as described in any one of the above.

The electronic equipment provided by the embodiment of the invention comprises the chip.

Drawings

Fig. 1 is a schematic diagram illustrating an overall structure of a data comparator according to an embodiment;

fig. 2 is a schematic structural diagram of a data comparator according to another embodiment;

FIG. 3 is a schematic diagram of another data comparator according to another embodiment;

fig. 4 is a schematic structural diagram of a data comparator according to another embodiment;

fig. 5 is a schematic diagram of another specific structure of a data comparator according to another embodiment;

FIG. 6 is a flowchart illustrating a data processing method according to an embodiment;

FIG. 7 is a flowchart illustrating another data processing method according to another embodiment;

FIG. 8 is a block diagram of a combined processing device according to an embodiment;

FIG. 9 is a block diagram of another integrated processing device according to an embodiment;

fig. 10 is a schematic structural diagram of a board card according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The data comparator provided by the application can be applied to an AI chip, a Field Programmable Gate Array (FPGA) chip, or other hardware circuit devices for multiplication processing, and a specific structural schematic diagram of the data comparator is shown in fig. 1.

Fig. 2 is a schematic structural diagram of a data comparator according to an embodiment. As shown in fig. 2, the data comparator includes: the circuit comprises a data splitting circuit 11, a highest nonzero digit comparison circuit 12 and a data comparison circuit 13, wherein the output end of the data splitting circuit 11 is connected with the input end of the highest nonzero digit comparison circuit 12, and the output end of the highest nonzero digit comparison circuit 12 is connected with the input end of the data comparison circuit 13;

the data splitting circuit 11 is configured to split received first data and second data to obtain first mantissa data and first exponent data in the first data, and second mantissa data and second exponent data in the second data, the highest nonzero-bit comparing circuit 12 is configured to compare sizes of highest nonzero bits in the received first mantissa data and second mantissa data, and the data comparing circuit 13 is configured to compare sizes of received exponent data and/or mantissa data.

Specifically, the data splitting circuit 11, the highest nonzero digit comparing circuit 12 and the data comparing circuit 13 may process data in a serial manner, or may process data in a parallel manner through or logic implementation. Optionally, the data splitting circuit 11 may split the two received data to obtain two parts, namely mantissa bit data and exponent bit data. Optionally, when the data comparator compares data, the data splitting circuit 11 may input both the two split mantissa data into the highest nonzero-bit comparing circuit 12, and may compare the highest nonzero-bit data of the two mantissa data with the two exponent data by the highest nonzero-bit comparing circuit 12, and further, the data splitting circuit 11 may input both the two split mantissa data and the two exponent data into the data comparing circuit 13, and compare the two mantissa data and/or the two exponent data by the data comparing circuit 13.

It should be noted that, the first data and the second data may be unsigned floating point numbers with multiple bit widths, and the bit widths of the first data and the second data may be the same. Optionally, if the bit width of the unsigned floating point number is n bits, the exponent number of the unsigned floating point number may be greater than or equal to 1, and when the exponent number is equal to m, the mantissa number of the unsigned floating point number may be equal to n-m. For example, if the unsigned floating point number is 8 bits wide, the most significant bit value may be an exponent bit value and the lower 7 bit value may be a mantissa bit value. Alternatively, the data comparison circuit 13 may be a circuit that compares exponent data and mantissa data in the received floating point number. Alternatively, the data comparison circuit 13 may include a plurality of comparison modules having different functions. Optionally, there may be a plurality of input ports of the comparison circuits with different functions, each input port of each comparison circuit may have different or the same function, and there may also be a plurality of output ports, and each output port of each comparison circuit may have the same or different function, but the input ports of different comparison circuits may have the same or different functions, and the output ports of different comparison circuits may have the same or different functions, and the circuit structures of the comparison circuits with different functions may be different or the same.

In addition, the most significant non-zero bits of the mantissa data may be represented as significant bits of the mantissa data of the first data and the second data, and a specific position corresponding to a first non-zero bit value from a lowest bit value to a highest bit value, wherein the bit corresponding to the lowest bit value may be represented as 0, the bit corresponding to a next lowest bit value may be represented as 1, and the significant bits may represent the significant bits of the mantissa data starting from the highest bit value to the first non-zero bit value of the lowest bit value until the lowest bit values are all significant bits. For example, if the mantissa bit data a of the unsigned floating point number is "00101", the valid bit data in the mantissa bit data is "101", the lowest bit value "1" in the valid bit data may be referred to as the 0 th bit value, and the next lowest bit value "0" may be referred to as the 1 st bit value, the highest non-zero bit value in the mantissa bit data may be equal to 2, if the mantissa bit data b of the unsigned floating point number is "01110", the valid bit data in the mantissa bit data is "1110", the lowest bit value "0" in the valid bit data may be referred to as the 0 th bit value, and the next lowest bit value "1" may be referred to as the 1 st bit value, the highest non-zero bit value in the mantissa bit data may be equal to 3, at this time, the number of unsigned floating points with the highest non-zero bit in the mantissa data being larger is larger, that is, the number of unsigned floating points with the highest non-zero bit being lower is smaller, that is, a is smaller than b.

In the data comparator provided by this embodiment, the data splitting circuit is configured to split the received first data and the second data to obtain first mantissa data, second mantissa data, first exponent data, and second exponent data, input the first mantissa data and the second mantissa data to the mantissa data highest nonzero digit comparing circuit, perform a comparison operation on the digits of the highest nonzero digit in the mantissa data to obtain a comparison result, and determine whether the received data needs to pass through the next data comparing circuit according to the comparison result to perform the comparison operation on the two mantissa data and/or the two exponent data, if the next data comparing circuit does not need to perform the processing, end the operation to obtain the operation result, otherwise, the data splitting circuit continues to perform the obtained two mantissa data and the two exponent data, the input is to the data comparison circuit, when the data comparison circuit outputs a high level signal, the operation is finished to obtain an operation result, the operation amount can be reduced in the process, and the operation time is saved; in addition, the data comparator can compare and operate floating points, and the universality of the data comparator is improved.

Fig. 3 is a block diagram of a data comparator according to another embodiment. As shown in fig. 3, the data comparator includes: a zero value judging circuit 21, a sign bit comparing circuit 22 and a data comparing circuit 23, wherein the output end of the zero value judging circuit 21 is connected with the input end of the sign bit comparing circuit 22, and the output end of the sign bit comparing circuit 22 is connected with the input end of the data comparing circuit 23;

the zero value judging circuit 21 is configured to judge whether a zero value exists in the received first data and second data, and split the first data and the second data to obtain first sign bit data, first exponent bit data and first mantissa bit data in the first data, and second sign bit data, second exponent bit data and second mantissa bit data in the second data, the sign bit comparing circuit 22 is configured to compare sizes of the received first sign bit data and the received second sign bit data, and the data comparing circuit 23 is configured to compare the received exponent bit data and/or mantissa bit data.

Specifically, the zero value judgment circuit 21, the sign bit comparison circuit 22, and the data comparison circuit 23 may process data in a serial manner, or may process data in a parallel manner through logical or. Optionally, the first data and the second data may be signed floating point numbers with multiple bit widths, and the bit widths of the first data and the second data are equal. Alternatively, the data comparison circuit 23 may be a circuit for comparing sizes of digits, exponent digit data and/or mantissa digit data of the first data and the second data, which are highest non-zero digits in mantissa digit data. Alternatively, the data comparison circuit 23 may include a plurality of data comparison circuits having different functions. Optionally, there may be a plurality of input ports of the data comparing circuits with different functions, each input port of each data comparing circuit may have different or the same function, and there may also be a plurality of output ports, and each output port of each data comparing circuit may have the same or different function.

It should be noted that, if the judgment result of the zero-value judgment circuit 21 is yes, the zero-value judgment circuit 21 may output a high-level signal, and at this time, the operation is ended and the operation result is output; if the first data and the second data received by the zero-value judging circuit 21 do not satisfy the preset condition, the zero-value judging circuit 21 may output a low-level signal, and at this time, the data comparator does not end the operation, and needs to continue to compare the first data and the second data by the next circuit. Optionally, the satisfied preset condition may be characterized as a coding format corresponding to a zero value in the received floating point number, where the coding format corresponding to the zero value may be represented as that exponent bit data and mantissa bit data in signed data are all 0. In addition, if the judgment result of the zero value judgment circuit 21 is negative, the data comparator may compare the magnitude of the first sign bit data and the magnitude of the second sign bit data through the sign bit comparison circuit 22, if the magnitude of the sign bit data in the first data and the magnitude of the second sign bit data are equal, the data comparator may continue to compare the first data and the second data through the next comparison circuit, otherwise, the data comparator may obtain an operation result, and the operation is ended.

In one embodiment, the data splitting circuit 11 includes a data input port 111, a first mantissa data output port 112, and a first exponent data output port 113; the data input port 111 is configured to input the first data and the second data, the first mantissa data output port 112 is configured to output first mantissa data and second mantissa data obtained by splitting the first data and the second data, and the first exponent data output port 113 is configured to output first exponent data and second exponent data obtained by splitting the first data and the second data.

Specifically, the data splitting circuit 11 may receive two unsigned floating point numbers to be compared through the data input port 111, split the two unsigned floating point numbers to obtain mantissa data and exponent data in the two unsigned floating point numbers, respectively, and input the obtained two mantissa data into the highest nonzero-bit comparison circuit 12 through the first mantissa data output port 112, and input the obtained two exponent data into the highest nonzero-bit comparison circuit 12 through the first exponent data output port 113. It can also be understood that, after the data splitting circuit 11 splits the two received data to be compared, the two mantissa bit data and the two exponent bit data obtained after splitting may be simultaneously input to the highest nonzero-bit comparing circuit 12.

In the data comparator provided by this embodiment, the data splitting circuit may split the received first data and second data to obtain mantissa data and exponent data of the two data, further perform a comparison operation on the highest nonzero digit of the two mantissa data by using the highest nonzero digit comparison circuit to obtain a comparison result, and determine whether the received data needs to pass through the next data comparison circuit to perform the comparison operation on the two mantissa data and/or the two exponent data according to the comparison result, if the next data comparison circuit does not need to perform the processing, the operation is ended to obtain the operation result, otherwise, the data splitting circuit may continue to input the obtained two mantissa data and the obtained two exponent data into the data comparison circuit, when the data comparison circuit outputs a high level signal, the operation is finished to obtain an operation result, the operation amount can be reduced in the process, and the operation time is saved; in addition, the data comparator can compare and operate floating points, and the universality of the data comparator is improved.

In one embodiment, the highest non-zero bit compare circuit 12 comprises: a first mantissa data input port 121, a first exponent data input port 122, a second mantissa data output port 123, a second mantissa data output port 124, a highest non-zero bit logic determination signal output port 125, a highest non-zero bit comparison result output port (agtb1)126, and (altb1) 127;

wherein the first mantissa data input port 121 is configured to receive the first mantissa data and the second mantissa data input by the data splitting circuit 11, the first exponent data input port 122 is configured to receive the first exponent data and the second exponent data input by the data splitting circuit 11, the second mantissa data output port 123 is configured to output the first mantissa data and the second mantissa data, the second exponent data output port 124 is configured to output the first exponent data and the second exponent data, the highest non-zero logic determination signal output port 125 is configured to output a logic determination signal, and the highest non-zero comparison result output ports (agtb1) and (altb1)127 are respectively configured to output the first mantissa data and the second mantissa data, the comparison of the bit sizes of the highest non-zero bits.

Specifically, the highest nonzero-bit comparison circuit 12 may compare the received first mantissa data and second mantissa data with the highest nonzero-bit size, and if the highest nonzero-bit comparison result output port (agtb1)126 or (altb1)127 outputs a high level signal, the operation is ended to obtain an operation result, at this time, the highest nonzero-bit logic determination signal output port 125 may output a low level signal, and the characterization data comparator does not need to compare two exponent data and two mantissa data through the exponent data comparison module 131 and the mantissa data comparison module 132. If the highest nonzero bit comparison result output port (agtb1)126 or (altb1)127 outputs a low level signal, the data comparator needs to continue to compare two exponent bit data and/or two mantissa bit data through the exponent bit comparison module 131 and/or the mantissa bit comparison module 132, at this time, the highest nonzero bit logic judgment signal output port 125 can output a high level signal, and the characterization data comparator needs to continue to compare two exponent bit data and/or two mantissa bit data through the data comparison circuit 13.

Optionally, if the signed floating point number is a positive number, the larger the highest nonzero digit (i.e., the lower the highest nonzero digit position) in mantissa digit data of the floating point number is, the smaller the corresponding signed floating point number is; if the signed floating point number is a negative number, the larger the number of the highest nonzero digit (i.e. the higher the position of the highest nonzero digit), the smaller the corresponding signed floating point number in the mantissa digit data of the floating point number.

For example, for a positive floating point number, if mantissa bit data a of the floating point number is "00101", valid bit data in the mantissa bit data is "101", a lowest order bit value "1" in the valid bit data may be referred to as a 0 th order bit value, and a next lowest order bit value "0" may be referred to as a 1 st order bit value, the number of highest non-zero bits in the valid bit data may be equal to 2, if mantissa bit data b of the floating point number is "01110", valid bit data in the mantissa bit data is "1110", a lowest order bit value "0" in the valid bit data may be referred to as a 0 th order bit value, and a next lowest order bit value "1" may be referred to as a 1 st order bit value, the number of highest non-zero bits in the mantissa bit data may be equal to 3, at this time, the floating point number with the highest nonzero digit in the mantissa data is larger, that is, the floating point number with the highest nonzero digit in the mantissa data is lower, that is, a is smaller than b.

For negative floating point number, if mantissa digit data a of the floating point number is "00101", valid digit data in the mantissa digit data is "101", a highest digit value "1" in the valid digit data may be referred to as a 0 th digit value, and a next highest digit value "0" may be referred to as a 1 st digit value, the highest non-zero digit value in the valid digit data may be equal to 2, if mantissa digit data b of the floating point number is "01110", valid digit data in the mantissa digit data is "1110", the highest digit value "1" in the valid digit data may be referred to as a 0 th digit value, and the next highest digit value "1" may be referred to as a 1 st digit value, the highest non-zero digit value in the valid digit data may be equal to 1, at this time, the highest non-zero digit value in the mantissa digit data is smaller than the floating point number, that is, the number of floating-point bits higher in the highest non-zero bit position in the mantissa data is smaller, i.e., a is greater than b.

In the data comparator provided by this embodiment, the highest nonzero-position comparison circuit can compare the magnitude of the highest nonzero position in mantissa data of the first data and the second data, and output a comparison result, thereby ending the operation to obtain an operation result, and the process can reduce the operation amount and save the operation time; in addition, the data comparator can also perform comparison operation on the floating point number, so that the universality of the data comparator is improved.

Fig. 4 is a schematic diagram of a specific structure of a data comparator according to another embodiment, the data comparator includes a data comparison circuit 13, the data comparison circuit 13 includes a exponent bit comparison module 131 and a mantissa bit comparison module 132, and an output terminal of the exponent bit comparison module 131 is connected to an input terminal of the mantissa bit comparison module 132. The exponent bit comparing module 131 is configured to compare the received first exponent data and the received second exponent data, and the mantissa bit comparing module 132 is configured to compare the received first mantissa data and the received second mantissa data.

It should be noted that, if the data comparator needs to compare the received first data and second data through the data comparing circuit 13, the exponent data comparing module 131 and the mantissa data comparing module 132 sequentially process the mantissa data and the exponent data in the received first data and second data until one comparing module can obtain a comparing result, and the corresponding comparing module outputs a high level signal, at this time, the operation is ended and the operation result is output. Optionally, the comparison result may include an exponent data size comparison result and/or a mantissa data size comparison result in the first data and the second data.

According to the data comparator provided by the embodiment, through the exponent bit comparison module and the mantissa bit comparison module, the size of the exponent bit data and/or the size of the mantissa bit data in the received first data and second data are sequentially judged, if the size of the exponent bit data and/or the size of the mantissa bit in the received first data and second data can be determined, the corresponding comparison module can output a high-level signal, and further an operation result is obtained, the data comparator can perform comparison operation on floating point numbers, and the universality of the data comparator is improved.

In one embodiment, the exponent bit comparison module 131 includes: a second mantissa data input port 1311, a second exponent data input port 1312, a third mantissa data output port 1313, an exponent bit logic determination signal output port 1314, exponent bit comparison result output ports (agtb2)1315, and (altb2) 1316; the second mantissa data input port 1311 is configured to receive the highest nonzero bit comparison circuit 12, the first mantissa data and the second mantissa data that are input, the second exponent data input port 1312 is configured to receive the highest nonzero bit comparison circuit 12, the first exponent data and the second mantissa data that are input, the third mantissa data output port 1313 is configured to output the first mantissa data and the second mantissa data, the exponent logic determination signal output port 1314 is configured to output a logic determination signal, and the exponent data comparison result output ports (agtb2)1315 and (altb2)1316 are configured to output size comparison results of the first exponent data and the second exponent data, respectively.

Specifically, the exponent bit comparing module 131 may compare two received exponent bit data, and if the exponent bit comparison result output port (agtb2)1315 or (altb2)1316 outputs a high level signal, the operation is ended to obtain an operation result, at this time, the exponent bit logic determination signal output port 1314 may output a low level signal, and the token data comparator does not need to compare two mantissa bit data through the mantissa bit comparing module 132. If the exponent bit comparison result output port (agtb2)1315 or (altb2)1316 outputs a low level signal, the data comparator needs to continue to compare two mantissa bit data through the mantissa bit comparison module 132, at this time, the exponent bit logic determination signal output port 1314 can output a high level signal, and the token data comparator needs to compare two mantissa bit data through the mantissa bit comparison module 132.

In the data comparator provided by this embodiment, the exponent bit comparison module can compare the magnitude of the exponent bit data in the first data and the second data, and output a comparison result, thereby ending the operation to obtain an operation result, which can reduce the operation amount and save the operation time; in addition, the data comparator can also perform comparison operation on the floating point number, so that the universality of the data comparator is improved.

In one embodiment, the mantissa bit comparison module 132 comprises: a third mantissa data input port 1321, a mantissa bit comparison result output port (agtb3)1322, (altb3)1323, and (aeqb3) 1324; the third mantissa data input port 1321 is configured to receive the first mantissa data and the second mantissa data input by the exponent bit comparison module 131, and the mantissa data comparison result output port (agtb3)1322, (altb3)1323 and (aeqb3)1324 are configured to output a size comparison result of the first mantissa data and the second mantissa data, respectively.

Specifically, the mantissa bit comparing module 132 may compare two received mantissa bit data, and if the mantissa bit comparison result output port (agtb3)1322, (altb3)1323 or (aeqb3)1324 outputs a high level signal, the operation is ended to obtain the operation result.

In the data comparator provided by this embodiment, the mantissa bit comparing circuit can compare the magnitude of mantissa data in the first data and the second data, and output the comparison result, thereby ending the operation to obtain the operation result, which can reduce the operation amount and save the operation time; in addition, the data comparator can also perform comparison operation on the floating point number, so that the universality of the data comparator is improved.

In one embodiment, the zero value determining circuit 21 includes: a data input port 211, a sign bit output port 212, a first mantissa bit output port 213, a first exponent bit output port 214, a zero value determination result output port (agtb1)215, (aeqb1)216, and (altb1) 217. Wherein, the data input port 211 is configured to input first data and second data, the sign bit output port 212 is configured to output the zero value judging circuit 21, and split the first data and the second data to obtain first sign bit data in the first data and second sign bit data in the second data, the first mantissa bit output port 213 is configured to output the zero value judging circuit 21, and split the first data and the second data to obtain first mantissa bit data in the first data and second mantissa bit data in the second data, the first exponent bit output port 214 is configured to output the zero value judging circuit 21, and split the first data and the second data to obtain first exponent bit data in the first data, and second digital data in the second data, the zero-value judgment result output port (agtb1)215, (aeqb1)216, and (altb1)217 for outputting the judgment result of the zero-value judgment circuit 21, respectively.

Specifically, the determination results output by the three zero-value determination result output ports (agtb1)215, (aeqb1)216, and (altb1)217 may be logic signals, which may be high-level signals or low-level signals. If both the two data received by the zero-value judging circuit 21 satisfy the preset condition, the zero-value judging result output port (aeqb1)216 may output a high-level signal, and the other two ports may output low-level signals, at this time, the operation is ended and the operation result is output. Optionally, if the zero-value determination result output port (agtb1)215 or (altb1)217 outputs a high-level signal, it indicates that there is a zero value in the two data received by the zero-value determination circuit 21, and at this time, the size of the two data may be determined directly according to the zero-value determination circuit 21. Optionally, when the three zero-value determination result output ports all output low-level signals, it may be indicated that zero values do not exist in the two data received by the zero-value determination circuit 21, and the operation cannot be ended, and the data still needs to be compared by the next comparison circuit. Optionally, the preset condition corresponding to the zero value judgment circuit 21 may be whether the number of the received floating points satisfies the coding format corresponding to the zero value.

It should be noted that, the first data and the second data may be signed floating point numbers, and bit widths of the first data and the second data may be equal. Optionally, the zero value determining circuit 21 may determine whether the exponent data and the mantissa data in the two received data are both in a coding format corresponding to a zero value. For example, if one of the two data received by the zero value judging circuit 21 is a positive zero and one is a negative zero, the zero value judging result output port (aeqb1)216 in the zero value judging circuit 21 may output a high level signal, which indicates that the two data compared by the data comparator are equal, i.e., the positive zero is equal to the negative zero, and at this time, the maximum value Zmax and the minimum value Zmin output by the data comparator are equal and both are zero values. In addition, if one of the first data and the second data is a zero value and the other is a non-zero value, the data comparator may directly determine the size of the data through the zero value determining circuit 21, and end the operation without continuing to perform the comparison operation on the data through other comparing circuits.

According to the data comparator provided by the embodiment, the zero value judgment circuit can determine whether the data comparator can directly finish the operation to obtain the operation result according to the judgment result output by the zero value judgment result, and at the moment, the data comparator does not need to perform subsequent operation of other comparison circuits, so that the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can also perform comparison operation on the floating point number, so that the universality of the data comparator is improved.

As one embodiment, the sign bit comparison circuit 22 includes: a sign bit input port 221, a first mantissa bit input port 222, a first exponent bit input port 223, a sign bit logic determination signal output port 224, a second mantissa bit output port 225, a second mantissa bit output port 226, a sign bit comparison result output port (agtb2)227, and (altb2)228, wherein the sign bit input port 221 is used for receiving the first sign bit data and the second sign bit data input by the zero value determination circuit 21, the first mantissa bit input port 222 is used for receiving the first mantissa bit data and the second mantissa bit data input by the zero value determination circuit 21, the first exponent bit input port 223 is used for receiving the first exponent bit data and the second exponent bit data input by the zero value determination circuit 21, and the sign bit logic determination signal output port 224 is used for outputting a logic determination signal, the second mantissa bit output port 225 is configured to output the first mantissa bit data and the second mantissa bit data, the second exponent bit output port 226 is configured to output the first exponent bit data and the second exponent bit data, and the sign bit comparison result output ports (agtb2)227 and (altb2)228 are configured to output magnitude comparison results of the first sign bit data and the second sign bit data, respectively.

When the sign bit comparison result output port (agtb2)227 or (altb2)228 outputs a high level signal, the operation is ended to obtain an operation result. Illustratively, if the two signed float points received by the data comparator are a and b, respectively, the output of the agtb2 is a high level signal, which can be characterized, the signed float point a is a negative number, the signed float point b is a positive number, and it is stated that a is smaller than b; if the altb2 outputs a high level signal, it can be characterized that the floating point with sign a is positive number, the floating point with sign b is negative number, and a is larger than b. In addition, if all the sign bit comparison result output ports do not output high level signals, the sign bit comparison circuit 22 needs to input the received two mantissa bit data and two exponent bit data to the next comparison circuit for further comparison.

In addition, the data comparator may determine the maximum value Zmax and the minimum value Zmin of the output according to the high level signal output from the sign bit comparison result output port (agtb2)227 or (altb2) 228.

According to the data comparator provided by the embodiment, the magnitude of the sign bit number in the two received data is compared through the sign bit comparison circuit, if a high level signal is output in the comparison result, the comparison operation is ended to obtain the operation result, so that the operation amount can be reduced, and the operation time is saved; in addition, the data comparator can also perform comparison operation on the floating point number, so that the universality of the data comparator is improved.

Fig. 5 is a schematic diagram of a specific structure of another data comparator according to another embodiment, where the data comparator includes a data comparing circuit 23, and the data comparing circuit 23 includes: a highest non-zero bit comparison module 231, an exponent bit comparison module 232, and a mantissa bit comparison module 233, wherein an output of the highest non-zero bit comparison module 231 is connected to an input of the exponent bit comparison module 232, and an output of the exponent bit comparison module 232 is connected to an input of the mantissa bit comparison module 233. The highest nonzero-bit comparing module 231 is configured to compare the bit size of the highest nonzero bit in the received first mantissa data and second mantissa data, the exponent bit comparing module 232 is configured to compare the first exponent data and the second exponent data, and the mantissa bit comparing module 233 is configured to compare the first mantissa data and the second mantissa data.

Specifically, the highest nonzero digit comparison module 231, the exponent digit comparison module 232 and the mantissa digit comparison module 233 may process data in a serial manner, or may process data in a parallel manner through logical or.

In the data comparator provided by this embodiment, the sign bit comparison circuit inputs the received two mantissa data to the highest nonzero-bit comparison module, and compares the highest nonzero-bit data of the two mantissa data by the highest nonzero-bit comparison module to obtain a comparison result, and according to the comparison result, determines whether the received two mantissa data and/or exponent data of the two data need to be compared by the next comparison module, if the next comparison module does not need to process, the operation is ended to obtain an operation result, otherwise, the sign bit comparison circuit continues to input the two mantissa data and/or the two exponent data to the comparison module, and when the comparison module outputs a high level signal, the operation is ended to obtain an operation result, which can reduce the operation amount, the operation time is saved; in addition, the data comparator can compare and operate floating points, and the universality of the data comparator is improved.

In one embodiment, the highest non-zero bit comparison module 231 comprises: a second mantissa bit input port 2311, a second mantissa bit input port 2312, a highest non-zero logic determination signal output port 2313, a highest non-zero comparison result output port (agtb3)2314 and (altb3)2315, wherein the second mantissa bit input port 2311 is used for receiving the first mantissa data and the second mantissa data input by the sign bit comparison circuit 22, the second exponent bit input port 2312 is configured to receive the first exponent bit data and the second exponent bit data input by the sign bit comparing circuit 22, the highest non-zero logic determination signal output port 2313 is used for outputting a logic determination signal, the highest non-zero bit comparison result output ports (agtb3)2314 and (altb3)2315 are respectively used for outputting comparison results of the bit size of the highest non-zero bit in the first mantissa data and the second mantissa data.

If the highest non-zero bit comparison result output port (agtb3)2314 or (altb3)2315 outputs a high level signal, the operation is ended to obtain the operation result. For example, if two unsigned floating point numbers received by the data comparator are a and b, respectively, the output of the agtb3 is a high-level signal, which can represent that the bit of the highest non-zero bit in the mantissa data of the unsigned floating point number a is greater than the bit of the highest non-zero bit in the mantissa data of the unsigned floating point number b, and indicates that a is less than b; if the altb1 outputs a high level signal, it can be shown that the highest non-zero bit in the mantissa data of the unsigned floating point number a is less than the highest non-zero bit in the mantissa data of the unsigned floating point number b, and it is indicated that a is greater than b. Alternatively, the data comparator may determine the maximum value Zmax and the minimum value Zmin of the output according to the high level signal output from the highest non-zero bit comparison result output port (agtb3)2314 or (altb3) 2315. In addition, if all the output ports of the highest nonzero-position comparison result have no high-level signal output, the highest nonzero-position comparison module 231 is represented, and two received exponent bit data and two received mantissa bit data need to be input to the next data comparison circuit for comparison.

In the data comparator provided by this embodiment, the highest nonzero-position comparison module can output the comparison result according to the output port of the highest nonzero-position comparison result in the two pieces of mantissa data, so as to end the operation to obtain the operation result, and the operation amount can be reduced and the operation time can be saved in the process; in addition, the data comparator can also perform comparison operation on the floating point number, so that the universality of the data comparator is improved.

In one embodiment, the exponent bit comparison module 232 includes: a third mantissa data input port 2321, a third exponent data input port 2322, a fourth mantissa data output port 2323, an exponent bit logic determination signal output port 2324, exponent bit comparison result output ports (agtb4)2325 and (altb4) 2326; the third mantissa data input port 2321 is configured to receive the highest nonzero-bit comparison module 231, the input first mantissa data and the input second mantissa data, the third exponent data input port 2322 is configured to receive the highest nonzero-bit comparison module 231, the input first exponent data and the input second mantissa data, the fourth mantissa data output port 2323 is configured to output the first mantissa data and the second mantissa data, the exponent logic determination signal output port 2324 is configured to output a logic determination signal, and the exponent data comparison result output ports (agtb4)2325 and (altb4)2326 are configured to output size comparison results of the first exponent data and the second mantissa data, respectively.

Specifically, the exponent bit comparing module 232 may compare two received exponent bit data, and if the exponent bit comparison result output port (agtb4)2325 or (altb4)2326 outputs a high level signal, the operation is ended to obtain an operation result, at this time, the exponent bit logic determination signal output port 2324 may output a low level signal, and the token data comparator does not need to compare two mantissa bit data through the mantissa bit comparing module 233. If the exponent bit comparison result output port (agtb4)2325 or (altb4)2326 outputs a low level signal, the data comparator needs to continue to compare two mantissa bit data through the mantissa bit comparison module 233, at this time, the exponent bit logic determination signal output port 2324 can output a high level signal, and the token data comparator needs to compare two mantissa bit data through the mantissa bit comparison module 233.

As one embodiment, the mantissa bit comparison module 233 includes: a fourth mantissa data input port 2331, a mantissa bit comparison result output port (agtb5)2332, (altb5)2333, and (aeqb5) 2334; the fourth mantissa data input port 2331 is configured to receive the exponent data comparing module 232, the first mantissa data and the second mantissa data input thereto, and the mantissa data comparison result output ports (agtb5)2332, (altb5)2333 and (aeqb5)2334 are configured to output the magnitude comparison results of the first mantissa data and the second mantissa data, respectively.

Specifically, the mantissa bit comparison module 233 may compare two received mantissa bit data, and if the mantissa bit comparison result output port (agtb5)2332, (altb5)2333 or (aeqb5)2334 outputs a high level signal, the operation is ended to obtain the operation result.

In the data comparator provided by this embodiment, the mantissa digit comparison module may compare mantissa digit data of the first data and the second data, and output a comparison result, thereby ending the operation to obtain an operation result, which may reduce the operation amount and save the operation time; in addition, the data comparator can also perform comparison operation on the floating point number, so that the universality of the data comparator is improved.

Fig. 6 is a flowchart illustrating a data processing method according to an embodiment, which may be processed by the data comparator shown in fig. 2 and fig. 4, where the embodiment relates to a process of comparing data. As shown in fig. 6, the method includes:

s101, receiving data to be processed.

Specifically, the data comparator may receive two data to be processed. Optionally, the data comparator inputs the received data to be processed to the highest nonzero-position comparison circuit, and if the data to be processed needs to be processed by the data comparison circuit after the operation of the highest nonzero-position comparison circuit is finished, the highest nonzero-position comparison circuit inputs the received data to be processed to the data comparison circuit for comparison operation of the data to be processed. Optionally, the data to be processed may be unsigned floating point numbers with multiple bit widths, and the bit widths of the two data to be processed are equal.

S102, splitting the data to be processed to obtain exponent data and mantissa data in the data to be processed.

Specifically, the data comparator may perform data splitting processing on two data to be processed through the data splitting circuit to obtain exponent bit data and mantissa bit data in the two data to be processed, and input both the exponent bit data and the mantissa bit data to the highest nonzero digit comparing circuit for subsequent comparison processing. Optionally, if the bit width of the unsigned floating point number is n bits, the total number of digits of the digital data in the unsigned floating point number may be greater than or equal to 1, and when the total number of digits of the exponent data is equal to m, the total number of digits of the mantissa data of the unsigned floating point number may be equal to n-m. For example, if the unsigned floating point number is 8 bits wide, the most significant bit value may be an exponent bit value and the lower 7 bit value may be a mantissa bit value.

S103, comparing the highest nonzero digit in the mantissa digit data through a highest nonzero digit comparison circuit to obtain a comparison result.

Specifically, the comparison result may be obtained by comparing the highest non-zero digit in the mantissa digit data of the data to be processed. Optionally, the comparison result may be a logic determination signal, and the logic determination signal may be a high level signal 1 or a low level signal 0. Optionally, the highest nonzero digit of the mantissa digit data may be represented as valid digit data in the mantissa digit data of the first data and the second data, and a specific position corresponding to a first nonzero digit value from a lowest digit value to a highest digit value, wherein the digit corresponding to the lowest digit value may be represented as 0, the digit corresponding to a next lowest digit value may be represented as 1, and the valid digit data may represent the first nonzero digit value from the highest digit value to the lowest digit value in the mantissa digit data until the lowest digit value is the valid digit data.

For example, if the mantissa bit data a of the unsigned floating point number is "00101", the valid bit data in the mantissa bit data is "101", the lowest bit value "1" in the valid bit data may be referred to as the 0 th bit value, and the next lowest bit value "0" may be referred to as the 1 st bit value, the highest non-zero bit value in the mantissa bit data may be equal to 2, if the mantissa bit data b of the unsigned floating point number is "01110", the valid bit data in the mantissa bit data is "1110", the lowest bit value "0" in the valid bit data may be referred to as the 0 th bit value, and the next lowest bit value "1" may be referred to as the 1 st bit value, the highest non-zero bit value in the mantissa bit data may be equal to 3, at this time, the number of unsigned floating points with the highest non-zero bit in the mantissa data being larger is larger, that is, the number of unsigned floating points with the highest non-zero bit being lower is smaller, that is, a is smaller than b.

And S104, judging whether the exponent data and/or the mantissa data need to be compared through a data comparison circuit according to the comparison result.

Optionally, the determining, in S104, whether the exponent data and/or the mantissa data need to be compared by a data comparison circuit according to the comparison result includes: if the comparison result is a high level signal, judging that the exponent data and/or the mantissa data do not need to be compared by the data comparison circuit; and if the comparison result is a low-level signal, judging that the exponent bit data and/or the mantissa bit data need to be compared by the data comparison circuit.

Optionally, after the step of determining whether the exponent data and/or the mantissa data need to be compared by a data comparison circuit according to the comparison result in S104, the method further includes: if the comparison processing by the data comparison circuit is not required, the operation result is obtained.

Specifically, the data comparator may determine whether two exponent bit data and/or two mantissa bit data need to be continuously compared by the data comparison circuit according to a comparison result output by the highest nonzero-bit comparison circuit, so as to obtain an operation result. Optionally, if the comparison result is a high-level signal, the data comparator may not need to compare the two exponent data and/or the two mantissa data obtained after the splitting, otherwise, the data comparator may also need to compare the two exponent data and/or the two mantissa data.

And S105, if necessary, inputting the exponent bit data and the mantissa bit data into the data comparison circuit by the highest nonzero digit comparison circuit, and comparing the exponent bit data and/or the mantissa bit data by the data comparison circuit to obtain an operation result.

Specifically, if the comparison result output by the highest nonzero-position comparison circuit is a low-level signal, the highest nonzero-position comparison circuit can input two pieces of mantissa data and two pieces of exponent data to the data comparison circuit, compare the two pieces of mantissa data and/or the two pieces of exponent data through the data comparison circuit, and obtain an operation result according to the comparison result.

In the data processing method provided by this embodiment, the data comparator may split the received two pieces of data to be processed to obtain mantissa data and exponent data in the two pieces of data to be processed, compare the highest nonzero digit of the mantissa data to obtain a comparison result, determine whether to compare the size of the two pieces of exponent data and/or the size of the two pieces of mantissa data obtained after splitting according to the comparison result, and if not, end the operation processing to obtain an operation result, thereby reducing the amount of operation and saving the operation time; in addition, the method can also carry out comparison operation on the received floating point number, and effectively improves the universality of the data comparator.

In one embodiment, in S105, the inputting, by the highest nonzero-bit comparing circuit, the exponent data and the mantissa data to the data comparing circuit, and comparing, by the data comparing circuit, the exponent data and/or the mantissa data to obtain an operation result includes:

s1051, comparing whether the exponent bit data are equal through an exponent bit comparison module.

Specifically, the exponent bit comparison module may receive two exponent bit data input by the highest nonzero digit comparison circuit, compare the exponent bit data, and determine whether the two exponent bit data are equal.

Optionally, after the step of comparing, by the comparing module, whether the exponent bit data are equal in S1051, the method further includes: if the exponent bit data are not equal, obtaining an operation result and ending the operation.

It should be noted that, when the two exponent bit data received by the exponent bit comparing module are not equal, the larger the exponent bit data is, the larger the data to be processed is, and the smaller the exponent bit data is, the smaller the data to be processed is.

And S1052, if the exponent bit data are equal, comparing whether the mantissa bit data are equal through the mantissa bit comparison module.

Specifically, if the two exponent bit data are equal, the exponent bit comparison module may input the two mantissa bit data to the mantissa bit comparison module, and compare the two mantissa bit data through the mantissa bit comparison module to determine whether the mantissa bit data in the two data to be processed are equal.

Optionally, after the step of comparing whether the mantissa data are equal by the mantissa data comparing module in the step S1052, the method further includes: if the mantissa bit data are not equal, obtaining an operation result and ending the operation.

S1053, if the mantissa bit data are equal, obtaining the operation result and ending the operation.

Specifically, if the mantissa bit data in the two pieces of data to be processed are equal, the mantissa bit comparison module may output the mantissa bit comparison operation result through the mantissa bit comparison result output port, and output the maximum value and the minimum value in the received two pieces of data to be processed through the maximum value output port (Zmax) and the minimum value output port (Zmin) of the data comparator, and end the comparison operation, where the maximum value may be equal to the minimum value. Wherein the mantissa bit comparison result may be a high level signal.

In the data processing method provided by this embodiment, the exponent data are compared by the exponent data comparison module to determine whether the exponent data are equal, if the exponent data are equal, the mantissa data are compared by the mantissa data comparison module to determine whether the mantissa data are equal, and if the mantissa data are equal, an operation result is obtained to end the operation.

Fig. 7 is a flowchart illustrating a data processing method according to an embodiment, which may be processed by the data comparator shown in fig. 3 and 5, and this embodiment relates to a process of comparing data. As shown in fig. 7, the method includes:

s201, receiving data to be processed.

Specifically, the data comparator may receive two data to be processed. Optionally, the two pieces of data to be processed received by the data comparator may be both a multi-bit wide signed bit floating point number, and the bit widths of the two pieces of data to be processed are equal.

S202, judging whether the data to be processed has a zero value through a zero value judging circuit.

Specifically, the data comparator can determine whether zero exists in the two received data to be processed through the zero value determining circuit.

Optionally, after the zero value determining circuit determines whether the zero value exists in the data to be processed in S202, the method further includes: and if zero exists in the data to be processed, obtaining an operation result and finishing the operation.

Specifically, if a zero value exists in the data to be processed, the condition of the zero value may include two conditions, one of which is that one of the two data to be processed has a zero value and one has a non-zero value, at this time, the zero value judgment circuit may also directly judge the size of the data, and end the operation without continuing the comparison operation by other comparison circuits, and it can also be understood that, in this condition, the zero value judgment circuit may also judge the sign bit of the zero value and the non-zero value, and directly obtain the operation result; the other is that there are two zero values in the two data to be processed, and in this case, the two data to be processed may be equal.

S203, if the data to be processed does not have a zero value, the zero value judgment circuit splits the data to be processed to obtain sign bit data, exponent bit data and mantissa bit data in the data to be processed, and the sign bit comparison circuit compares whether the sign bit data are equal in size or not.

Specifically, if no zero value exists in the data to be processed, the sign bit comparison circuit may compare the two received sign bit values, and obtain an operation result according to the comparison result. Optionally, the zero value judging circuit may perform data splitting on the two data to be processed to obtain sign bit data, exponent bit data, and mantissa bit data of the two data to be processed, and input the two sign bit data, the two exponent bit data, and the two mantissa bit data to the sign bit comparing circuit. Optionally, the zero value determining circuit may split the data to be processed to obtain sign bit data, exponent bit data, and mantissa bit data in the data to be processed.

Optionally, after the step of comparing whether the sign bit data size is equal by the sign bit comparing circuit in S203, the method further includes: and if the sign bit data are not equal, obtaining an operation result and finishing the operation.

And S204, if the sign bit data are equal, the sign bit comparison circuit inputs the exponent bit data and the mantissa bit data into a data comparison circuit, and the data comparison circuit compares the highest nonzero digit in the mantissa bit data, the exponent bit data and/or the mantissa bit data to obtain an operation result.

Specifically, if the sign bit comparison circuit in the data comparator determines that the sign bit data in the two pieces of data to be processed are equal, the sign bit comparison circuit can input the received two pieces of exponent bit data and two pieces of mantissa bit data to the data comparison circuit, and the data comparison circuit compares the sizes of the highest nonzero digit position in the two pieces of data to be processed, the exponent bit data and/or the mantissa bit data to obtain an operation result.

The data comparator provided by this embodiment receives data to be processed, determines whether a zero value exists in the data to be processed through a zero value determining circuit, and if the zero value does not exist in the data to be processed, the zero value determining circuit inputs sign bit data, exponent bit data, and mantissa bit data in the data to be processed to a sign bit comparing circuit, and compares the magnitude of the sign bit data through the sign bit comparing circuit to obtain an operation result, so that the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can also perform comparison operation on the floating point number, so that the universality of the data comparator is improved.

As one embodiment, the sign bit comparing circuit in S204 inputs the exponent bit data and the mantissa bit data to a data comparing circuit, and the data comparing circuit compares the size of the highest nonzero digit bit in the mantissa bit data, the exponent bit data and/or the mantissa bit data to obtain an operation result, including:

s2041, judging whether the digit size of the highest nonzero digit in the mantissa digit data is equal through a highest nonzero digit comparison module.

Optionally, after the step of determining, by the highest nonzero-bit comparison module in S2041, whether the bit size of the highest nonzero bit in the mantissa data is equal to or not, the method further includes: if the digit sizes of the highest nonzero digit are not equal, obtaining an operation result and finishing the operation.

S2042, if the sizes of the digits of the highest nonzero digit are equal, judging whether the sizes of the exponential digit data are equal through an exponential digit comparison module.

Specifically, if the highest nonzero-position comparison module outputs a low-level signal, the size of the highest nonzero-position digit in the signified mantissa digit data is equal, at this time, the data comparator needs to compare the size of the exponent digit data in the data to be processed through the exponent digit comparison module, and judges whether the size of the exponent digit data is equal according to the comparison result.

Optionally, after the determining, by the exponent data comparing module, whether the exponent data magnitudes are equal in S2042, the method further includes: if the exponent bit data are not equal in size, an operation result is obtained, and the operation is finished.

It should be noted that, if the exponent bits in the two pieces of data to be processed are not equal, the larger the exponent bits are for positive numbers, the larger the data to be processed is, and for negative numbers, the larger the exponent bits are, the smaller the data to be processed is.

S2043, if the exponent bit data are equal in size, judging whether the mantissa bit data are equal in size through a mantissa bit comparison module.

Specifically, if the exponent bit comparison module outputs a low level signal, the magnitude of the significand bit data is equal, and at this time, the data comparator needs to compare the magnitude of mantissa data in the data to be processed through the mantissa bit comparison module, and determine whether the magnitude of mantissa data is equal according to the comparison result.

Optionally, after the determining, by the mantissa bit comparing module in S2043, whether the mantissa data in the to-be-processed data are equal in size, the method further includes: if the mantissa bit data are equal in size, an operation result is obtained, and the operation is finished.

It should be noted that, if the mantissa bit comparison result output port aeqb5 in the mantissa bit comparison module outputs a high level signal, the two mantissa bit data are equal in size, which can indicate that the two to-be-processed data received by the data comparator are equal in size.

S2044, if the mantissa bit data are not equal in size, obtaining an operation result, and ending the operation.

Specifically, if the mantissa bit comparison module determines that the mantissa bit data are not equal in size, for a positive number, the larger the mantissa bit data is, the larger the to-be-processed data is, and for a negative number, the larger the mantissa bit data is, the smaller the to-be-processed data is.

The embodiment of the invention also provides a machine learning arithmetic device which comprises one or more data comparators mentioned in the application and is used for acquiring data to be operated and control information from other processing devices, executing specified machine learning arithmetic and transmitting the execution result to peripheral equipment through an I/O interface. Peripheral devices such as cameras, displays, mice, keyboards, network cards, wifi interfaces, servers. When more than one data comparator is included, the data comparators can be linked and transmit data through a specific structure, for example, through the PCIE bus for interconnection and data transmission, so as to support larger-scale machine learning operations. At this time, the same control system may be shared, or there may be separate control systems; the memory may be shared or there may be separate memories for each accelerator. In addition, the interconnection mode can be any interconnection topology.

The machine learning arithmetic device has high compatibility and can be connected with various types of servers through PCIE interfaces.

The embodiment of the invention also provides a combined processing device which comprises the machine learning arithmetic device, the universal interconnection interface and other processing devices. The machine learning arithmetic device interacts with other processing devices to jointly complete the operation designated by the user. Fig. 8 is a schematic view of a combined treatment apparatus.

Other processing devices include one or more of general purpose/special purpose processors such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), neural network processors, and the like. The number of processors included in the other processing devices is not limited. The other processing devices are used as interfaces of the machine learning arithmetic device and external data and control, and comprise data transportation to finish basic control of starting, stopping and the like of the machine learning arithmetic device; other processing devices can cooperate with the machine learning calculation device to complete calculation tasks.

And the universal interconnection interface is used for transmitting data and control instructions between the machine learning arithmetic device and other processing devices. The machine learning arithmetic device obtains the required input data from other processing devices and writes the input data into a storage device on the machine learning arithmetic device; control instructions can be obtained from other processing devices and written into a control cache on a machine learning arithmetic device chip; the data in the storage module of the machine learning arithmetic device can also be read and transmitted to other processing devices.

Alternatively, as shown in fig. 9, the configuration may further include a storage device, and the storage device is connected to the machine learning arithmetic device and the other processing device, respectively. The storage device is used for storing data in the machine learning arithmetic device and the other processing device, and is particularly suitable for data which is required to be calculated and cannot be stored in the internal storage of the machine learning arithmetic device or the other processing device.

The combined processing device can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video monitoring equipment, the core area of a control part is effectively reduced, the processing speed is increased, and the overall power consumption is reduced. In this case, the generic interconnect interface of the combined processing device is connected to some component of the apparatus. Some parts are such as camera, display, mouse, keyboard, network card, wifi interface.

In some embodiments, a chip is also claimed, which includes the above machine learning arithmetic device or the combined processing device.

In some embodiments, a chip package structure is provided, which includes the above chip.

In some embodiments, a board card is provided, which includes the above chip package structure. As shown in fig. 10, fig. 10 provides a card that may include other kits in addition to the chip 389, including but not limited to: memory device 390, receiving means 391 and control device 392;

the memory device 390 is connected to the chip in the chip package structure through a bus for storing data. The memory device may include a plurality of groups of memory cells 393. Each group of the storage units is connected with the chip through a bus. It is understood that each group of the memory cells may be a DDR SDRAM (Double Data Rate SDRAM).

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the storage device may include 4 sets of the storage unit. Each group of the memory cells may include a plurality of DDR4 particles (chips). In one embodiment, the chip may internally include 4 72-bit DDR4 controllers, and 64 bits of the 72-bit DDR4 controller are used for data transmission, and 8 bits are used for ECC check. It can be understood that when DDR4-3200 particles are adopted in each group of memory cells, the theoretical bandwidth of data transmission can reach 25600 MB/s.

In one embodiment, each group of the memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. And a controller for controlling DDR is arranged in the chip and is used for controlling data transmission and data storage of each memory unit.

The receiving device is electrically connected with the chip in the chip packaging structure. The receiving device is used for realizing data transmission between the chip and an external device (such as a server or a computer). For example, in one embodiment, the receiving device may be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface, so as to implement data transfer. Preferably, when PCIE 3.0X 16 interface transmission is adopted, the theoretical bandwidth can reach 16000 MB/s. In another embodiment, the receiving device may also be another interface, and the present application does not limit the concrete expression of the other interface, and the interface unit may implement the switching function. In addition, the calculation result of the chip is still transmitted back to an external device (e.g., a server) by the receiving apparatus.

The control device is electrically connected with the chip. The control device is used for monitoring the state of the chip. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may include a single chip Microcomputer (MCU). The chip may include a plurality of processing chips, a plurality of processing cores, or a plurality of processing circuits, and may carry a plurality of loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation and control of the working states of a plurality of processing chips, a plurality of processing andor a plurality of processing circuits in the chip.

In some embodiments, an electronic device is provided that includes the above board card.

The electronic device may be a data processor, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

It should be noted that, for simplicity of description, the foregoing method embodiments are described as a series of circuit combinations, but those skilled in the art should understand that the present application is not limited by the described circuit combinations, because some circuits may be implemented in other ways or structures according to the present application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are all alternative embodiments, and that the devices and modules referred to are not necessarily required for this application.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A data comparator, characterized in that the data comparator comprises: the output end of the zero value judging circuit is connected with the input end of the sign bit comparing circuit, and the output end of the sign bit comparing circuit is connected with the input end of the data comparing circuit;

2. The data comparator as claimed in claim 1, wherein the zero value judging circuit comprises: a data input port, a sign bit output port, a first mantissa bit output port, a first exponent bit output port, and a zero value judgment result output port;

3. The data comparator as claimed in claim 1, wherein the sign bit comparison circuit comprises: sign bit input port, first mantissa bit input port, first exponent bit input port, sign bit logic judgment signal output port, second mantissa bit output port, second exponent bit output port, sign bit comparison result output port;

4. The data comparator as claimed in claim 1, wherein the data comparison circuit comprises: the device comprises a highest nonzero digit comparison module, an exponent digit comparison module and a mantissa digit comparison module, wherein the output end of the highest nonzero digit comparison module is connected with the input end of the exponent digit comparison module, and the output end of the exponent digit comparison module is connected with the input end of the mantissa digit comparison module;

5. The data comparator as claimed in claim 4, wherein the highest non-zero bit compare module comprises: a second mantissa bit input port, a second exponent bit input port, a highest non-zero logic judgment signal output port and a highest non-zero comparison result output port;

6. The data comparator as claimed in claim 4, wherein the exponent bit comparison module comprises: a third mantissa data input port, a third exponent data input port, a fourth mantissa data output port, an exponent bit logic judgment signal output port and an exponent bit comparison result output port;

7. The data comparator as claimed in claim 4, wherein the mantissa bit comparison module comprises: a fourth mantissa data input port and a mantissa comparison result output port; the fourth mantissa data input port is configured to receive the first mantissa data and the second mantissa data input by the exponent data comparing module, and the mantissa data comparison result output port is configured to output a size comparison result of the first mantissa data and the second mantissa data.

8. A method of data processing, the method comprising:

receiving data to be processed;

9. The method of claim 8, wherein after the determining whether the zero value exists in the data to be processed by the zero value determining circuit, the method further comprises: and if zero exists in the data to be processed, obtaining an operation result and finishing the operation.

10. The method of claim 8, wherein after comparing the sign bit data size by the sign bit comparison circuit is equal, further comprising: and if the sign bit data are not equal, obtaining an operation result and finishing the operation.

11. The method according to claim 8, wherein the sign bit comparison circuit inputs the exponent bit data and the mantissa bit data to a data comparison circuit, and the data comparison circuit compares the size of the highest nonzero digit position in the mantissa bit data, the exponent bit data and/or the mantissa bit data to obtain an operation result, including:

12. The method of claim 11, wherein after determining, by the highest non-zero bit comparison module, whether the bit sizes of the highest non-zero bits in the mantissa data are equal, further comprising: if the digit sizes of the highest nonzero digit are not equal, obtaining an operation result and finishing the operation.

13. The method as claimed in claim 11, wherein after determining whether the exponent data magnitudes are equal by the exponent data comparison module, the method further comprises: if the exponent bit data are not equal in size, an operation result is obtained, and the operation is finished.

14. The method as claimed in claim 11, wherein after determining whether mantissa data size in the data to be processed is equal by the mantissa data comparison module, the method further comprises: if the mantissa bit data are equal in size, an operation result is obtained, and the operation is finished.

15. A machine learning arithmetic device, characterized in that the machine learning arithmetic device comprises one or more data comparators as claimed in any one of claims 1 to 7, and is used for acquiring input data and control information to be operated from other processing devices, executing specified machine learning operation, and transmitting the execution result to other processing devices through an I/O interface;

when the machine learning arithmetic device comprises a plurality of data comparators, the plurality of computing devices can be connected through a specific structure and transmit data;

16. A combined processing apparatus, characterized in that the combined processing apparatus comprises the machine learning arithmetic apparatus according to claim 15, a universal interconnect interface and other processing apparatus;

and the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user.

17. The combined processing device according to claim 16, further comprising: and a storage device connected to the machine learning arithmetic device and the other processing device, respectively, for storing data of the machine learning arithmetic device and the other processing device.

18. A neural network chip, wherein the machine learning chip comprises the machine learning arithmetic device of claim 15 or the combined processing device of claim 16.

19. An electronic device, characterized in that it comprises a chip according to claim 18.

20. The utility model provides a board card, its characterized in that, the board card includes: a memory device, a receiving device and a control device and a neural network chip as claimed in claim 18;

wherein the neural network chip is respectively connected with the storage device, the control device and the receiving device;

the storage device is used for storing data;

the receiving device is used for realizing data transmission between the chip and external equipment;

and the control device is used for monitoring the state of the chip.

21. The board card of claim 20,

the memory device includes: a plurality of groups of memory cells, each group of memory cells is connected with the chip through a bus, and the memory cells are: DDR SDRAM;

the chip includes: the DDR controller is used for controlling data transmission and data storage of each memory unit;

the receiving device is as follows: a standard PCIE interface.