CN111258534B

CN111258534B - Data comparator, data processing method, chip and electronic equipment

Info

Publication number: CN111258534B
Application number: CN201811450789.5A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Cambricon Information Technology Co Ltd
Current assignee: Shanghai Cambricon Information Technology Co Ltd
Priority date: 2018-11-30
Filing date: 2018-11-30
Publication date: 2022-10-04
Anticipated expiration: 2038-11-30
Also published as: CN111258534A

Abstract

The application provides a data comparator, a data processing method, a chip and an electronic device, wherein the data comparator comprises: the data processor can reduce the operation amount and save the operation time; in addition, the data comparator can select mode signals according to different functions received by the judging circuit and the comparing circuit so as to process data operation with various bit widths, and the area of the AI chip occupied by the data comparator is effectively reduced.

Description

Data comparator, data processing method, chip and electronic equipment

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a data comparator, a data processing method, a chip, and an electronic device.

Background

With the continuous development of digital electronic technology, the rapid development of various Artificial Intelligence (AI) chips has higher and higher requirements for high-performance digital comparators. The neural network algorithm is one of algorithms widely applied to intelligent chips, and a data comparator is required to be used for data size comparison operation for many times.

Generally, a large amount of various data need to be input into the data comparator for comparison, so that the operation amount of the data comparator is too large, the operation time is long, and the processing efficiency of the data comparator is affected. In addition, when the data with different bit widths are operated, the data with the same bit width is operated by the existing comparator with the corresponding bit number, and the data with different bit widths is operated by the existing comparators with different bit widths. However, different comparators are required to perform comparison operation for data with different bit widths, which results in a large area occupied by the data comparators on the AI chip.

Disclosure of Invention

In view of the above, it is desirable to provide a data comparator, a data processing method, a chip and an electronic device.

An embodiment of the present invention provides a data comparator, including: the device comprises a judgment circuit and a comparison circuit, wherein the judgment circuit comprises a zero value judgment unit, the comparison circuit comprises a sign bit comparison unit and an exponent bit comparison unit, the output end of the zero value judgment unit is connected with the input end of the sign bit comparison unit and the input end of the exponent bit comparison unit, and the output end of the sign bit comparison unit is connected with the input end of the exponent bit comparison unit;

the zero value judging unit is used for judging whether zero values exist in the received data or not, the sign bit comparing unit is used for judging the size of the sign bit of the received data, and the exponent bit comparing unit is used for judging the size of the exponent bit of the received data.

In one embodiment, the judging circuit includes a first input terminal for receiving an input function selection mode signal; the comparison circuit comprises a second input end for receiving the input function selection mode signal; the function selection mode signal is used to determine the bit width of the data processed by the data comparator.

In one embodiment, the determining circuit further comprises: the output end of the non-numerical value judging unit is connected with the input end of the infinite number judging unit, the output end of the infinite number judging unit is connected with the input end of the zero value judging unit, the output end of the infinite number judging unit is connected with the input end of the non-numerical value judging unit, and the output end of the non-numerical value judging unit is connected with the input end of the zero value judging unit;

the non-numerical value judging unit is used for judging whether a non-numerical value exists in the received data, and the infinite number judging unit is used for judging whether an infinite number exists in the received data.

In one embodiment, the non-numerical value judging unit in the judging circuit includes: the device comprises a first data input port, a second data input port, a function selection mode signal input port, a first data output port, a second data output port and a non-numerical value judgment result output port, wherein the first data input port is used for receiving input first data, the second data input port is used for receiving input second data, the function selection mode signal input port is used for receiving a function selection mode signal corresponding to data with different bit widths to be processed, the first data output port is used for outputting the received first data to an input port of a next unit, the second data output port is used for outputting the received second data to an input port of the next unit, and the non-numerical value judgment result output port is used for outputting a judgment result of the non-numerical value judgment unit;

the infinity determination unit in the determination circuit includes: the first data input port is used for receiving input first data, the second data input port is used for receiving input second data, the function selection mode signal input port is used for receiving a function selection mode signal corresponding to data with different bit widths, the first data output port is used for outputting the received first data to an input port of a next unit, the second data output port is used for outputting the received second data to an input port of the next unit, and the infinite number judgment result output port is used for outputting a judgment result of the infinite number judgment unit;

the zero value judging unit in the judging circuit includes: the first data input port receives input first data, the second data input port receives input second data, the function selection mode signal input port receives function selection mode signals corresponding to data with different bit widths, the zero value judgment result output port outputs judgment results of a zero value judgment unit, the first sign bit output port outputs sign bit data of the received first data, the second sign bit output port outputs sign bit data of the received second data, the first exponent bit output port outputs exponent bit data of the received first data, the second digit output port outputs exponent bit data of the received second data, the first mantissa bit output port outputs the mantissa bit data of the received second data, the second digit mantissa bit output port outputs the mantissa bit data of the received second data, and the logic signal output port outputs logic signal.

In one embodiment, an output of the sign bit comparison unit is connected to an input of the exponent bit comparison unit.

In one embodiment, the sign bit comparison unit in the comparison circuit: the first sign bit input port is used for receiving sign bit data of the first data, the second sign bit input port is used for receiving sign bit data of the second data, the function selection mode signal input port is used for receiving a function selection mode signal corresponding to data with different bit widths to be processed, the sign bit comparison result output port is used for outputting a sign bit size comparison result of the data, and the sign bit logic signal output port is used for outputting a logic judgment signal;

the exponent bit compare unit in the compare circuit: the device comprises a first exponent bit input port, a second exponent bit input port, a function selection mode signal input port, an exponent bit comparison result output port and an exponent bit logic signal output port, wherein the first exponent bit input port is used for receiving exponent bit data of first data, the second exponent bit input port is used for receiving exponent bit data of second data, the function selection mode signal input port is used for receiving function selection mode signals corresponding to data with different bit widths to be processed, the exponent bit comparison result output port is used for outputting exponent bit size comparison results of the data, and the exponent bit logic signal output port is used for outputting logic judgment signals.

In one embodiment, the comparison circuit further comprises: and the output end of the zero value judging unit is connected with the input end of the mantissa bit comparing unit, and the mantissa bit comparing unit is used for judging the size of the mantissa bits of the received data.

In one embodiment, the mantissa bit comparison unit includes: a first mantissa bit input port, a second mantissa bit input port, a function selection mode signal input port, a mantissa bit comparison result output port, and a mantissa bit logic signal output port;

the first mantissa bit input port is configured to receive mantissa bit data of the first data, the second mantissa bit input port is configured to receive mantissa bit data of the second data, the function selection mode signal input port is configured to receive a function selection mode signal corresponding to data with different bit widths to be processed, the mantissa bit comparison result output port is configured to output a mantissa bit size comparison result of the data, and the mantissa bit logic signal output port is configured to output a logic determination signal.

The data comparator provided in this embodiment, the data comparator includes: the output end of the judging circuit is connected with the input end of the comparing circuit; the judging circuit is used for judging whether the received data needs to be processed through the comparing circuit connected with the output end of the judging circuit, the comparing circuit is used for comparing the received data, and if the data does not need to be processed through the comparing circuit, the operation is finished to obtain an operation result, so that the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can select mode signals according to different functions received by the judging circuit and the comparing circuit so as to process various data operations with different bit widths, and the area of the AI chip occupied by the data comparator is effectively reduced.

An embodiment of the present invention provides a data processing method, including:

receiving data to be processed;

judging whether the data to be processed needs to be processed through a comparison circuit or not through a judgment circuit;

if necessary, the sign bit, the exponent bit and the mantissa bit of the data to be processed are respectively input to the comparison circuit through the judgment circuit, the magnitude of the sign bit, the magnitude of the exponent bit and the magnitude of the mantissa bit of the data to be processed are compared through the comparison circuit, and an operation result is output.

In one embodiment, the determining, by the determining circuit, whether the data to be processed needs to be processed by the comparing circuit includes:

judging whether a non-numerical value, an infinite number or a zero value exists in the data to be processed through the judging circuit;

and if the data does not have a non-numerical value, an infinite number and a zero value, judging that the data needs to be processed through the comparison circuit.

In one embodiment, the determining, by the determining circuit, whether a non-numerical value, an infinite number, or a zero value exists in the data to be processed includes:

judging whether a non-numerical value exists in the data to be processed through a non-numerical value judging unit;

if the non-numerical value does not exist, inputting the data to be processed into an infinite number judging unit, and judging whether infinite numbers exist in the data to be processed through the infinite number judging unit;

if the infinite number does not exist, inputting the data to be processed into a zero value judging unit, and judging whether a zero value exists in the data to be processed or not through the zero value judging unit;

and if no zero value exists, judging that the data needs to be processed through the comparison circuit.

judging whether infinite numbers exist in the data to be processed through an infinite number judging unit;

if the infinite number does not exist, inputting the data to be processed into a non-numerical value judging unit, and judging whether a non-numerical value exists in the data to be processed through the non-numerical value judging unit;

if the non-numerical value does not exist, inputting the data to be processed into a zero value judging unit, and judging whether a zero value exists in the data to be processed or not through the zero value judging unit;

In one embodiment, after the determining, by the non-numerical value determining unit, whether a non-numerical value exists in the data to be processed, the method further includes: if the non-numerical value exists, outputting a first operation result, and finishing the operation;

after the data to be processed is input to the infinite number judging unit, and whether an infinite number exists in the data to be processed is judged by the infinite number judging unit, the method further comprises the following steps: if the infinite number exists, outputting a second operation result, and finishing the operation;

after the data to be processed is input to a zero value judging unit and the zero value judging unit judges whether a zero value exists in the data to be processed, the method further comprises the following steps: if the zero value exists, outputting a third operation result and finishing the operation.

In one embodiment, the determining circuit respectively inputs a sign bit, an exponent bit and a mantissa bit of the data to be processed into the comparing circuit, and the comparing circuit compares the magnitude of the sign bit, the exponent bit and the mantissa bit of the data to be processed to output an operation result, including:

judging whether sign bits of the received data to be processed are equal or not through a sign bit comparison unit;

if the sign bits of the data to be processed are equal, inputting the exponent bits of the data to be processed into an exponent bit comparison unit, and judging whether the exponent bits of the data to be processed are equal or not through the exponent bit comparison unit;

if the exponent bits of the data to be processed are equal, inputting the mantissa bits of the data to be processed into a mantissa bit comparison unit, and judging whether the mantissa bits of the data to be processed are equal or not through the mantissa bit comparison unit;

if the mantissa bits of the data to be processed are equal, outputting a fourth operation result, and finishing the operation; or alternatively

And performing OR logic operation on the judging circuit and an output port corresponding to each unit in the comparison circuit, and outputting an operation result.

In one embodiment, after the judging, by the sign bit comparing unit, whether the sign bits of the received data to be processed are equal, the method further includes: if the sign bits of the data to be processed are not equal, outputting a fifth operation result and finishing the operation;

after the exponent bits of the data to be processed are input to an exponent bit comparison unit, and whether the exponent bits of the data to be processed are equal is judged by the exponent bit comparison unit, the method further comprises the following steps: and if the exponent bits of the data to be processed are not equal, outputting a sixth operation result and finishing the operation.

In one embodiment, the exponent bit comparing unit determines whether exponent bits of the data to be processed are equal, including:

dividing exponent bits of the data to be processed into a first exponent bit and a second exponent bit, and judging whether the first exponent bits are equal;

if the first exponent bits of the data exponent bits to be processed are equal, judging whether the second exponent bits are equal;

and if the second exponent bits of the data to be processed are equal, continuously judging whether the mantissa bits of the data to be processed are equal through the mantissa bit comparison unit.

In one embodiment, after the mantissa bits of the data to be processed are input to the mantissa bit comparing unit, and whether the mantissa bits of the data to be processed are equal is judged by the mantissa bit comparing unit, the method further includes: and if the mantissa bits of the data to be processed are not equal, outputting a seventh operation result and finishing the operation.

In one embodiment, the mantissa bit comparing unit determines whether mantissa bits of the data to be processed are equal, including:

dividing mantissa bits of the data to be processed into a first mantissa bit and a second mantissa bit, and judging whether the first mantissa bits are equal;

and if the first mantissa bits of the exponent bits of the data to be processed are equal, judging whether the second mantissa bits are equal.

In the data comparison data processing method provided by this embodiment, the data comparator receives the selection mode signal and the data to be processed, and determines, by the determination circuit, whether the data to be processed needs to be processed by the comparison circuit, if the data needs to be processed by the comparison circuit, the determination circuit inputs the data to be processed into the comparison circuit, and compares the sign bit, the exponent bit and the mantissa bit of the data to be processed by the comparison circuit, and outputs the operation result, and if the data does not need to be processed by the comparison circuit, the operation is ended to obtain the operation result, so that the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can select mode signals according to different functions received by the judging circuit and the comparing circuit so as to process data operation with various bit widths, and the area of the AI chip occupied by the data comparator is effectively reduced.

The machine learning arithmetic device provided by the embodiment of the invention comprises one or more data comparators; the machine learning arithmetic device is used for acquiring data to be operated and control information from other processing devices, executing specified machine learning arithmetic and transmitting an execution result to other processing devices through an I/O interface;

when the machine learning arithmetic device comprises a plurality of data comparators, the data comparators can be linked and transmit data through a specific structure;

the data comparators are interconnected through a PCIE bus and transmit data so as to support larger-scale machine learning operation; a plurality of the data comparators share the same control system or own respective control systems; the data comparators share a memory or own respective memories; the interconnection mode of the data comparators is any interconnection topology.

The combined processing device provided by the embodiment of the invention comprises the machine learning processing device, the universal interconnection interface and other processing devices; the machine learning arithmetic device interacts with the other processing devices to jointly complete the operation designated by the user; the combined processing device may further include a storage device, which is connected to the machine learning arithmetic device and the other processing device, respectively, and is configured to store data of the machine learning arithmetic device and the other processing device.

The embodiment of the present invention provides a neural network chip, which includes the data comparator, the machine learning arithmetic device, or the combination processing device.

The embodiment of the invention provides a neural network chip packaging structure which comprises the neural network chip.

The board card provided by the embodiment of the invention comprises the neural network chip packaging structure.

The embodiment of the application provides an electronic device, which comprises the neural network chip or the board card.

An embodiment of the present invention provides a chip, including at least one data comparator as described in any one of the above.

The electronic equipment provided by the embodiment of the invention comprises the chip.

Drawings

FIG. 1 is a schematic diagram of an overall structure of a data comparator;

FIG. 2 is a block diagram of a data comparator according to one embodiment;

FIG. 3 is a diagram of an internal circuit configuration of a data comparator according to another embodiment;

FIG. 4 is a specific circuit configuration diagram of a data comparator according to another embodiment;

fig. 5 is a schematic diagram of a specific structure of a determining circuit according to another embodiment;

fig. 6 is a schematic structural diagram of a data comparator according to an embodiment;

FIG. 7 is a schematic diagram of another embodiment of a data comparator;

FIG. 8 is a schematic diagram of a specific structure of a comparison circuit according to another embodiment;

FIG. 9 is a flowchart illustrating a data processing method according to an embodiment;

FIG. 10 is a flow diagram illustrating a method for determining whether a non-numeric, an infinite, or a zero value is present in data according to one embodiment;

FIG. 11 is a flow chart illustrating a method for determining whether a non-numeric value, an infinite number, or a zero value exists in data according to another embodiment;

FIG. 12 is a flowchart illustrating a method for determining whether a sign bit, a exponent bit, and a mantissa bit of data are equal according to one embodiment;

FIG. 13 is a flowchart illustrating a method for determining whether a sign bit, an exponent bit, and a mantissa bit of data are equal according to another embodiment;

FIG. 14 is a flowchart illustrating an embodiment of a method for determining exponent bits of data according to another embodiment;

FIG. 15 is a flowchart illustrating a method for determining mantissa bits of data according to another embodiment;

FIG. 16 is a flowchart illustrating a data processing method according to another embodiment;

FIG. 17 is a flowchart illustrating a method for outputting operation results according to another embodiment;

FIG. 18 is a block diagram of a combined processing device according to an embodiment;

FIG. 19 is a block diagram of another alternative combination processing device according to an embodiment;

fig. 20 is a schematic structural diagram of a board card according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.

The data comparator provided by the application can be applied to an AI chip, a Field-Programmable Gate Array (FPGA) chip, or other hardware circuit devices for comparison operation processing, and a schematic structural diagram of the data comparator is shown in fig. 1.

Fig. 2 is a schematic structural diagram of a data comparator according to an embodiment. As shown in fig. 2, the data comparator includes: the output end of the judging circuit 11 is connected with the input end of the comparing circuit 12; the judging circuit 11 is configured to judge whether the received data needs to be processed by a comparing circuit 12 connected to an output end of the judging circuit 11, where the comparing circuit 12 is configured to compare the received data.

Specifically, the judgment circuit 11 and the comparison circuit 12 may process data in a serial manner, or may process data in a parallel manner through or logic. Alternatively, the judging circuit 11 may be a circuit that judges a value type of the received data. Optionally, the data may be floating point numbers. Optionally, the value types may include non-values, infinity numbers and zero values. Alternatively, the comparison circuit 12 may be a circuit that compares the sign bit, exponent bit, and mantissa bit of the received data. Alternatively, the comparison circuit 12 may include a plurality of comparison units having different functions. Optionally, there may be a plurality of input ports of the comparing units with different functions, each input port of each comparing unit may have different or the same function, and there may also be a plurality of output ports, and each output port of each comparing unit may have the same or different function, but the input ports of different comparing units may have the same or different functions, and the output ports of different comparing units may have the same or different functions, and the comparing units with different functions may have different or the same circuit structures.

Optionally, the determining circuit 11 includes a first input terminal 01 for receiving an input function selection mode signal; the comparison circuit 12 includes a second input end 02 for receiving the input function selection mode signal; the function selection mode signal is used to determine the bit width of the data processed by the data comparator.

It should be noted that the function selection mode signal may be various, and different function selection mode signals correspond to data comparators capable of processing data with different bit widths.

In the data comparator provided in this embodiment, the determining circuit determines whether the received data needs to be processed by the next comparing circuit, if the received data does not need to be processed by the next comparing circuit, the operation is ended to obtain the operation result, otherwise, the received data is continuously input to the comparing circuit. When the comparison circuit outputs a high-level signal, the operation is finished to obtain an operation result, so that the operation amount can be reduced, and the operation time is saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the judging circuit and the comparing circuit, and the area of the AI chip occupied by the data comparator is effectively reduced.

In one embodiment, the judging circuit 11 may be specifically configured to judge whether a non-numerical value, an infinite number, or a zero value exists in the received data, and judge whether the comparing circuit needs to perform the next processing according to the result.

Specifically, the above-mentioned judgment circuit 11 may include a circuit that compares the received data with a coding format corresponding to a non-numeric value, an infinite number, or a zero value in the IEEE data arithmetic standard. Alternatively, the above-described judgment circuit 11 may include a plurality of judgment units having different functions. In addition, there may be a plurality of input ports of the determination units with different functions, and the functions of each input port of each determination unit may be different or the same; similarly, there may be a plurality of output ports, the function of each output port of each judgment unit may be the same or different, and the circuit structures of different function judgment units may be different or the same.

In the data comparator provided by this embodiment, it is determined by the determining circuit whether there is a non-numerical value, an infinite value or a zero value, if the determining result is yes, the operation is ended to obtain the operation result, otherwise, the received data is continuously input into the comparing circuit, and when the comparing circuit outputs a high level signal, the operation is ended to obtain the operation result, so that when the determining result of the determining circuit in the data comparator is yes, the operation is ended, the operation of the comparing circuit is not required, the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the judging circuit and the comparing circuit, and the area of the AI chip occupied by the data comparator is effectively reduced.

Fig. 3 is a block diagram of a data comparator according to another embodiment. As shown in fig. 3, the data comparator includes: the circuit comprises a judgment circuit 11 and a comparison circuit 12, wherein the judgment circuit 11 comprises a zero value judgment unit 113, the comparison circuit comprises a sign bit comparison unit 121 and an exponent bit comparison unit 122, the output end of the zero value judgment unit 113 is connected with the input end of the sign bit comparison unit 121 and the input end of the exponent bit comparison unit 122, and the output end of the sign bit comparison unit 121 is connected with the input end of the exponent bit comparison unit 122;

the zero value determining unit 113 is configured to determine whether a zero value exists in the received data, the sign bit comparing unit 121 is configured to determine a sign bit size of the received data, and the exponent bit comparing unit 122 is configured to determine an exponent bit size of the received data.

Specifically, the judgment circuit 11 and the comparison circuit 12 may process data in a serial manner, and may also process data in a parallel manner through or logic. Optionally, the judging circuit 11 may be a circuit for judging a value type of the received data, and the judging circuit 11 may include a plurality of judging units for judging the value type of the data, where the value type may include a non-value, an infinite number, and a zero value. Alternatively, the comparison circuit 12 may be a circuit that compares the sign bit, exponent bit, and mantissa bit of the received data. Alternatively, the comparison circuit 12 may include a plurality of comparison units with different functions. Optionally, there may be a plurality of input ports of the comparing units with different functions, each input port of each comparing unit may have different or the same function, there may also be a plurality of output ports, and each output port of each comparing unit may have the same or different function, however, the input ports of different comparing units may have the same or different functions, the output ports of different comparing units may have the same or different functions, and the comparing units with different functions may have different or the same circuit structures.

Optionally, an output of the sign bit comparing unit 121 is connected to an input of the exponent bit comparing unit 122.

If the determination result of zero value determining section 113 is yes, zero value determining section 113 may output a high level signal, and at this time, the operation is ended and the operation result is output. If the judgment result of the zero-value judgment unit 113 does not satisfy the preset condition, the zero-value judgment unit 113 may output a low-level signal, and at this time, the operation is not ended, and the processing needs to be continued by the next unit. Optionally, the preset condition that is satisfied may be characterized in that the received data satisfies a coding format corresponding to a zero value in the IEEE standard. In the IEEE data arithmetic standard, the coding format corresponding to zero can be expressed as that the exponent bits of the data are all 0 and the mantissa bits are all 0.

Optionally, the determining circuit 11 includes a first input terminal 01 for receiving an input function selection mode signal; the comparison circuit 12 includes a second input terminal 02 for receiving the input function selection mode signal.

In the data comparator provided by this embodiment, the zero value judging unit in the judging circuit judges whether a zero value exists in the received data, if the zero value exists in the received data, the judging result of the judging unit is yes, and at this time, the operation is finished to output the operation result, and the operation of the comparing circuit is not required, so that the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the judging circuit and the comparing circuit, and the area of the AI chip occupied by the data comparator is effectively reduced.

Fig. 4 is a schematic structural diagram of a data comparator according to another embodiment, as shown in fig. 4, the data comparator includes the determining circuit 11, and the determining circuit 11 further includes: a non-numerical value judging unit 111 and an infinite number judging unit 112, wherein an output end of the non-numerical value judging unit 111 is connected with an input end of the infinite number judging unit 112;

the non-numerical value determining unit 111 is configured to determine whether a non-numerical value exists in the received data, and the infinity determining unit 112 is configured to determine whether an infinity exists in the received data.

Optionally, an output end of the infinity judgment unit 112 is connected to an input end of the zero value judgment unit 113.

It should be noted that, the non-numerical value determining unit 111, the infinite number determining unit 112, and the zero value determining unit 113 sequentially process the received data until the determination result of one of the determining units satisfies the preset condition, and if the determination result of any one of the three determining units is yes, the corresponding determining unit with the yes determination result outputs a high level signal, and at this time, the operation is ended and the operation result is output. If the judgment result of any one or more judgment units in the three judgment units does not meet the preset condition, the corresponding judgment unit which does not meet the preset condition can output a low level signal, and at the moment, the operation is not finished, and the processing needs to be continuously carried out through the next unit. Optionally, the preset condition that is satisfied may be characterized in that the received data satisfies a coding format corresponding to a non-numerical value, an infinite number, or a zero value in the IEEE standard. In the IEEE data arithmetic standard, the encoding format corresponding to the non-numeric value can be expressed as that the exponent bits of the data are all 0 and the mantissa bits are not all 0; the encoding format corresponding to the infinite number can be expressed as that the exponent bits of the data are all 0 and the mantissa bits are all 0; the encoding format for zero correspondence can be expressed as the exponent bits of the data are all 0's and the mantissa bits are all 0's.

Optionally, the output end of the infinity judging unit 112 may be further connected to the input end of the non-numerical value judging unit 111, and the output end of the non-numerical value judging unit 111 is connected to the input end of the zero value judging unit 113. It should be noted that, the connection structures of the non-numerical value judging unit 111 and the infinite number judging unit 112 in the judging circuit 11 may be interchanged, and this embodiment is not limited in any way.

In the data comparator provided in this embodiment, through the non-value determining unit, the infinite number determining unit and the zero value determining unit, it is sequentially determined whether a non-value, an infinite number or a zero value exists in the received data, and if the non-value, the infinite number or the zero value exists in the received data and the determination result of the corresponding determining unit is yes, the operation is ended and the operation result is output, and the operation of the comparing circuit is not required, so that the operation amount can be reduced and the operation time can be saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the judging circuit and the comparing circuit, and the area of the AI chip occupied by the data comparator is effectively reduced.

Fig. 5 is a schematic structural diagram of a determining circuit according to another embodiment, as shown in fig. 5, the determining circuit 11 includes: the output end of the non-numerical value judging unit 111 is connected with the input end of the infinite number judging unit 112, and the output end of the infinite number judging unit 112 is connected with the input end of the zero value judging unit 113; the non-numerical value determining unit 111 is configured to determine whether a non-numerical value exists in the received data, the infinity determining unit 112 is configured to determine whether an infinity number exists in the received data, and the zero value determining unit 113 is configured to determine whether a zero value exists in the received data.

Optionally, an output end of the infinity judgment unit 112 is connected to an input end of the non-numerical value 111 judgment unit, and an output end of the non-numerical value 111 is connected to an input end of the zero value judgment unit 113.

It should be noted that, the non-numerical value determining unit 111, the infinite number determining unit 112, and the zero value determining unit 113 sequentially process the received data until the determination result of one of the determining units satisfies the preset condition, and if the determination result of any one of the three determining units is yes, the corresponding determining unit with the yes determination result outputs a high level signal, and at this time, the operation is ended and the operation result is output. If the judgment result of any one or more judgment units in the three judgment units does not meet the preset condition, the corresponding judgment unit which does not meet the preset condition outputs a low level signal, and at the moment, the operation is not finished, and the processing needs to be continued through the next unit. Optionally, the preset condition that is satisfied may be characterized in that the received data satisfies a coding format corresponding to a non-numeric value, an infinite number, or a zero value in the IEEE standard. In the IEEE data arithmetic standard, the encoding format corresponding to the non-numeric value can be expressed as that the exponent bits of the data are all 0, and the mantissa bits are not all 0; the encoding format corresponding to the infinite number can be expressed as that the exponent bits of the data are all 0 and the mantissa bits are all 0; the encoding format for zero correspondence may be expressed as exponent bits of data all being 0 and mantissa bits all being 0.

In one embodiment, as shown in fig. 6 and 7, a specific structural diagram of a data comparator is shown, and the non-numerical value determining unit 111 in both the data comparators includes: a first data input port 1111, a second data input port 1112, a function selection mode signal input port (mode) 1113, a first data output port 1114, a second data output port 1115, a non-numeric decision result output port (unordered) 1116; the first data input port 1111 is configured to receive input first data, the second data input port 1112 is configured to receive input second data, the function selection mode signal input port (mode) 1113 is configured to receive a function selection mode signal corresponding to data with different bit widths to be processed, the first data output port 1114 is configured to output the received first data to an input port of a next unit, the second data output port 1115 is configured to output the received second data to an input port of the next unit, and the non-numeric value determination result output port (unordered) 1116 is configured to output a determination result of the non-numeric value determining unit 111.

The non-numeric determination result output port (unordered) 1116 may output a determination result as a logic signal, which may be a high-level signal or a low-level signal. If the determination result of the non-numerical value determining unit 111 satisfies the preset condition, the non-numerical value determination result output port (unordered) 1116 may output a high level signal to end the operation, which may indicate that at least one non-numerical value exists in the two data received by the non-numerical value determining unit 111. If the determination result of the non-numerical value determining unit 111 satisfies the preset condition, the non-numerical value determination result output port (unordered) 1116 may output a low level signal, which may not end the operation, and needs to perform the next unit processing, which may indicate that there is no non-numerical value in the data received by the non-numerical value determining unit 111. Optionally, the preset condition corresponding to the non-numerical value determining unit 111 may be whether the data received by the non-numerical value determining unit 111 meets an encoding format corresponding to a non-numerical value in the IEEE standard. Optionally, the function selection mode signal input in the non-numerical value determining unit 111 may be determined according to a user requirement, and may determine a data bit width currently processable by the data comparator according to the input function selection mode signal.

In the data comparator provided by this embodiment, the non-numerical judgment unit may determine whether the data comparator can directly end the operation to output the operation result according to the judgment result output by the non-numerical judgment result output port, and at this time, the data comparator does not need to perform the subsequent operations of other units, so that the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the function selection mode signal input port, and the area of the AI chip occupied by the data comparator is effectively reduced.

In one embodiment, as shown in fig. 6 and fig. 7, a specific structural diagram of a data comparator is shown, and the infinity determining unit 112 in both the data comparators includes: a first data input port 1121, a second data input port 1122, a function selection mode signal input port (mode) 1123, a first data output port 1124, a second data output port 1125, an infinity determination result output port (altb 1) 1126, (aeqb 1) 1127, and (agtb 1) 1128; the first data input port 1121 is configured to receive the first data input, the second data input port 1122 is configured to receive the second data input, the function selection mode signal input port (mode) 1123 is configured to receive a function selection mode signal corresponding to data with different bit widths to be processed, the first data output port 1124 is configured to output the received first data to an input port of a next unit, the second data output port 1125 is configured to output the received second data to an input port of a next unit, the infinity determination result output port (altb 1) 1126, (aeqb 1) 1127, and (agtb 1) 1128 are configured to output a determination result of the infinity determination unit 112.

Specifically, the determination results output by the three infinity determination result output ports (altb 1) 1126, (aeqb 1) 1127 and (agtb 1) 1128 may be logic signals, which may be high-level signals or low-level signals. If the determination result of the infinite number determining unit 112 satisfies the predetermined condition, any one of the infinite number determining result output ports (altb 1) 1126, any one of the (aeqb 1) 1127 and (agtb 1) 1128 may output a high level signal, and the other two ports output low level signals, so as to end the operation, which may indicate that at least one infinite number exists in the two data received by the infinite number determining unit 112. If all three ports output low level signals, it may indicate that there is no infinity in the data received by the infinity determining unit 112, and the operation cannot be ended, and the next unit processing is required. Optionally, the preset condition corresponding to the infinity judging unit 112 may be whether the received data meets a coding format corresponding to an infinity in the IEEE standard. Optionally, the function selection mode signal input in the infinity judgment unit 112 may be determined according to a user requirement, and a data bit width currently processable by the data comparator may be determined according to the input function selection mode signal.

It should be noted that if the two data received by the data comparator are a and b, respectively, the output high level signal of altb1 can be characterized as a being less than b, the output high level signal of aeqb1 can be characterized as a being equal to b, and the output high level signal of agtb1 can be characterized as a being greater than b.

In the data comparator provided by this embodiment, the infinity judgment unit may determine whether the data comparator can directly end the operation and output the operation result according to the judgment result output by the infinity judgment result output port, and at this time, the data comparator does not need to perform subsequent operations on other units, so that the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the function selection mode signal input port, and the area of the AI chip occupied by the data comparator is effectively reduced.

In one embodiment, as shown in fig. 6, a specific structural diagram of a data comparator is shown, where the zero value determining unit 113 in the data comparator includes: a first data input port 1131, a second data input port 1132, a function selection mode signal input port (mode) 1133, a zero value determination result output port (altb 2) 1134a, (altb 2) 1134b, and (agtb 2) 1134c, a first sign bit output port 1135a, a second sign bit output port 1135b, a first exponent bit output port 1136a, a second exponent bit output port 1136b, a first mantissa bit output port 1137a, a second mantissa bit output port 1137b, and a logic signal output port 1138;

the first data input port 1131 receives the first data, the second data input port 1132 is configured to receive the second data, the function selection mode signal input port (mode) 1133 is configured to receive a function selection mode signal corresponding to data with different bit widths, the zero value determination result output port (altb 2) 1134a, (aeqb 2) 1134b and (agtb 2) 1134c are configured to output the determination result of the zero value determination unit 113, the first sign bit output port 1135a is configured to output sign bit data of the received first data, the second sign bit output port 1135b is configured to output sign bit data of the received second data, the first exponent bit output port 1136a is configured to output exponent bit data of the received first data, the second exponent bit output port 1136b is configured to output exponent bit data of the received second data, the first tail bit output port 1137a is configured to output tail bit data of the received first data, the second tail bit output port 1137b is configured to output tail bit data of the received second data, and the logic signal output port 1138 is configured to output a logic signal.

Specifically, the determination results output by the three zero-value determination result output ports (altb 2) 1134a, (aeqb 2) 1134b, and (agtb 2) 1134c may be logic signals, which may be high-level signals or low-level signals. If the judgment result of the zero value judgment unit 113 meets the preset condition, any one of the zero value judgment result output ports (altb 2) 1134a, (aeqb 2) 1134b and (agtb 2) 1134c may output a high level signal, and the other two ports output low level signals, so as to end the operation, which may indicate that at least one zero value exists in the data received by the zero value judgment unit 113, and at this time, the logic signal output port 1138 may output a low level signal. If all three ports output low-level signals, it may indicate that there is no zero value in the data received by the zero-value determining unit 113, and the operation cannot be ended, and the next unit processing is required, and at this time, the zero-value logic signal output port 1138 may output a high-level signal. Optionally, the preset condition corresponding to the zero value determining unit 113 may be whether the received data meets a coding format corresponding to a zero value in the IEEE standard. Optionally, the function selection mode signal input in the zero value judgment unit 113 may be determined according to a user requirement, and may determine a data bit width currently processable by the data comparator according to the input function selection mode signal.

It should be noted that if the data received by the data comparator is a and b, the output high level signal of altb2 can be characterized as a being less than b, the output high level signal of aeqb2 can be characterized as a being equal to b, and the output high level signal of agtb2 can be characterized as a being greater than b. In addition, when the zero-value logic signal output port 1138 outputs a high-level signal, the first sign bit output port 1135a and the second sign bit output port 1135b may input the sign bits of the received first data and the received second data to the sign bit comparing unit 114, respectively, and the sign bit comparing unit 114 may continue to compare the received two data.

In the data comparator provided by this embodiment, the zero-value judging unit may determine, according to the judgment result output by the zero-value judging result output port, whether the data comparator can directly end the operation to output the operation result, and at this time, the data comparator does not need to perform the subsequent operations of other units, so that the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the function selection mode signal input port, and the area of the AI chip occupied by the data comparator is effectively reduced.

In one embodiment, as shown in fig. 7, a specific structural diagram of a data comparator is shown, where the zero value determining unit 113 in the data comparator includes: a first data input port 1131, a second data input port 1132, a function selection mode signal input port (mode) 1133, a first data output port 1134, a second data output port 1135, a zero value determination result output port (altb 2) 1136, (aeqb 2) 1137, and (agtb 2) 1138; the first data input port 1131 is configured to receive the first data, the second data input port 1132 is configured to receive the second data, the function selection mode signal input port (mode) 1133 is configured to receive a function selection mode signal corresponding to data with different bit widths, the first data output port 1134 is configured to output the received first data to an input port of a next unit, the second data output port 1135 is configured to output the received second data to an input port of a next unit, the zero-value determination result output port (altb 2) 1136, (aeqb 2) 1137, and (agtb 2) 1138 are configured to output a determination result of the zero-value determination unit 113.

Specifically, the determination results output by the three zero-value determination result output ports (altb 2) 1136, (aeqb 2) 1137 and (agtb 2) 1138 may be logic signals, which may be high-level signals or low-level signals. If the judgment result of the zero value judging unit 113 meets the preset condition, any one of the zero value judgment result output ports (altb 2) 1136, (aeqb 2) 1137 and (agtb 2) 1138 can output a high level signal, and the other two ports output low level signals, so as to end the operation, which may indicate that at least one zero value exists in the two data received by the zero value judging unit 113. If all three ports output low level signals, it may indicate that zero values do not exist in the two data received by the zero value determining unit 113, and the operation cannot be ended, and the next unit processing is required. Optionally, the preset condition corresponding to the zero value determining unit 113 may be whether the received data meets a coding format corresponding to a zero value in the IEEE standard. Optionally, the function selection mode signal input in the zero value judgment unit 113 may be determined according to a user requirement, and may determine a data bit width currently processable by the data comparator according to the input function selection mode signal.

It should be noted that if the data received by the data comparator is a and b, the output high level signal of altb2 can be characterized as a being less than b, the output high level signal of aeqb2 can be characterized as a being equal to b, and the output high level signal of agtb2 can be characterized as a being greater than b.

In the data comparator provided by this embodiment, the zero-value judging unit can determine whether the data comparator can directly end the operation and output the operation result according to the judgment result output by the zero-value judging result output port, and at this time, the data comparator does not need to perform the subsequent operations of other units, so that the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the function selection mode signal input port, and the area of the AI chip occupied by the data comparator is effectively reduced.

With continuing reference to fig. 4, as shown in fig. 4, a specific structural diagram of a data comparator according to another embodiment is provided, where the comparing circuit 12 in the data comparator further includes: a mantissa bit comparing unit 123, wherein the mantissa bit comparing unit 123 is configured to determine a mantissa bit size of the received data.

Specifically, when the mantissa bit comparing unit 123 processes the received data to obtain a comparison result, the mantissa bit comparing unit 123 may output a high level signal, and at this time, end the operation and output the operation result.

Alternatively, the output terminal of the zero value judging unit 113 may be connected to the input terminal of the mantissa bit comparing unit 123.

In the data comparator provided by this embodiment, the mantissa bit comparing unit determines the size of the mantissa bit of the received data, and if the size of the mantissa bit of the received data can be determined, the mantissa bit comparing unit outputs a high level signal, thereby ending the operation and outputting the operation result; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the comparison circuit, and the area of the AI chip occupied by the data comparator is effectively reduced.

Fig. 8 is a schematic structural diagram of a comparison circuit according to another embodiment, and as shown in fig. 8, the comparison circuit 12 includes: a sign bit comparison unit 121, a exponent bit comparison unit 122 and a mantissa bit comparison unit 123, an output of the sign bit comparison unit 121 being connected to an input of the exponent bit comparison unit 122, an output of the exponent bit comparison unit 122 being connected to an input of the mantissa bit comparison unit 123; the sign bit comparing unit 121 is configured to determine a sign bit size of the received data, the exponent bit comparing unit 122 is configured to determine a exponent bit size of the received data, and the mantissa bit comparing unit 123 is configured to determine a mantissa bit size of the received data.

It should be noted that sign bit comparing unit 121, exponent bit comparing unit 122 and mantissa bit comparing unit 123 sequentially process the received data until one of the comparing units can obtain a comparison result, and the corresponding comparing unit outputs a high level signal, at this time, the operation is finished and the operation result is output. Alternatively, the comparison result may include a sign bit size comparison result of the data, a exponent bit size comparison result of the data, and a mantissa bit size comparison result of the data.

In the data comparator provided by the embodiment, the sign bit comparison unit, the exponent bit comparison unit and the mantissa bit comparison unit sequentially judge the size of the sign bit, the size of the exponent bit and the size of the mantissa bit of received data, if the size of the sign bit, the size of the exponent bit or the size of the mantissa bit of the received data can be determined, the corresponding comparison unit outputs a high-level signal, and at the moment, the operation is finished to output an operation result, the operation of other comparison units is not needed, the operation amount can be reduced, and the operation time is saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the comparison circuit, and the area of the AI chip occupied by the data comparator is effectively reduced.

In one embodiment, as shown in fig. 6, a specific structural diagram of a data comparator is shown, in which the sign bit comparing unit 121 includes: a first sign bit input port 1211, a second sign bit input port 1212, a function selection mode signal input port (mode) 1213, sign bit comparison result output ports (altb 3) 1214a and (agtb 3) 1214b, a sign bit logic signal output port 1215, and a zero value logic signal input port 1216; the first sign bit input port 1211 is configured to receive sign bit data of the first data, the second sign bit input port 1212 is configured to receive sign bit data of the second data, the mode signal input port (mode) 1213 is configured to receive a function selection mode signal corresponding to data with different bit widths, the sign bit comparison result output ports (altb 3) 1214a and (agtb 3) 1214b are configured to output a sign bit size comparison result of the data, the sign bit logic signal output port 1215 is configured to output a logic determination signal, and the zero value logic signal input port 1216 is configured to receive a logic determination signal output by the zero value determining unit 113.

Specifically, the first sign bit input port 1211 and the second sign bit input port 1212 may receive sign bit data of the first data and the second data output by the zero value judging unit 113, respectively.

When the sign bit comparison result output port (altb 3) 1214a or (agtb 3) 1214b outputs a high level signal, it indicates that the next unit is not required to process data and the arithmetic operation result is output after the operation is completed, and at this time, the sign bit logic signal output port 1215 can output a low level signal. Otherwise, when the sign bit comparison result output port (altb 3) 1214a or (agtb 3) 1214b outputs a low level signal, the processing of the next unit is required to be continued, and at this time, the sign bit logic signal output port 1215 may output a high level signal.

In the data comparator provided by this embodiment, the sign bit comparison unit may determine whether the data comparator can directly end the operation and output the operation result according to the comparison result output by the sign bit comparison result output port, and at this time, the data comparator does not need to perform the subsequent operations of other units, so that the operation amount may be reduced, and the operation time may be saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the function selection mode signal input port, and the area of the AI chip occupied by the data comparator is effectively reduced.

In one embodiment, as shown in fig. 7, a specific structural diagram of a data comparator is shown, in which the sign bit comparing unit 121 includes: a first data input port 1211, a second data input port 1212, a function selection mode signal input port (mode) 1213, a first data output port 1214, a second data output port 1215, a sign bit comparison result output port (altb 3) 1216 and (agtb 3) 1217; the first data input port 1211 is configured to receive the first data, the second data input port 1212 is configured to receive the second data, the function selection mode signal input port (mode) 1213 is configured to receive a function selection mode signal corresponding to data with different bit widths to be processed, the first data output port 1214 is configured to output the received first data to an input port of a next unit, the second data output port 1215 is configured to output the received second data to an input port of a next unit, and the sign bit comparison result output ports (altb 3) 1216 and (agtb 3) 1217 are configured to output a sign bit size comparison result of the data.

It should be noted that the function selection mode signal input in the sign bit comparison unit 121 may be determined according to user requirements, and the data bit width currently processable by the data comparator may be determined according to the input function selection mode signal. If the sign bit comparison result output port (altb 3) 1216 or (agtb 3) 1217 outputs a high level signal, it indicates that the next unit does not need to be processed, and the operation result is output after the operation is finished, otherwise, the sign bit comparison result output ports (altb 3) 1216 and (agtb 3) 1217 both output low level signals, and the next unit needs to be processed. Illustratively, if the data comparator receives data a and b, the output high signal of altb3 can be characterized as a being less than b, and the output high signal of agtb3 can be characterized as a being greater than b.

In the data comparator provided by this embodiment, the sign bit comparing unit may determine whether the data comparator can directly end the operation to output the operation result according to the comparison result output by the sign bit comparison result output port, and at this time, the data comparator does not need to perform the subsequent operations of other units, so that the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the function selection mode signal input port, and the area of the AI chip occupied by the data comparator is effectively reduced.

In one embodiment, as shown in fig. 6, a specific structure of a data comparator is shown, in which the exponent comparing unit 122 includes: a first exponent bit input port 1221, a second exponent bit input port 1222, a function selection mode signal input port (mode) 1223, exponent bit comparison result output ports (altb 4) 1224a and (agtb 4) 1224b, an exponent bit logic signal output port 1225, and a sign bit logic signal input port 1226; the first exponent bit input port 1211 is configured to receive exponent bit data of the first data, the second exponent bit input port 1212 is configured to receive exponent bit data of the second data, the function selection mode signal input port (mode) 1223 is configured to receive a function selection mode signal corresponding to data with different bit widths to be processed, the exponent bit comparison result output ports (altb 4) 1224a and (agtb 4) 1224b are configured to output an exponent bit size comparison result of the data, the exponent bit logic signal output port 1225 is configured to output a logic determination signal, and the sign bit logic signal input port 1226 is configured to receive a logic determination signal output by the sign bit comparison unit 121.

Specifically, the first exponent bit input port 1221 and the second exponent bit input port 1222 may receive exponent bit data of the first data and the second data output by the zero value determining unit 113, respectively.

When the exponent bit comparison result output port (altb 4) 1224a or (agtb 4) 1224b outputs a high level signal, it indicates that the next unit does not need to continue processing data and the arithmetic operation is ended, and the exponent bit logic signal output port 1225 can output a low level signal. Otherwise, when the exponent bit comparison result output port (altb 4) 1224a or (agtb 4) 1224b outputs a low level signal, the next unit needs to be processed, and at this time, the exponent bit logic signal output port 1225 can output a high level signal.

In the data comparator provided by the embodiment, the exponent bit comparison unit can determine whether the data comparator can directly end the operation and output the operation result according to the comparison result output by the exponent bit comparison result output port, and at the moment, the data comparator does not need to perform subsequent operations of other units, so that the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the function selection mode signal input port, and the area of the AI chip occupied by the data comparator is effectively reduced.

In one embodiment, as shown in fig. 7, a specific structure of a data comparator is illustrated, in which the exponent bit comparing unit 122 includes: a first data input port 1221, a second data input port 1222, a function selection mode signal input port (mode) 1223, a first data output port 1224, a second data output port 1225, exponent bit comparison result output ports (altb 4) 1226 and (agtb 4) 1227; the first data input port 1221 is configured to receive exponent bit data of the first data, the second data input port 1222 is configured to receive exponent bit data of the second data, the function selection mode signal input port (mode) 1223 is configured to receive a function selection mode signal corresponding to data with different bit widths, the first data output port 1224 is configured to output the received first data to an input port of a next unit, the second data output port 1225 is configured to output the received second data to an input port of the next unit, and the exponent bit comparison result output ports (altb 4) 1226 and (agtb 4) 1227 are configured to output exponent bit size comparison results of the data.

It should be noted that the function selection mode signal input in the exponent bit comparing unit 122 may be determined according to the user requirement, and the data bit width currently processable by the data comparator may be determined according to the input function selection mode signal. If the exponent bit comparison result output port (altb 4) 1224 or (agtb 4) 1225 outputs a high level signal, it indicates that the next unit does not need to be processed, and the operation is ended to output the operation result, otherwise, the exponent bit comparison result output ports (altb 4) 1224 and (agtb 4) 1225 both output low level signals, and the next unit needs to be processed. Illustratively, if the data comparator receives data as a and b, the output high signal of altb4 may be characterized as a less than b and the output high signal of agtb4 may be characterized as a greater than b.

In the data comparator provided by the embodiment, the exponent bit comparing unit can determine whether the data comparator can directly end the operation and output the operation result according to the comparison result output by the exponent bit comparison result output port, and at this time, the data comparator does not need to perform subsequent operations of other units, so that the operation amount can be reduced, and the operation time can be saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the function selection mode signal input port, and the area of the AI chip occupied by the data comparator is effectively reduced.

In one embodiment, as shown in fig. 6, a specific structure of a data comparator is shown, in which the mantissa bit comparing unit 123 includes: a first mantissa bit input port 1231, a second mantissa bit input port 1232, a function selection mode signal input port (mode) 1233, mantissa bit comparison result output ports (altb 5) 1234a, (agtb 5) 1234b, and (aeqb 5) 1234c, an exponent bit logic signal input port 1235; the first mantissa bit input port 1231 is configured to receive mantissa bit data of the first data, the second mantissa bit input port 1232 is configured to receive mantissa bit data of the second data, the function selection mode signal input port (mode) 1233 is configured to receive a function selection mode signal corresponding to data with different bit widths to be processed, the mantissa bit comparison result output ports (altb 5) 1234a and (agtb 5) 1234b are configured to output mantissa bit size comparison results of the data, and the exponent bit logic signal input port 1235 is configured to receive a logic determination signal output by the exponent bit comparison unit 122.

Specifically, the first mantissa bit input port 1231 and the second mantissa bit input port 1232 may receive exponent bit data of the first data and the second data output by the zero value determination unit 113, respectively.

Note that, when the mantissa logic signal input port (altb 5) 1234a or (agtb 5) 1234b outputs a high level signal, the operation output result is finished, and at this time, the exponent logic signal input port 1235 can receive a high level signal.

In the data comparator provided by this embodiment, the mantissa bit comparing unit may determine whether the data comparator can directly end the operation to output the operation result according to the comparison result output by the mantissa bit comparison result output port, and at this time, the data comparator does not need to perform the subsequent operations of other units, so that the operation amount may be reduced, and the operation time may be saved; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the function selection mode signal input port, and the area of the AI chip occupied by the data comparator is effectively reduced.

In one embodiment, as shown in fig. 7, a specific structure of a data comparator is shown, in which the mantissa bit comparing unit 123 includes: a first data input port 1231, a second data input port 1232, a function selection mode signal input port (mode) 1233, a mantissa bit comparison result output port (altb 5) 1234, (agtb 5) 1235, and (aegb 5) 1236; the first data input port 1231 is configured to receive the first data, the second data input port 1232 is configured to receive the second data, the function selection mode signal input port (mode) 1233 is configured to receive a function selection mode signal corresponding to data with different bit widths to be processed, and the mantissa bit comparison result output ports (altb 5) 1234, (agtb 5) 1235 and (aegb 5) 1236 are configured to output a mantissa bit size comparison result of the data.

It should be noted that the function selection mode signal input in the mantissa bit comparing unit 123 may be determined according to a user requirement, and a data bit width currently processable by the data comparator may be determined according to the input function selection mode signal. If the mantissa bit comparison result output port (altb 5) 1234, (agtb 5) 1235 or (aegb 5) 1236 outputs a high level signal, the operation is ended and the operation result is output. Illustratively, if the data comparator receives data a and b, the altb5 output high signal may be characterized as a being less than b, the aeqb5 output high signal may be characterized as a being equal to b, and the agtb5 output high signal may be characterized as a being greater than b. Meanwhile, if no high level signal is output from all the judgment result output ports of the judgment units, the sign bit comparison unit 121 and the exponent bit comparison unit 122, then there is inevitably one port capable of outputting a high level signal from the three comparison result output ports corresponding to the mantissa bit comparison unit 123.

In the data comparator provided by this embodiment, the mantissa bit comparing unit may output the comparison result according to the mantissa bit comparison result output port, thereby ending the operation and outputting the operation result; in addition, the data comparator can process various data operations with different bit widths according to different function selection mode signals received by the function selection mode signal input port, and the area of the AI chip occupied by the data comparator is effectively reduced.

Fig. 9 is a flowchart illustrating a data processing method according to an embodiment, where the method can be processed by the data comparator shown in fig. 1 and fig. 2, and this embodiment relates to a process of performing a comparison operation on data. As shown in fig. 9, the method includes:

s101, receiving data to be processed.

In particular, the data comparator may receive two data to be processed. Optionally, the data comparator inputs the received data to be processed to the judging circuit, and if the data to be processed needs to be processed by the comparing circuit after the operation of the judging circuit is finished, the judging circuit inputs the received data to be processed to the comparing circuit for performing the comparison operation on the data to be processed. Optionally, the data comparator may further receive different function selection mode signals through each of the determination units in the determination circuit and each of the comparison units in the comparison circuit at the same time, and when performing the same operation, the function selection mode signals received by each of the determination units in the determination circuit and each of the comparison units in the comparison circuit may be the same. If the data comparator receives different function selection mode signals, the data comparator can process data with different corresponding bit widths, and meanwhile, the corresponding relationship between the different selection mode signals and the data comparator, which can process the data with different bit widths, can be flexibly set, and the embodiment is not limited at all. Optionally, the data may be floating point numbers.

Illustratively, if the determination circuit and the comparison circuit can receive a plurality of function selection mode signals, taking three function selection mode signals as an example, mode =0, mode =1, and mode =2, respectively, mode =0 may indicate that the data comparator can process 16-bit data, mode =1 may indicate that the data comparator can process 32-bit data, mode =2 may indicate that the data comparator can process 64-bit data, mode =0 may indicate that the data comparator can process 64-bit data, mode =1 may indicate that the data comparator can process 16-bit data, and mode =2 may indicate that the data comparator can process 32-bit data.

It should be noted that, if the bit width of the to-be-processed data received by the determining circuit is not equal to the bit width of the processable data corresponding to the function selection mode signal received by the data comparator, the data comparator divides the received to-be-processed data into a plurality of groups of data having the same bit width as the currently processable data of the data comparator according to the current processable data bit width of the data comparator, and performs parallel processing, where the bit width of the to-be-processed data received by the determining circuit may be greater than the current processable data bit width of the data comparator. Optionally, the parallel processing may be characterized in that each group of data to be processed is processed at the same time. If the bit width of the data to be processed received by the circuit is judged to be equal to the bit width of the data which can be processed and corresponds to the function selection mode signal received by the data comparator, the data comparator directly processes the received data to be processed.

S102, judging whether the data to be processed needs to be processed through a comparison circuit through a judgment circuit.

Specifically, the data comparator may determine whether the data to be processed needs to be processed by the comparison circuit according to the determination result output by the determination circuit.

S103, if necessary, the judging circuit respectively inputs the sign bit, the exponent bit and the mantissa bit of the data to be processed into the comparing circuit, the comparing circuit compares the magnitude of the sign bit, the exponent bit and the mantissa bit of the data to be processed, and an operation result is output.

Specifically, if there is no non-numerical value, infinite number or zero value in the data to be processed, the sign bit, exponent bit and mantissa bit of the data to be processed may be respectively input to the comparison circuit after the data to be processed is processed by the determination circuit, the magnitude of the sign bit, exponent bit and mantissa bit of the data to be processed is sequentially compared by each comparison unit in the comparison circuit, the comparison unit outputs a high level signal according to any one of the comparison results output by the sign bit comparison result output port, the exponent bit comparison result output port and/or the mantissa bit comparison result output port, and outputs the maximum data and the minimum data in the received data to be processed through the maximum value output port (Zmax) and the minimum value output port (Zmin) of the data comparator, thereby ending the operation.

For example, if two pieces of data a and b to be processed with 32 bits are input, the current data comparator may perform a data comparison operation with 16 bits to be processed, and the data comparator divides the input two pieces of data to be processed with 32 bits into two sets of data to be processed with 16 bits, respectively, the maximum value output port (Zmax) and the minimum value output port (Zmin) are obtained by concatenating the data to be processed with 16 bits, which are higher and lower, respectively, according to a formula Zmax = { max { a [31], b [31 ]:16 ] }, max { a [ 15. If the data bit width which can be processed currently by the data comparator is equal to the received data bit width to be processed by 32, the high-low 16-bit data of the maximum value and the minimum value of the 32-bit output by the maximum value output port (Zmax) and the minimum value output port (Zmin) are the high-low 16-bit data of the same data to be processed.

Optionally, after the step of determining, by the determining circuit, whether the data to be processed needs to be processed by the comparing circuit, the method may further include: if necessary, the judging circuit respectively inputs the data to be processed into the comparing circuit, compares the sign bit, the exponent bit and the mantissa bit of the data to be processed through the comparing circuit, and outputs an operation result.

In the data comparator provided by this embodiment, the data comparator determines, by the determination circuit, whether the data to be processed needs to be processed by the comparison circuit, so as to reduce the amount of computation and save the computation time; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

Another embodiment provides a data processing method. In the above S102, the determining, by the determining circuit, whether the data to be processed needs to be processed by the comparing circuit includes: judging whether a non-numerical value, an infinite number or a zero value exists in the data to be processed through the judging circuit; if the data to be processed does not have a non-numerical value, an infinite number and a zero value, it is determined that the data to be processed needs to be processed through the comparison circuit.

It should be noted that, based on the encoding standard corresponding to the non-numerical value, the infinite number, and the zero value in the IEEE data arithmetic standard, if the non-numerical value, the infinite number, and the zero value do not exist in the to-be-processed data received by the judgment circuit, it may be judged that the to-be-processed data needs to be further processed by the comparison circuit; if the data to be processed received by the judgment circuit has a non-numerical value, an infinite number or a zero value, the judgment result of the judgment circuit is yes, and the output port of the judgment result can output a high-level signal to finish the operation. In this embodiment, a high level signal may be represented by 1, and a low level signal may be represented by 0.

For example, if two pieces of data to be processed, a and b, of 32 bits are input, and the current data comparator can perform a comparison operation on 16 bits of data, the data comparator will divide the two pieces of input 32 bits of data to be processed into two sets of data to be processed, which can be represented as a [31] and a [15], and b [31] and b [15] respectively, and therefore, the data comparator will simultaneously process the two sets of data to be processed, a [31] and b [31], and a [15] and b [15] by the determining unit, and obtain whether there are non-numerical values, infinity numbers, and zero values in the two sets of data to be processed, that is, the data to be processed, of a [31] and b [31], respectively.

In the data comparator provided by this embodiment, the data comparator determines whether the data to be processed has a non-numerical value, an infinite number, and a zero value through the determination circuit, and determines whether to input the comparison circuit for processing according to the determination result, so as to reduce the amount of computation and save the computation time; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of an AI chip occupied by the data comparator is effectively reduced.

Fig. 10 is a schematic flow chart of a data processing method provided by another embodiment, where the determining circuit in S102 determines whether a non-numerical value, an infinite number, or a zero value exists in the data to be processed, which may be implemented by the following method, as shown in fig. 10, specifically including:

and S1021, judging whether the data to be processed has a non-numerical value through a non-numerical value judging unit.

Specifically, the data comparator determines whether a non-numerical value exists in the received data to be processed through the non-numerical value determining unit based on a coding standard corresponding to the non-numerical value in the IEEE data arithmetic standard.

And S1022, if no non-numerical value exists, inputting the data to be processed into an infinite number judgment unit, and judging whether infinite numbers exist in the data to be processed through the infinite number judgment unit.

Specifically, if no non-numerical value exists in the data to be processed received by the non-numerical value judging unit, the non-numerical value judging unit outputs the received data to be processed to the infinity judging unit, and based on a coding standard corresponding to the infinity in the IEEE data arithmetic standard, the infinity judging unit continues to judge whether the infinity exists in the received data to be processed.

And S1023, if the infinite number does not exist, inputting the data to be processed into a zero value judging unit, and judging whether the zero value exists in the data to be processed or not through the zero value judging unit.

Specifically, if the infinity exists in the to-be-processed data received by the infinity determining unit, the infinity determining unit outputs the received to-be-processed data to the zero value determining unit, and based on the coding standard corresponding to the zero value in the IEEE data arithmetic standard, the zero value determining unit continues to determine whether the zero value exists in the received to-be-processed data.

And S1024, if no zero value exists, judging that the data needs to be processed through the comparison circuit.

Specifically, if the to-be-processed data received by the zero value determining unit does not have a zero value, the zero value determining unit may output the received to-be-processed data to the comparing circuit for processing.

Optionally, in the above S102, the determining circuit determines whether the data to be processed has a non-numerical value, an infinite number, or a zero value, and may also be implemented by the following method, as shown in fig. 11, specifically including:

s1025, judging whether the data to be processed has infinite numbers through an infinite number judging unit.

And S1026, if the infinite number does not exist, inputting the data to be processed into a non-numerical value judging unit, and judging whether a non-numerical value exists in the data to be processed through the non-numerical value judging unit.

S1027, if there is no non-numerical value, inputting the data to be processed to a zero value judging unit, and judging whether there is a zero value in the data to be processed by the zero value judging unit.

And S1028, if no zero value exists, judging that the data need to be processed through the comparison circuit.

In the data comparator provided in this embodiment, the data comparator sequentially determines whether a non-numerical value, an infinite number, or a zero value exists in the data to be processed, and determines whether the data to be processed needs to be input into the comparison circuit for comparison according to a determination result, so as to reduce the amount of computation and save the computation time; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

In another embodiment of the data processing method, after the determining whether the data to be processed has the non-numerical value by the non-numerical value determining unit in the step S1021, the method further includes: if the non-numerical value exists, outputting a first operation result and finishing the operation.

Specifically, if at least one non-numerical value is in the data to be processed received by the non-numerical value determining unit, the non-numerical value determining unit may directly output a first operation result through an output port (unordered) of the non-numerical value determining result, and end the comparison operation, where the first operation result is a high level signal. At this time, it is described that there is a non-numerical value in the received data to be processed, and the numerical value comparison cannot be performed, and the operation is ended.

In the data comparator provided by this embodiment, if at least one non-value exists in the received data to be processed, the non-value determining unit directly outputs the high level signal without continuing to perform the operation of other units, so as to reduce the operation amount and save the operation time; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

Another embodiment provides a data processing method, in which, in the above S1021, the data to be processed is input to an infinite number judging unit, and after the infinite number judging unit judges whether an infinite number exists in the data to be processed, the method further includes: and if the infinite number exists, outputting a second operation result and finishing the operation.

Specifically, if there is an infinite number in the data to be processed received by the infinite number determining unit, the infinite number determining unit may directly output the second operation result through any one of the infinite number determination result output ports (altb 1), (aeqb 1), and (agtb 1), and output the maximum data and the minimum data in the received data to be processed through the maximum value output port (Zmax) and the minimum value output port (Zmin) of the data comparator, and end the comparison operation, where the second operation result is a high level signal.

Illustratively, if two input data to be processed are a and b, when the infinite number judgment result output port (altb 1) outputs a high level signal, it indicates that a < b, and at this time, data b is output through the maximum value output port (Zmax) of the data comparator, and data a to be processed is output through the minimum value output port (Zmin).

It should be noted that, if the two pieces of data to be processed received by the infinity judgment unit are both infinity numbers and sign bits of the two infinity numbers are the same, the infinity judgment unit outputs a second operation result through the infinity judgment result output port (aeqb 1), and ends the operation, where the second operation result is a high level signal. If one of the two pieces of data to be processed received by the infinite number judging unit is infinite and the other piece of data to be processed is not infinite, judging the size of the two pieces of data to be processed according to the sign bit.

Illustratively, if two input data to be processed are a and b, a is an infinite number, the sign bit is 0 (i.e. representing positive infinity), and b is not an infinite number, then a > b is illustrated, at this time, the infinite number judgment unit outputs the second operation result through the infinite number judgment result output port (agtb 1), and the comparison operation is ended. If the two input data to be processed are a and b, a is an infinite number, the sign bit is 1 (namely, negative infinite), and b is not an infinite number, it indicates that a < b, at this time, the infinite number judgment unit outputs a second operation result through the infinite number judgment result output port (altb 1), and the comparison operation is ended.

In the data comparator provided by this embodiment, if there is an infinite number in the received data to be processed, the infinite number determining unit directly outputs a high level signal without continuing to perform operations on other units, so that the amount of operations is reduced, and the operation time is saved; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

Another embodiment provides a data processing method, in the above S1023, after the data to be processed is input to a zero value judgment unit, and the zero value judgment unit judges whether a zero value exists in the data to be processed, the method further includes: if the zero value exists, outputting a third operation result and finishing the operation.

Specifically, if the data to be processed received by the zero value determining unit has a zero value, the zero value determining unit may directly output the third operation result through any one of the zero value determining result output ports (altb 2), (aeqb 2), and (agtb 2), and output the maximum data and the minimum data in the received data to be processed through the maximum value output port (Zmax) and the minimum value output port (Zmin) of the data comparator, thereby ending the comparison operation. Wherein the third operation result is a high level signal.

It should be noted that, if the two to-be-processed data received by the zero value determining unit are both zero values, the zero value determining unit outputs a third operation result through the zero value determining result output port (aeqb 2), and ends the operation, where the third operation result is a high level signal. If one of the two pieces of data to be processed received by the zero value judging unit is a zero value, judging the size of the two pieces of data to be processed according to the sign bit of the other piece of data to be processed.

Illustratively, if the input data to be processed are a and b, a is a zero value, b is not a zero value, and the sign bit of b is 0 (i.e., b is a positive number), the zero value determination unit outputs a third operation result through the zero value determination result output port (altb 2) to end the operation, and if the sign bit of b is 1 (i.e., b is a negative number), the zero value determination unit outputs the third operation result through the zero value determination result output port (agtb 2) to end the operation.

In the data comparator provided by this embodiment, if the data to be processed received by the data comparator has a zero value, the zero value judgment unit directly outputs the high level signal without continuing the operation of other units, so that the operation amount is reduced, and the operation time is saved; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

Fig. 12 is a schematic flow chart of a data processing method according to another embodiment, where in the above S103, the determining circuit respectively inputs the sign bit, the exponent bit, and the mantissa bit of the data to be processed into the comparing circuit, and the comparing circuit compares the magnitudes of the sign bit, the exponent bit, and the mantissa bit of the data to be processed to output the operation result, which may be implemented by the following method, as shown in fig. 12, specifically including:

and S1031, judging whether the sign bits of the received data to be processed are equal through a sign bit comparison unit.

Specifically, the sign bit of the data to be processed may be represented by 0 or 1, where 0 represents that the data is a positive number, and 1 represents that the data is a negative number. It should be noted that, when the zero-value judgment result output port and the infinity judgment result output port both output low-level signals, the data comparator may input the data to be processed to the sign bit comparison unit for processing through the zero-value judgment unit or the infinity judgment unit.

S1032, if the sign bits of the data to be processed are equal, inputting the exponent bits of the data to be processed into an exponent bit comparison unit, and judging whether the exponent bits of the data to be processed are equal through the exponent bit comparison unit.

Specifically, if the sign bits of the received data to be processed are equal, the exponent bits of the data to be processed are input to the exponent bit comparison unit, and whether the exponent bits of the data to be processed are equal or not is continuously judged through the exponent bit comparison unit.

It should be noted that, when the sign bit comparison result output port does not output a high level signal, the data comparator may input the exponent bit of the data to be processed to the exponent bit comparison unit through the sign bit comparison unit.

S1033, if the exponent bits of the data to be processed are equal, inputting the mantissa bits of the data to be processed to a mantissa bit comparing unit, and determining whether the mantissa bits of the data to be processed are equal through the mantissa bit comparing unit.

Specifically, if the exponent bits of the received data to be processed are equal, the mantissa bits of the data to be processed are input to the mantissa bit comparison unit, and whether the mantissa bits of the data to be processed are equal or not is continuously judged through the mantissa bit comparison unit.

It should be noted that, when the exponent bit comparison result output port does not output a high level signal, the data comparator may input the mantissa bit of the data to be processed to the mantissa bit comparison unit through the exponent bit comparison unit.

S1034, if the mantissa bits of the data to be processed are equal, outputting a fourth operation result, and ending the operation.

Specifically, if the mantissa bits of the received data to be processed are equal, the mantissa bit comparing unit outputs a fourth operation result through the mantissa bit comparison result output port (aegb 5), and outputs the maximum data and the minimum data of the received data to be processed through the maximum value output port (Zmax) and the minimum value output port (Zmin) of the data comparator, and ends the comparison operation, wherein the fourth operation result is a high level signal.

In the data comparator provided by the embodiment, the sign bit, the exponent bit and the mantissa bit of the received data to be processed are sequentially compared by the data comparator, so that the operation amount is reduced, and the operation time is saved; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

Optionally, as shown in fig. 13, the above-mentioned inputting the data to be processed into the comparison circuit through the judgment circuit, comparing the magnitude of the sign bit, the exponent bit and the mantissa bit of the data to be processed through the comparison circuit, and outputting the operation result may also be implemented through the following method, as shown in fig. 13, specifically including:

s1035, determining whether sign bits of the received data to be processed are equal by the sign bit comparing unit.

S1036, if sign bits of the data to be processed are equal, inputting the data to be processed to an exponent bit comparing unit, and determining whether exponent bits of the data to be processed are equal through the exponent bit comparing unit.

Specifically, if the sign bits of the received data to be processed are equal, the data to be processed is input to the exponent bit comparison unit, and whether the exponent bits of the data to be processed are equal or not is continuously judged through the exponent bit comparison unit.

It should be noted that, when the sign bit comparison result output port does not output a high level signal, the data comparator may input data to be processed to the exponent bit comparison unit through the sign bit comparison unit.

S1037, if the exponent bits of the data to be processed are equal, inputting the data to be processed to a mantissa bit comparing unit, and determining whether the mantissa bits of the data to be processed are equal by the mantissa bit comparing unit.

Specifically, if the exponent bits of the received data to be processed are equal, the data to be processed is input to the mantissa bit comparison unit, and whether the mantissa bits of the data to be processed are equal or not is continuously judged through the mantissa bit comparison unit.

It should be noted that, when the exponent bit comparison result output port does not output a high level signal, the data comparator may input data to be processed to the mantissa bit comparison unit through the exponent bit comparison unit.

And S1038, if mantissa bits of the data to be processed are equal, outputting a fourth operation result, and ending the operation.

In another embodiment of the flowchart of the data processing method, in the above S103, the determining circuit respectively inputs the sign bit, the exponent bit and the mantissa bit of the data to be processed into the comparing circuit, and the comparing circuit compares the magnitudes of the sign bit, the exponent bit and the mantissa bit of the data to be processed to output the operation result, which may be implemented by the following method, specifically including: and performing OR logic operation on the judging circuit and an output port corresponding to each unit in the comparison circuit, and outputting an operation result.

Specifically, if the data comparator processes data in a parallel processing manner, the data to be processed may be processed through each judgment unit in the judgment circuit and each comparison unit in the comparison circuit, and the output ports unordered, altb, agtb, and aeqb corresponding to each unit in the judgment circuit and the comparison circuit are subjected to or logic operation, respectively, so as to output an operation result.

According to the data comparator provided by the embodiment, the data comparator performs parallel processing on the received data to be processed, so that the complexity of operation can be reduced, and the operation time can be saved; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

In another embodiment of the data processing method, after the sign bit comparing unit determines whether the sign bits of the received to-be-processed data are equal in S1031, the method further includes: and if the sign bits of the data to be processed are not equal, outputting a fifth operation result and finishing the operation.

Specifically, if the sign bits of the two pieces of data to be processed received by the sign bit comparing unit are not equal, the positive number is greater than the negative number. Illustratively, if two input data are a and b, the sign bit of a is 0, and the sign bit of b is 1, then a > b is indicated, at this time, the sign bit comparison unit outputs a fifth operation result through the sign bit comparison result output port (agtb 3), and outputs the maximum data and the minimum data in the received data to be processed through the maximum value output port (Zmax) and the minimum value output port (Zmin) of the data comparator, and ends the comparison operation, wherein the fifth operation result is a high level signal.

In the data comparator provided by this embodiment, if the sign bits of the received data to be processed are not equal, the sign bit comparison unit directly outputs a high level signal, and the data to be processed does not need to be processed continuously through other units, so that the operation amount is reduced, and the operation time is saved; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

Another embodiment provides a data processing method, in S1032, after the exponent bits of the data to be processed are input to the exponent bit comparing unit, and the exponent bit comparing unit determines whether the exponent bits of the data to be processed are equal, the method further includes: and if the exponent bits of the data to be processed are not equal, outputting a sixth operation result and finishing the operation.

It should be noted that, when the exponent bits of the two pieces of data to be processed received by the exponent bit comparing unit are not equal, the larger the exponent bit is for a positive number, the larger the value is, and for a negative number, the larger the exponent bit is, the smaller the value is. Illustratively, if two input data are a and b, the sign bits of a and b are both 1, and the exponent bit of a is greater than the exponent bit of b, then a < b is indicated, and at this time, the exponent bit comparison unit outputs a sixth operation result through an exponent bit comparison result output port (altb 4), and the operation is ended; if the sign bits of a and b are both 0 and the exponent bit of a is greater than the exponent bit of b, a > b is indicated, at this time, the exponent bit comparison unit outputs a sixth operation result through an exponent bit comparison result output port (agtb 4), and outputs the maximum data and the minimum data in the received data to be processed through a maximum value output port (Zmax) and a minimum value output port (Zmin) of the data comparator, and the comparison operation is finished, wherein the sixth operation result is a high level signal.

In the data comparator provided by the embodiment, if the exponent bits of the received data to be processed are not equal, the exponent bit comparing unit directly outputs a high level signal, and the data to be processed does not need to be processed continuously through other units, so that the operation amount is reduced, and the operation time is saved; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of an AI chip occupied by the data comparator is effectively reduced.

Optionally, after the data to be processed is input to the exponent bit comparing unit in S1036, and the exponent bit comparing unit determines whether the exponent bits of the data to be processed are equal, the method further includes: and if the exponent bits of the data to be processed are not equal, outputting a sixth operation result and finishing the operation.

In one embodiment, as shown in fig. 14, the exponent bit comparing unit in S1036 determines whether exponent bits of the data to be processed are equal, which may be implemented by the following method, as shown in fig. 14, including:

s1036a, dividing exponent bits of the data to be processed into a first exponent bit and a second exponent bit, and determining whether the first exponent bits are equal.

Specifically, by comprehensively considering the exponent bits and mantissa bit widths of different bit widths of data specified by the IEEE data arithmetic standard, the bit width of data to be processed, and the data bit width processable by the data comparator, the exponent bits of the data to be processed can be divided into two parts, which are the first exponent bit and the second exponent bit, respectively. Alternatively, the first exponent bit may be a first half of the exponent bit, and the second exponent bit may be a second half of the exponent bit.

Illustratively, based on the IEEE data arithmetic standard, the sign bit may be 1-bit wide, the exponent bit may be 8-bit wide, and the mantissa bit may be 23-bit wide in the prescribed 32-bit data. Wherein a [30 ]. In addition, based on the IEEE data arithmetic standard, the exponent bit and the mantissa bit of 32-bit data are divided according to the method, the bit width rule of the exponent bit and the mantissa bit of 32-bit data and 16-bit data is mainly considered, and the 32-bit data can be divided into high-level and low-level 16-bit data for comparison processing.

S1036b, if the first exponent bits of the data exponent bits to be processed are equal, determining whether the second exponent bits are equal.

It should be noted that, when performing comparison operation on exponent bits of 32-bit data or 16-bit data, the first half of the exponent bits may be compared first, and if the first half of the data exponent bits are not equal in size, the size relationship between the two data may be directly determined, and the operation is ended.

S1036c, if the second exponent bits of the data to be processed are equal, continuing to determine whether the mantissa bits of the data to be processed are equal through the mantissa bit comparing unit.

Specifically, if the second exponent bits of the data are also equal after the comparison is completed, the comparison of the mantissa bits of the data may be continued.

In the data comparator provided by this embodiment, if the exponent bits of the received data to be processed are not equal, the exponent bit comparing unit directly outputs a high level signal, and the data to be processed does not need to be processed continuously by other units, so that the computation amount is reduced, and the computation time is saved; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

Another embodiment provides a flow chart of a data processing method, wherein in the above S1033, the method further includes, after inputting mantissa bits of the data to be processed into the mantissa bit comparing unit, and determining whether mantissa bits of the data to be processed are equal by the mantissa bit comparing unit, further including: and if the mantissa bits of the data to be processed are not equal, outputting a seventh operation result and finishing the operation.

It should be noted that, if mantissa bits of two data to be processed received by the mantissa bit comparing unit are not equal, for a positive number, the larger the mantissa bit is, the larger the value is, and for a negative number, the larger the mantissa bit is, the smaller the value is. Illustratively, if two input data to be processed are a and b, the sign bits of a and b are both 1, and the mantissa bit of a is greater than the mantissa bit of b, it indicates that a < b, and at this time, the mantissa bit comparison unit outputs a sixth operation result through a mantissa bit comparison result output port (altb 5), and the operation is ended; if the sign bits of a and b are both 0 and the mantissa bit of a is greater than the mantissa bit of b, a > b is indicated, at this time, the mantissa bit comparison unit outputs a seventh operation result through the mantissa bit comparison result output port (agtb 5), and outputs the maximum data and the minimum data in the received data to be processed through the maximum value output port (Zmax) and the minimum value output port (Zmin) of the data comparator, and the comparison operation is finished, wherein the seventh operation result is a high level signal.

In the data comparator provided by the embodiment, if the mantissa bits of the received data to be processed are not equal, the mantissa bit comparing unit directly outputs a high level signal without continuously processing the data to be processed through other units, so that the operation amount is reduced, and the operation time is saved; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of an AI chip occupied by the data comparator is effectively reduced.

Optionally, in S1037, after the data to be processed is input to the mantissa bit comparing unit, and whether mantissa bits of the data to be processed are equal is determined by the mantissa bit comparing unit, the method further includes: and if the mantissa bits of the data to be processed are not equal, outputting a seventh operation result and finishing the operation.

In the data comparator provided by this embodiment, if the mantissa bits of the received data to be processed are not equal, the mantissa bit comparing unit may output a high level signal, thereby ending the operation and outputting the operation result; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

In one embodiment, as shown in fig. 15, the mantissa bit comparing unit in S1037 may determine whether mantissa bits of the data to be processed are equal, and may be implemented by the following method, as shown in fig. 15, including:

s1037a, dividing mantissa bits of the data to be processed into a first mantissa bit and a second mantissa bit, and determining whether the first mantissa bits are equal.

S1037b, if the first mantissa bits of the exponent bits of the data to be processed are equal, determining whether the second mantissa bits are equal.

It should be noted that the way of comparing mantissa bits may be similar to that of comparing exponent bits, and will not be described herein.

Fig. 16 is a flowchart illustrating a data processing method according to an embodiment, where the method can be processed by the data comparator shown in fig. 2 and fig. 7, and this embodiment relates to a process of performing a comparison operation on data. As shown in fig. 16, the method includes:

s201, receiving data to be processed.

S202, judging whether the data to be processed needs to be processed through a comparison circuit through a judgment circuit.

S203, if necessary, the judging circuit inputs the data to be processed into the comparing circuit, the comparing circuit compares the sign bit, exponent bit and mantissa bit of the data to be processed, and an operation result is output.

Specifically, if the data to be processed does not have a non-numerical value, an infinite number or a zero value, the data to be processed or sign bit data of the data to be processed is input into the comparison circuit after being processed by the judgment circuit, the sign bit, the exponent bit and the mantissa bit of the data to be processed are sequentially compared by the comparison circuit, the comparison unit outputs a high level signal according to a comparison result of the sign bit, the exponent bit and the mantissa bit of the data, and outputs the maximum data and the minimum data in the received data to be processed through a maximum numerical output port (Zmax) and a minimum numerical output port (Zmin) of the data comparator, thereby finishing the operation.

For example, if two pieces of data a and b to be processed with 32 bits are input, the current data comparator may perform a data comparison operation with 16 bits to be processed, and the data comparator correspondingly divides the two pieces of data to be processed with 32 bits into two sets of data to be processed with 16 bits according to 16 bits, the values output by the maximum value output port (Zmax) and the minimum value output port (Zmin) are obtained by respectively comparing the maximum value and the minimum value of the data to be processed with 16 bits, and then concatenating the data to be processed with 16 bits, that is, the maximum value is obtained by the following formula Zmax = { max { a [31 ]. If the data bit width which can be processed currently by the data comparator is equal to the received data bit width to be processed by 32, the high-low 16-bit data of the maximum value and the minimum value of the 32-bit output by the maximum value output port (Zmax) and the minimum value output port (Zmin) are the high-low 16-bit data of the same data to be processed.

In the data processing method provided by this embodiment, the data comparator determines, by the determination circuit, whether the data to be processed needs to be processed by the comparison circuit, so as to reduce the amount of computation and save the computation time; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of an AI chip occupied by the data comparator is effectively reduced.

Another embodiment provides a data processing method. In the above S202, the determining, by the determining circuit, whether the data to be processed needs to be processed by the comparing circuit includes: judging whether a non-numerical value, an infinite number or a zero value exists in the data to be processed through the judging circuit; and if no zero value exists, judging that the data needs to be processed through the comparison circuit.

It should be noted that, based on the encoding standard corresponding to the non-numerical value, the infinite number, and the zero value in the IEEE data arithmetic standard, if the non-numerical value, the infinite number, or the zero value does not exist in the to-be-processed data received by the judgment circuit, it may be judged that the to-be-processed data needs to be further processed by the comparison circuit; if the data to be processed received by the judging circuit has a non-numerical value, an infinite number or a zero value, the judging result of the judging circuit is yes, a high-level signal is output, and the operation is finished. In the present embodiment, the high level signal may be represented by 1.

Illustratively, if two to-be-processed data a and b with 32 bits are input, and the current data comparator can perform a 16-bit data comparison operation, the data comparator will divide the input two 32-bit to-be-processed data into two sets of 16-bit to-be-processed data according to 16-bit correspondence, which can be represented as a [31] and a [15] and b [31] and b [ 15.

In the data processing method provided by this embodiment, the data comparator determines whether a non-numerical value, an infinite number, or a zero value exists in the data to be processed, and determines whether to input the data to the comparison circuit for processing according to the determination result, so as to reduce the amount of computation and save the computation time; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

In another embodiment of the data processing method, after the determining, by the non-numerical value determining unit in the step S2021, whether a non-numerical value exists in the data to be processed, the method further includes: if the non-numerical value exists, outputting a first operation result and finishing the operation.

Specifically, if at least one non-numerical value is included in the to-be-processed data received by the non-numerical value determining unit, the non-numerical value determining unit may directly output a first operation result through a determination result output port (unordered), and end the comparison operation, where the first operation result is a high level signal. At this time, it is described that there is a non-numerical value in the received data to be processed, and the numerical value comparison cannot be performed, and the operation is ended.

In the data processing method provided by this embodiment, if at least one non-numerical value exists in the received data to be processed by the data comparator, the non-numerical value determining unit directly outputs a high level signal without continuing the operation of other units, thereby reducing the operation amount and saving the operation time; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

Another embodiment provides a data processing method, in which, in the above S2021, after the data to be processed is input to an infinite number judging unit, and whether an infinite number exists in the data to be processed is judged by the infinite number judging unit, the method further includes: and if the infinite number exists, outputting a second operation result and finishing the operation.

Specifically, if there is an infinite number in the data to be processed received by the infinite number judgment unit, the infinite number judgment unit may directly output the second operation result through the judgment result output ports (altb 1), (aeqb 1) and (agtb 1), and output the maximum data and the minimum data in the received data to be processed through the maximum value output port (Zmax) and the minimum value output port (Zmin) of the data comparator, and end the comparison operation, where the second operation result is a high level signal.

Illustratively, if the two input data to be processed are a and b, when the output port (altb 1) outputs a high level signal, it indicates that a < b, and at this time, data b is output through the maximum value output port (Zmax) of the data comparator and data a to be processed is output through the minimum value output port (Zmin).

It should be noted that, if the two pieces of data to be processed received by the infinity judgment unit are both infinity numbers and sign bits of the two infinity numbers are the same, the infinity judgment unit outputs a second operation result through the judgment result output port (aeqb 1), and ends the operation, where the second operation result is a high level signal. If one of the two pieces of data to be processed received by the infinite number judging unit is infinite and the other piece of data to be processed is not infinite, judging the size of the two pieces of data to be processed according to the sign bit.

Illustratively, if two input data to be processed are a and b, a is an infinite number, the sign bit is 0 (i.e. representing positive infinity), and b is not an infinite number, then a > b is illustrated, and at this time, the infinite number judgment unit outputs the second operation result through the judgment result output port (agtb 1), and the comparison operation is ended. If the two input data to be processed are a and b, a is an infinite number, the sign bit is 1 (namely, negative infinite), and b is not an infinite number, it indicates that a < b, and at this time, the infinite number judgment unit outputs a second operation result through the judgment result output port (altb 1), and the comparison operation is ended.

In the data processing method provided by this embodiment, if the data to be processed received by the data comparator has an infinite number, the infinite number judgment unit directly outputs a high-level signal without continuing the operation of other units, so that the operation amount is reduced, and the operation time is saved; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

Another embodiment provides a data processing method, in which the data to be processed is input to a zero value judging unit in S2023, and after the zero value judging unit judges whether a zero value exists in the data to be processed, the method further includes: if the zero value exists, outputting a third operation result and finishing the operation.

Specifically, if the data to be processed received by the zero value determining unit has a zero value, the zero value determining unit may directly output the third operation result through the determination result output port (altb 2), (aeqb 2), and (agtb 2), and output the maximum data and the minimum data in the received data to be processed through the maximum value output port (Zmax) and the minimum value output port (Zmin) of the data comparator, thereby ending the comparison operation. Wherein the third operation result is a high level signal.

It should be noted that, if the two to-be-processed data received by the zero-value determining unit are both zero values, the zero-value determining unit outputs a third operation result through the determination result output port (aeqb 2), and ends the operation, where the third operation result is a high-level signal. If one of the two pieces of data to be processed received by the zero value judging unit is a zero value, judging the size of the two pieces of data to be processed according to the sign bit of the other piece of data to be processed.

Illustratively, if the two input data to be processed are a and b, a is a zero value, b is not a zero value, and the sign bit of b is 0 (i.e. indicating that b is a positive number), the zero value judgment unit outputs a third operation result through the judgment result output port (altb 2) to finish the operation, and if the sign bit of b is 1 (i.e. indicating that b is a negative number), the zero value judgment unit outputs the third operation result through the judgment result output port (agtb 2) to finish the operation.

In the data processing method provided by this embodiment, if the data to be processed received by the data comparator has a zero value, the zero value judgment unit directly outputs the high level signal without continuing the operation of other units, thereby reducing the operation amount and saving the operation time; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

Fig. 17 is a flowchart of a data processing method according to another embodiment, where the determining circuit in S203 inputs the data to be processed into the comparing circuit, the comparing circuit compares the sign bit, the exponent bit, and the mantissa bit of the data to be processed, and outputs the operation result, which may be implemented by the following method, as shown in fig. 17, specifically including:

s2031, judging whether the sign bits of the received data to be processed are equal through a sign bit comparison unit.

It should be noted that the sign bit of the data to be processed may be represented by 0 or 1, where 0 represents that the data is a positive number, and 1 represents that the data is a negative number.

It should be noted that, when the zero value determining unit or the infinity determining unit does not output a high level signal, the data comparator may input the data to be processed to the sign bit comparing unit through the zero value determining unit or the infinity determining unit.

S2032, if sign bits of the data to be processed are equal, inputting the data to be processed to an exponent bit comparing unit, and determining whether exponent bits of the data to be processed are equal through the exponent bit comparing unit.

It should be noted that, when the sign bit comparison unit does not output a high level signal, the data comparator may input data to be processed to the exponent bit comparison unit through the sign bit comparison unit.

S2033, if the exponent bits of the data to be processed are equal, inputting the data to be processed to a mantissa bit comparing unit, and determining whether the mantissa bits of the data to be processed are equal or not by the mantissa bit comparing unit.

It should be noted that, when the exponent bit comparing unit does not output a high level signal, the data comparator may input data to be processed to the mantissa bit comparing unit through the exponent bit comparing unit.

And S2034, if the mantissa bits of the data to be processed are equal, outputting a fourth operation result, and ending the operation.

Specifically, if the mantissa bits of the received to-be-processed data are equal, the mantissa bit comparing unit outputs a fourth operation result through the comparison result output port (aegb 5), and outputs the maximum data and the minimum data of the received to-be-processed data through the maximum value output port (Zmax) and the minimum value output port (Zmin) of the data comparator, and ends the comparison operation, wherein the fourth operation result is a high level signal.

In the data processing method provided by the embodiment, the sign bit, the exponent bit and the mantissa bit of the received data to be processed are sequentially compared by the data comparator, so that the operation amount is reduced, and the operation time is saved; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

Another embodiment provides a data processing method, after the sign bit comparing unit determines whether the sign bits of the received to-be-processed data are equal in S2031, the method further includes: and if the sign bits of the data to be processed are not equal, outputting a fifth operation result and finishing the operation.

It should be noted that, if the sign bits of the two pieces of data to be processed received by the sign bit comparing unit are not equal, the positive number is greater than the negative number. Illustratively, if two input data are a and b, the sign bit of a is 0, and the sign bit of b is 1, indicating a > b, then the sign bit comparison unit outputs a fifth operation result through the comparison result output port (agtb 3), and outputs the maximum data and the minimum data of the received data to be processed through the maximum value output port (Zmax) and the minimum value output port (Zmin) of the data comparator, ending the comparison operation, wherein the fifth operation result is a high level signal.

In the data processing method provided by this embodiment, if the sign bits of the received data to be processed are not equal, the sign bit comparison unit directly outputs a high level signal without continuing the operation of other units, thereby reducing the operation amount and saving the operation time; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

Another embodiment provides a data processing method, in which in step S1032, the data to be processed is input to an exponent bit comparing unit, and after the exponent bit comparing unit determines whether exponent bits of the data to be processed are equal, the method further includes: and if the exponent bits of the data to be processed are not equal, outputting a sixth operation result and finishing the operation.

It should be noted that, when the exponent bits of the two pieces of data to be processed received by the exponent bit comparing unit are not equal, the larger the exponent bit is for a positive number, the larger the value is, and for a negative number, the larger the exponent bit is, the smaller the value is. Illustratively, if two input data are a and b, the sign bits of a and b are both 1, and the exponent bit of a is greater than the exponent bit of b, then a < b is indicated, and at this time, the sign bit comparison unit outputs a sixth operation result through the comparison result output port (altb 4), and the operation is ended; if the sign bits of a and b are both 0 and the exponent bit of a is greater than the exponent bit of b, a > b is indicated, at this time, the sign bit comparison unit outputs a sixth operation result through a comparison result output port (agtb 4), and outputs the maximum data and the minimum data in the received data to be processed through a maximum value output port (Zmax) and a minimum value output port (Zmin) of the data comparator, and the comparison operation is finished, wherein the sixth operation result is a high level signal.

In the data processing method provided by the embodiment, if the exponent bits of the received data to be processed are not equal, the exponent bit comparing unit directly outputs a high level signal without continuing to perform the operation of other units, so that the operation amount is reduced, and the operation time is saved; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

Another embodiment provides a data processing method, wherein in S2033, the data is input to a mantissa bit comparing unit, and after the mantissa bit comparing unit determines whether mantissa bits of the data to be processed are equal, the method further includes: and if the mantissa bits of the data to be processed are not equal, outputting a seventh operation result and finishing the operation.

It should be noted that, if mantissa bits of two data to be processed received by the mantissa bit comparing unit are not equal, for a positive number, the larger the mantissa bit is, the larger the value is, and for a negative number, the larger the mantissa bit is, the smaller the value is. Illustratively, if two input data to be processed are a and b, the sign bits of a and b are both 1, and the mantissa bit of a is greater than the mantissa bit of b, it indicates that a < b, and at this time, the mantissa bit comparing unit outputs a sixth operation result through the comparison result output port (altb 5), and the operation is ended; if the sign bits of a and b are both 0 and the mantissa bit of a is greater than the mantissa bit of b, a > b is indicated, at this time, the mantissa bit comparison unit outputs a seventh operation result through the comparison result output port (agtb 5), and outputs the maximum data and the minimum data in the received data to be processed through the maximum value output port (Zmax) and the minimum value output port (Zmin) of the data comparator, and the comparison operation is ended, wherein the seventh operation result is a high level signal.

In the data processing method provided by the embodiment, if the mantissa bits of the received data to be processed are not equal, the mantissa bit comparing unit directly outputs a high level signal without continuing the operation of other units, so that the operation amount is reduced, and the operation time is saved; in addition, the data comparator can process various data operations with different bit widths according to the received different function selection mode signals, and the area of the AI chip occupied by the data comparator is effectively reduced.

For the understanding of those skilled in the art, the data processing method provided by the present invention is described by taking an example that a data comparator can process 16-bit floating point numbers, and two 32-bit floating point numbers are received by the data comparator, and the specific method includes:

s301, the non-numeric value determining unit receives the two 32-bit floating point numbers, and determines whether a non-numeric value exists in the data of the upper 16-bit floating point number and the data of the lower 16-bit floating point number of the two 32-bit floating point numbers (i.e., a [31] and a [15] are respectively determined from b [ 16] and b [15 ].

S302, inputting the received two 32-bit floating point numbers to an infinite number judging unit through a non-numerical value judging unit, respectively judging whether infinite numbers exist in data of a high 16-bit floating point number and data of a low 16-bit floating point number of the two 32-bit floating point numbers, and if the infinite numbers do not exist, continuing to execute S203.

And S303, inputting the two received 32-bit floating point numbers to a zero value judging unit through the infinity number judging unit, respectively judging whether zero values exist in the data of the upper 16-bit floating point number and the data of the lower 16-bit floating point number of the two 32-bit floating point numbers, and if the zero values do not exist, continuing to execute S204.

S304, the received two 32-bit floating point numbers are input to a sign bit comparison unit through a zero value judgment unit, the sign bit comparison unit respectively compares the magnitude of the sign bit of the high 16-bit data and the magnitude of the sign bit of the low 16-bit data of the two 32-bit floating point numbers, and if the magnitude of the sign bit is equal, S205 is continuously executed.

It should be noted that, based on the IEEE data arithmetic standard, the sign bit in the 16-bit floating-point number may be 1-bit wide, the exponent bit may be 5-bit wide, and the mantissa bit may be 10-bit wide. Wherein a [30 ] and a [14 ] can be used as exponent bits in high and low 16-bit floating point numbers respectively, a [ 25.

S305, the sign bit comparing unit inputs the received two 32-bit floating point numbers to the exponent bit comparing unit, and the exponent bit comparing unit compares the magnitudes of exponent bits of the data of the upper 16-bit floating point number and the data of the lower 16-bit floating point number of the two 32-bit floating point numbers, and if the exponent bits are equal, continues to execute S206.

S306, the exponent bit comparing unit inputs the received two 32-bit floating point numbers to the mantissa bit comparing unit, and the mantissa bit comparing unit compares the sizes of the mantissa bits of the data of the upper 16-bit floating point number and the data of the lower 16-bit floating point number of the two 32-bit floating point numbers respectively and outputs an operation result.

Optionally, if the result of the determination in any one of the steps S301 to S303 is yes, the operation result may be output to end the operation, and meanwhile, if the result of the comparison in any one of the steps S304 to S305 is not equal, the operation result may be output to end the operation.

In addition, in the comparison operation process, the output port of the judgment result of each unit in the execution main body is two-bit valid, namely, the high level and the low level are both valid, and the specific comparison condition is shown in table 1:

TABLE 1

The execution process of S301 to S306 may specifically refer to the description of the above embodiments, and the implementation principle and the technical effect are similar, which are not described herein again.

In addition, if the data comparator can process 32-bit data, the data comparator receives two 32-bit data as an example to describe the data processing method provided by the present invention, and the specific method includes:

s401, receiving two 32-bit data through a non-numerical value judging unit, judging whether non-numerical values exist in the two 32-bit data, and if not, continuing to execute S302.

S402, inputting the received two 32-bit data into an infinite number judging unit through a non-numerical value judging unit, judging whether infinite numbers exist in the two 32-bit data, and if the infinite numbers do not exist, continuing to execute S303.

And S403, inputting the received two 32-bit data into a zero value judging unit through the infinity judging unit, judging whether zero values exist in the two 32-bit data, and if the zero values do not exist, continuing to execute S404.

S404, the zero value determining unit inputs the received two 32-bit data into the sign bit comparing unit, the sign bit comparing unit compares the magnitude of the sign bits of the two 32-bit data, and if the magnitude of the sign bits is equal, S305 is continuously executed.

S405, the sign bit comparison unit inputs the received two 32-bit data to the exponent bit comparison unit, the exponent bit comparison unit compares the magnitudes of the exponent bits of the two 32-bit data, and if the exponent bits are equal in magnitude, S406 is continuously executed.

S406, the exponent bit comparing unit inputs the received two 32-bit data to the mantissa bit comparing unit, and the mantissa bit comparing unit compares the magnitude of mantissa bits of the two 32-bit data and outputs an operation result.

Optionally, if the result of the determination in any one of the steps S401 to S403 is yes, the operation result may be output to end the operation, and meanwhile, if the result of the comparison in any one of the steps S404 to S405 is not equal, the operation result may be output to end the operation.

In addition, in the comparison operation process, the output port of the determination result of each unit in the execution main body is one bit valid, that is, the high level or the low level is valid, and if the low level is valid as an example, the specific comparison condition is shown in table 2:

TABLE 2

The execution process of S401 to S406 may specifically refer to the description of the above embodiments, and the implementation principle and the technical effect are similar, which are not described herein again.

The embodiment of the application also provides a machine learning arithmetic device, which comprises one or more data comparators mentioned in the application and is used for acquiring data to be operated and control information from other processing devices, executing specified machine learning arithmetic and transmitting an execution result to peripheral equipment through an I/O interface. Peripheral devices such as cameras, displays, mice, keyboards, network cards, wifi interfaces, servers. When more than one data comparator is included, the data comparators can be linked and transmit data through a specific structure, for example, the data comparators are interconnected and transmit data through a PCIE bus, so as to support a larger-scale machine learning operation. At this time, the same control system can be shared, and independent control systems can be provided; the memory may be shared or there may be separate memories for each accelerator. In addition, the interconnection mode can be any interconnection topology.

The machine learning arithmetic device has high compatibility and can be connected with various types of servers through PCIE interfaces.

The embodiment of the application also provides a combined processing device which comprises the machine learning arithmetic device, the universal interconnection interface and other processing devices. The machine learning arithmetic device interacts with other processing devices to jointly complete the operation designated by the user. Fig. 18 is a schematic view of a combined treatment apparatus.

Other processing devices include one or more of general purpose/special purpose processors such as Central Processing Units (CPUs), graphics Processing Units (GPUs), neural network processors, and the like. The number of processors included in the other processing devices is not limited. The other processing devices are used as interfaces of the machine learning arithmetic device and external data and control, and comprise data transportation to finish basic control of starting, stopping and the like of the machine learning arithmetic device; other processing devices can cooperate with the machine learning calculation device to complete calculation tasks.

And the universal interconnection interface is used for transmitting data and control instructions between the machine learning arithmetic device and other processing devices. The machine learning arithmetic device obtains the required input data from other processing devices and writes the required input data into a storage device on the machine learning arithmetic device chip; control instructions can be obtained from other processing devices and written into a control cache on a machine learning arithmetic device chip; the data in the storage module of the machine learning arithmetic device can also be read and transmitted to other processing devices.

Alternatively, as shown in fig. 19, the configuration may further include a storage device, and the storage device is connected to the machine learning arithmetic device and the other processing device, respectively. The storage device is used for storing data in the machine learning arithmetic device and the other processing device, and is particularly suitable for data which is required to be calculated and cannot be stored in the internal storage of the machine learning arithmetic device or the other processing device.

The combined processing device can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video monitoring equipment, the core area of a control part is effectively reduced, the processing speed is increased, and the overall power consumption is reduced. In this case, the universal interconnect interface of the combined processing device is connected to some component of the apparatus. Some parts are such as camera, display, mouse, keyboard, network card, wifi interface.

In some embodiments, a chip is also claimed, which includes the above machine learning arithmetic device or the combined processing device.

In some embodiments, a chip package structure is provided, which includes the above chip.

In some embodiments, a board card is provided, which includes the chip packaging structure. As shown in fig. 20, fig. 20 provides a card that may include other kits in addition to the chip 389, including but not limited to: memory device 390, receiving means 391 and control device 392;

the memory device 390 is connected to the chip in the chip package structure through a bus for storing data. The memory device may include a plurality of groups of memory cells 393. Each group of the storage units is connected with the chip through a bus. It is understood that each group of the memory cells may be a DDR SDRAM (Double Data Rate SDRAM).

DDR can double up the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the storage device may include 4 sets of the storage unit. Each group of the memory cells may include a plurality of DDR4 particles (chips). In one embodiment, the chip may include 4 72-bit DDR4 controllers, and 64 bits of the 72-bit DDR4 controllers are used for data transmission, and 8 bits are used for ECC checking. It can be understood that when DDR4-3200 grains are adopted in each group of memory cells, the theoretical bandwidth of data transmission can reach 25600MB/s.

In one embodiment, each group of the memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. And a controller for controlling DDR is arranged in the chip and is used for controlling data transmission and data storage of each memory unit.

The receiving device is electrically connected with the chip in the chip packaging structure. The receiving device is used for realizing data transmission between the chip and an external device (such as a server or a computer). For example, in one embodiment, the receiving device may be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface, so as to implement data transfer. Preferably, when PCIE 3.0X 16 interface is adopted for transmission, the theoretical bandwidth can reach 16000MB/s. In another embodiment, the receiving device may also be another interface, and the present application does not limit the concrete expression of the other interface, and the interface unit may implement the switching function. In addition, the calculation result of the chip is still transmitted back to an external device (e.g., a server) by the receiving apparatus.

The control device is electrically connected with the chip. The control device is used for monitoring the state of the chip. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may include a single chip Microcomputer (MCU). The chip may include a plurality of processing chips, a plurality of processing cores, or a plurality of processing circuits, and may carry a plurality of loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation and control of the working states of a plurality of processing chips, a plurality of processing andor a plurality of processing circuits in the chip.

In some embodiments, an electronic device is provided that includes the above board card.

The electronic device may be a data processor, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance instrument, a B ultrasonic instrument and/or an electrocardiograph.

It should be noted that, for simplicity of description, the foregoing method embodiments are described as a series of circuit combinations, but those skilled in the art should understand that the present application is not limited by the described circuit combinations, because some circuits may be implemented in other ways or structures according to the present application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are all alternative embodiments, and that the devices and modules referred to are not necessarily required for this application.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent should be subject to the appended claims.

Claims

1. A data comparator, comprising: the device comprises a judgment circuit and a comparison circuit, wherein the judgment circuit comprises a zero value judgment unit, the comparison circuit comprises a sign bit comparison unit and an exponent bit comparison unit, the output end of the zero value judgment unit is connected with the input end of the sign bit comparison unit and the input end of the exponent bit comparison unit, and the output end of the sign bit comparison unit is connected with the input end of the exponent bit comparison unit;

the zero value judging unit is used for judging whether zero values exist in the received data or not, the sign bit comparing unit is used for comparing the sign bits of the received data to determine the magnitude of the sign bits of the data, and the exponent bit comparing unit is used for comparing the exponent bits of the received data to determine the magnitude of the exponent bits of the data.

2. The data comparator as claimed in claim 1, wherein the judging circuit includes a first input terminal for receiving an input function selection mode signal; the comparison circuit comprises a second input end for receiving the input function selection mode signal; the function selection mode signal is used to determine the bit width of the data processed by the data comparator.

3. The data comparator as claimed in claim 1, wherein the judging circuit further comprises: the output end of the non-numerical value judging unit is connected with the input end of the infinite number judging unit, the output end of the infinite number judging unit is connected with the input end of the zero value judging unit, the output end of the infinite number judging unit is connected with the input end of the non-numerical value judging unit, and the output end of the non-numerical value judging unit is connected with the input end of the zero value judging unit;

the non-numerical value judging unit is used for judging whether a non-numerical value exists in the received data or not, and the infinite number judging unit is used for judging whether an infinite number exists in the received data or not.

4. The data comparator according to claim 3, wherein the non-numerical value judging unit in the judging circuit includes: the device comprises a first data input port, a second data input port, a function selection mode signal input port, a first data output port, a second data output port and a non-numerical value judgment result output port, wherein the first data input port is used for receiving input first data, the second data input port is used for receiving input second data, the function selection mode signal input port is used for receiving a function selection mode signal corresponding to data with different bit widths to be processed, the first data output port is used for outputting the received first data to an input port of a next unit, the second data output port is used for outputting the received second data to an input port of the next unit, and the non-numerical value judgment result output port is used for outputting a judgment result of the non-numerical value judgment unit;

the infinite number judgment unit in the judgment circuit includes: the first data input port is used for receiving input first data, the second data input port is used for receiving input second data, the function selection mode signal input port is used for receiving a function selection mode signal corresponding to data with different bit widths, the first data output port is used for outputting the received first data to an input port of a next unit, the second data output port is used for outputting the received second data to an input port of the next unit, and the infinite number judgment result output port is used for outputting a judgment result of the infinite number judgment unit;

the zero value judging unit in the judging circuit includes: the first data input port receives first data input, the second data input port receives second data input, the function selection mode signal input port receives function selection mode signals corresponding to data with different bit widths, the zero value judgment result output port outputs a judgment result of a zero value judgment unit, the first sign bit output port outputs sign bit data of the received first data, the second sign bit output port outputs sign bit data of the received second data, the first exponent bit output port outputs exponent bit data of the received first data, the second exponent bit output port outputs exponent bit data of the received second data, the second exponent bit output port outputs exponent bit data of the received first data, the second exponent bit output port outputs the exponent bit data of the received second data, and the logic signal output port outputs logic signal.

5. The data comparator according to claim 1, wherein the sign bit comparing unit in the comparing circuit: the device comprises a first sign bit input port, a second sign bit input port, a function selection mode signal input port, a sign bit comparison result output port and a sign bit logic signal output port, wherein the first sign bit input port is used for receiving sign bit data of first data, the second sign bit input port is used for receiving sign bit data of second data, the function selection mode signal input port is used for receiving function selection mode signals corresponding to data with different bit widths to be processed, the sign bit comparison result output port is used for outputting sign bit size comparison results of the data, and the sign bit logic signal output port is used for outputting logic judgment signals.

6. The data comparator as claimed in claim 1, wherein the exponent bit compare unit in the compare circuit: the device comprises a first exponent bit input port, a second exponent bit input port, a function selection mode signal input port, an exponent bit comparison result output port and an exponent bit logic signal output port, wherein the first exponent bit input port is used for receiving exponent bit data of first data in the data, the second exponent bit input port is used for receiving exponent bit data of second data in the data, the function selection mode signal input port is used for receiving function selection mode signals corresponding to data with different bit widths to be processed, the exponent bit comparison result output port is used for outputting exponent bit size comparison results of the data, and the exponent bit logic signal output port is used for outputting logic judgment signals.

7. The data comparator of claim 1, wherein the comparison circuit further comprises: and the output end of the zero value judging unit is connected with the input end of the mantissa bit comparing unit, and the mantissa bit comparing unit is used for judging the size of the mantissa bits of the received data.

8. The data comparator as claimed in claim 7, wherein the mantissa bit comparing unit comprises: a first mantissa bit input port, a second mantissa bit input port, a function selection mode signal input port, a mantissa bit comparison result output port, and a mantissa bit logic signal output port;

the first mantissa bit input port is configured to receive mantissa bit data of first data in the data, the second mantissa bit input port is configured to receive mantissa bit data of second data in the data, the function selection mode signal input port is configured to receive a function selection mode signal corresponding to data with different bit widths to be processed, the mantissa bit comparison result output port is configured to output a mantissa bit size comparison result of the data, and the mantissa bit logic signal output port is configured to output a logic determination signal.

9. A data processing method, comprising:

receiving data to be processed;

if necessary, respectively inputting the sign bit, the exponent bit and the mantissa bit of the data to be processed into the comparison circuit through the judgment circuit, comparing the magnitude of the sign bit, the exponent bit and the mantissa bit of the data to be processed through the comparison circuit, and outputting an operation result;

wherein said comparing, by said comparison circuit, sign bit, exponent bit and mantissa bit sizes of said data to be processed comprises:

comparing the sign bits of the data to be processed through the comparison circuit to determine the magnitude of the sign bits of the data;

comparing the exponent bits of the data to be processed through the comparison circuit to determine the exponent bit size of the data;

comparing, by the comparison circuit, mantissa bits of the data to be processed to determine a mantissa bit size of the data.

10. The method of claim 9, wherein the determining whether the data to be processed needs to be processed by the comparison circuit by the determining circuit comprises:

11. The method of claim 10, wherein the determining whether a non-numerical value, an infinite number, or a zero value exists in the data to be processed by the determining circuit comprises:

if the non-numerical value does not exist, inputting the data to be processed into an infinite number judging unit, and judging whether infinite numbers exist in the data to be processed or not through the infinite number judging unit;

if the infinite number does not exist, inputting the data to be processed into a zero value judging unit, and judging whether a zero value exists in the data to be processed through the zero value judging unit;

12. The method of claim 11, wherein the determining whether a non-numeric value, an infinite number, or a zero value exists in the data to be processed by the determining circuit comprises:

judging whether an infinite number exists in the data to be processed through an infinite number judging unit;

13. The method according to claim 12, wherein after the determining whether the non-numerical value exists in the data to be processed by the non-numerical value determining unit, the method further comprises: if the non-numerical value exists, outputting a first operation result, and finishing the operation;

after the data to be processed is input to an infinite number judging unit and whether infinite number exists in the data to be processed is judged by the infinite number judging unit, the method further comprises the following steps: if the infinite number exists, outputting a second operation result, and finishing the operation;

14. The method of claim 10, wherein the determining circuit inputs sign bit, exponent bit and mantissa bit of the data to be processed into a comparing circuit, respectively, and the comparing circuit compares the magnitude of sign bit, exponent bit and mantissa bit of the data to be processed to output the operation result, comprising:

if the sign bits of the data to be processed are equal, the exponent bits of the data to be processed are input to an exponent bit comparison unit, and whether the exponent bits of the data to be processed are equal or not is judged through the exponent bit comparison unit;

if the exponent bits of the data to be processed are equal, inputting mantissa bits of the data to be processed into a mantissa bit comparison unit, and judging whether the mantissa bits of the data to be processed are equal or not through the mantissa bit comparison unit;

if the mantissa bits of the data to be processed are equal, outputting a fourth operation result, and finishing the operation; or

15. The method according to claim 14, wherein after the determining, by the sign bit comparing unit, whether the sign bits of the received data to be processed are equal, the method further comprises: if the sign bits of the data to be processed are not equal, outputting a fifth operation result and finishing the operation;

16. The method of claim 15, wherein the exponent bit compare unit determining whether the exponent bits of the data to be processed are equal comprises:

17. The method of claim 14, wherein after inputting mantissa bits of the data to be processed to a mantissa bit comparison unit, and determining whether mantissa bits of the data to be processed are equal by the mantissa bit comparison unit, further comprising: and if the mantissa bits of the data to be processed are not equal, outputting a seventh operation result and finishing the operation.

18. The method of claim 17, wherein the mantissa bit comparison unit determining whether mantissa bits of the data to be processed are equal comprises:

19. A machine learning arithmetic device, characterized in that the machine learning arithmetic device comprises one or more data comparators as claimed in any one of claims 1 to 8, and is used for acquiring input data and control information to be operated from other processing devices, executing specified machine learning operation, and transmitting the execution result to other processing devices through an I/O interface;

when the machine learning arithmetic device comprises a plurality of data comparators, the data comparators can be connected through a specific structure and transmit data;

the data comparators are interconnected through a PCIE bus and transmit data so as to support operation of machine learning in a larger scale; the data comparators share the same control system or own respective control systems; the data comparators share a memory or own respective memories; the interconnection mode of the data comparators is any interconnection topology.

20. A combined processing apparatus, characterized in that the combined processing apparatus comprises the machine learning arithmetic apparatus according to claim 19, a universal interconnect interface and other processing apparatus;

and the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user.

21. The combined processing device according to claim 20, further comprising: and a storage device connected to the machine learning arithmetic device and the other processing device, respectively, for storing data of the machine learning arithmetic device and the other processing device.

22. A neural network chip, comprising the machine learning computation device of claim 19 or the combined processing device of claim 20.

23. An electronic device comprising the neural network chip of claim 22.

24. The utility model provides a board card, its characterized in that, the board card includes: a memory device, a receiving device and a control device and a neural network chip as claimed in claim 22;

wherein the neural network chip is connected with the storage device, the control device and the receiving device respectively;

the storage device is used for storing data;

the receiving device is used for realizing data transmission between the chip and external equipment;

and the control device is used for monitoring the state of the chip.

25. The card of claim 24,

the memory device includes: a plurality of groups of memory cells, each group of memory cells is connected with the chip through a bus, and the memory cells are: DDR SDRAM;

the chip includes: the DDR controller is used for controlling data transmission and data storage of each memory unit;

the receiving device is as follows: a standard PCIE interface.