CN110059797B

CN110059797B - Computing device and related product

Info

Publication number: CN110059797B
Application number: CN201811181151.6A
Authority: CN
Inventors: 不公告发明人
Original assignee: Cambricon Technologies Corp Ltd
Current assignee: Cambricon Technologies Corp Ltd
Priority date: 2018-10-10
Filing date: 2018-10-10
Publication date: 2020-03-10
Anticipated expiration: 2038-10-10
Also published as: CN110059797A

Abstract

The application provides a computing device and a related product, the computing device is used for executing convolutional neural network training operation, and the computing device has the advantages of low cost and low power consumption.

Description

Computing device and related product

Technical Field

The present application relates to the field of information processing technologies, and in particular, to a computing device and a related product.

Background

With the continuous development of information technology and the increasing demand of people, the requirement of people on the timeliness of information is higher and higher. Currently, the terminal obtains and processes information based on a general-purpose processor.

In practice, it is found that such a manner of processing information by running a software program based on a general-purpose processor is limited by the running speed of the general-purpose processor, and particularly under the condition that the load of the general-purpose processor is large, the information processing efficiency is low, the time delay is large, for the convolution training of a computation model for information processing, such as a computation model, the computation amount of the convolution training is large, and the time for the general-purpose processor to complete the convolution training is long, the efficiency is low, and the power consumption is high.

Disclosure of Invention

The embodiment of the application provides a computing device and a related product, which can improve the processing speed of convolution training operation, improve the efficiency and save the power consumption.

In a first aspect, the computing device is used for executing training operation of a convolutional neural network, the convolutional neural network comprises α layers, at least the ith layer in α layers is a convolutional layer, the computing device comprises an operation unit and a controller unit, wherein the operation unit comprises a main processing circuit and a slave processing circuit, the α is an integer which is more than or equal to 2, and the i is an integer which is less than or equal to α;

the executing the ith layer convolution forward operation specifically includes:

the controller unit is used for acquiring the ith layer of input data, the ith layer of convolution kernel and the ith layer of forward calculation instruction;

the controller unit is further configured to analyze the forward calculation instruction to obtain a plurality of forward operation instructions, and send the plurality of operation instructions, the input data, the convolution kernel, and the plurality of operation instructions to the main processing circuit;

the master processing circuit is configured to broadcast the input data to the slave processing circuit, split the convolution kernel into a plurality of kernel data blocks, distribute the plurality of kernel data blocks to the slave processing circuit, and send the plurality of operation instructions to the slave processing circuit;

the slave processing circuit is used for performing convolution operation on the input data and the received nuclear data block according to an operation instruction to obtain an operation result and transmitting the operation result to the main processing circuit;

the main processing circuit is used for splicing the operation result to obtain a convolution result;

the performing the i-th layer convolution inverse operation specifically includes:

the controller unit is also used for acquiring the ith layer of output result gradient, the ith layer of convolution kernel, the ith layer of input data and a reverse calculation instruction;

the controller unit is further configured to analyze the backward calculation instruction to obtain a plurality of backward calculation instructions, and send the backward calculation instruction, the ith layer output result gradient, the ith layer convolution kernel, and the ith layer input data to the main processing circuit;

the main processing circuit is further configured to select ith layer of inverse input data of inverse operation from ith layer of input data according to a convolution window, broadcast the ith layer of output result to the slave processing circuit in a gradient manner, split the ith layer of inverse input data into a plurality of inverse input data blocks, and distribute the plurality of inverse input data blocks and a plurality of inverse operation instructions to the slave processing circuit;

the slave processing circuit is used for executing vector multiplication vector operation on the received reverse input data block and the ith layer output result gradient according to the received reverse operation instruction to obtain a vector operation result; returning the vector operation result to the main processing circuit;

and the main processing circuit is used for determining the gradient of the ith layer of convolution kernel according to the vector operation result, and executing update operation on the gradient of the ith layer of convolution kernel and the ith layer of convolution kernel to obtain the updated convolution kernel of the ith layer.

In a second aspect, an embodiment of the present application provides a convolution training apparatus, where the convolution training apparatus includes one or more computing apparatuses provided in the first aspect, and is configured to obtain data to be operated and control information from other processing apparatuses, execute a specified convolution operation, and transmit an execution result to the other processing apparatuses through an I/O interface;

when the convolution training device comprises a plurality of computing devices, the computing devices can be connected through a specific structure and transmit data;

the computing devices are interconnected through a PCIE bus of a fast peripheral equipment interconnection bus and transmit data so as to support operation of larger-scale machine learning; a plurality of the computing devices share the same control system or own respective control systems; the computing devices share the memory or own the memory; the plurality of computing devices are interconnected in any interconnection topology.

In a third aspect, a combined processing device is provided, where the combined processing device includes the convolution training device of the second aspect, a universal interconnection interface, and other processing devices;

and the convolution training device interacts with the other processing devices to jointly complete the calculation operation specified by the user.

In a fourth aspect, a neural network chip is provided, where the neural network chip includes the computing device provided in the first aspect, or the convolution training device provided in the second aspect, or the combined processing device provided in the third aspect.

In a fifth aspect, an electronic device is provided, the electronic device comprising a chip as provided in the fourth aspect.

In a sixth aspect, a board card is provided, which includes: a memory device, an interface device and a control device and the neural network chip provided in the fourth aspect;

wherein, the neural network chip is respectively connected with the storage device, the control device and the interface device;

the storage device is used for storing data;

the interface device is used for realizing data transmission between the chip and external equipment;

and the control device is used for monitoring the state of the chip.

In a seventh aspect, the embodiment of the application further provides a convolutional neural network training method, which is applied to a computing device, wherein the convolutional neural network comprises α layers, at least the ith layer in α layers is a convolutional layer, the computing device comprises an operation unit and a controller unit, the operation unit comprises a main processing circuit and a slave processing circuit, the α is an integer which is greater than or equal to 2, and the i is an integer which is less than or equal to α;

the performing the ith layer convolution forward operation comprises:

the controller unit acquires ith layer of input data, ith layer of convolution kernel and ith layer of forward calculation instruction; analyzing the forward computing instruction to obtain a plurality of forward computing instructions, and sending the plurality of computing instructions, the input data, the convolution kernel and the plurality of computing instructions to the main processing circuit;

the master processing circuit broadcasts the input data to the slave processing circuit, splits the convolution kernel into a plurality of kernel data blocks, distributes the plurality of kernel data blocks to the slave processing circuit, and sends the plurality of operation instructions to the slave processing circuit;

the slave processing circuit executes convolution operation on the input data and the received nuclear data block according to an operation instruction to obtain an operation result, and transmits the operation result to the main processing circuit;

the main processing circuit splices the operation result to obtain a convolution result;

the performing the ith layer convolution inverse operation includes:

the controller unit acquires the ith layer of output result gradient, the ith layer of convolution kernel, the ith layer of input data and a reverse calculation instruction; analyzing the reverse calculation instruction to obtain a plurality of reverse calculation instructions, and sending the reverse calculation instructions, the ith layer output result gradient, the ith layer convolution kernel and the ith layer input data to the main processing circuit;

the main processing circuit selects ith layer of reverse input data of reverse operation from ith layer of input data according to a convolution window, broadcasts the ith layer of output result to the slave processing circuit in a gradient manner, splits the ith layer of reverse input data into a plurality of reverse input data blocks, and distributes the plurality of reverse input data blocks and a plurality of reverse operation instructions to the slave processing circuit;

the slave processing circuit performs vector multiplication vector operation on the received reverse input data block and the ith output result gradient according to the received reverse operation instruction to obtain a vector operation result; returning the vector operation result to the main processing circuit;

and the main processing circuit determines the gradient of the ith layer of convolution kernel according to the vector operation result, and executes updating operation on the gradient of the ith layer of convolution kernel and the ith layer of convolution kernel to obtain the updated convolution kernel of the ith layer.

In some embodiments, the electronic device comprises a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

In some embodiments, the vehicle comprises an aircraft, a ship, and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1A is a schematic structural diagram of a computing device according to an embodiment of the present application.

FIG. 1B is a block diagram of a computing device provided in one embodiment of the present application.

Fig. 1C is a block diagram of a computing device according to another embodiment of the present application.

Fig. 1D is a structural diagram of a main processing circuit according to an embodiment of the present application.

Fig. 1E is a block diagram of another computing device provided in the embodiments of the present application.

Fig. 1F is a schematic structural diagram of a tree module according to an embodiment of the present application.

Fig. 1G is a block diagram of another computing device provided in the embodiments of the present application.

Fig. 1H is a block diagram of another computing device provided in the embodiments of the present application.

Fig. 2 is a structural diagram of a combined processing device according to an embodiment of the present application.

Fig. 2A is a schematic structural diagram of a computing device according to an embodiment of the present application.

Fig. 3 is a block diagram of another combined processing device according to an embodiment of the present application.

Fig. 3A is a schematic structural diagram of a board card provided in the embodiment of the present application.

Fig. 4A is a schematic layered diagram of a convolutional neural network according to an embodiment of the present disclosure.

Fig. 4B is a schematic diagram of the ith layer forward operation provided in the embodiment of the present application.

Fig. 4C is a schematic diagram of the ith layer inverse operation provided in the embodiment of the present application.

Fig. 4D is a schematic diagram of a splicing result provided in the embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

First, a computing device as used herein is described. Referring to fig. 1A, there is provided a computing device for performing a convolutional neural network training operation, the computing device comprising: a controller unit 11 and an arithmetic unit 12, wherein the controller unit 11 is connected with the arithmetic unit 12, and the arithmetic unit 12 comprises: a master processing circuit 101 and a slave processing circuit 102 (which may be one or more slave processing circuits, with multiple slave processing circuits being preferred);

it should be noted that the main processing circuit itself includes a storage (e.g. a memory or a register) which can store some data of the main processing circuit, and the slave processing circuit can optionally carry the storage.

α layers, wherein at least the ith layer in the α layers is a convolutional layer, the schematic diagram of the multilayer structure of the convolutional neural network can be as shown in fig. 4A, it is to be noted that the ith layer can be any one of α layers, for convenience of drawing, the ith layer in fig. 4A takes an intermediate layer as an example, α is an integer greater than or equal to 2, and i is an integer and less than or equal to α;

the above executing the ith layer convolution forward operation specifically includes:

the above-mentioned i-th layer output result gradient may be obtained from the i + 1-th layer reverse input data gradient, for example, the i + 1-th layer reverse input data gradient may be directly used as the i-th layer output result gradient, and of course, the i + 1-th layer reverse input data gradient may be multiplied by h (x) to obtain the i-th layer output result gradient, and h (x) is a derivative function of the i-th layer activation function.

the ith layer of reverse input data for selecting the reverse operation from the ith layer of input data according to the convolution window may specifically be the ith layer of reverse input data for selecting the reverse operation according to information such as the size of the convolution window and the moving step length, and for example, the ith layer of reverse input data corresponding to the size of the convolution window and the moving step length may be obtained by cutting the ith layer of input data according to the size of the convolution window and the moving step length.

Optionally, the determining the gradient of the i-th layer of convolution kernel according to the vector operation result specifically includes:

the main processing circuit is specifically used for solving the square number corresponding to the convolution kernel gradient of all the slave operation modules at the ith layer

When c is larger than a threshold t, scaling dw' ═ dw/c × t by all gradients, and updating the value of a convolution kernel according to the scaled gradient of the convolution kernel; and w is a convolution kernel of the slave operation module.

Alternatively, the updated convolution kernel obtained by performing the update operation on the ith layer of convolution kernel gradient and the ith layer of convolution kernel may be specifically that the updated convolution kernel is the ith layer of convolution kernel gradient ＊.

It should be noted that, the training of the convolutional neural network is only an example of the training of the i-th convolutional layer, and a conventional training method may be used for training of other layers of the convolutional neural network, and the application does not limit the training methods of the convolutional neural network except for the i-th layer.

The technical scheme that this application provided sets the arithmetic element to a main many slave structures, to the computational command of forward operation, it can be with according to the computational command of forward operation with data split, can carry out parallel operation to the great part of calculated amount through following processing circuit like this, thereby improve the operating speed, save the operating time, and then reduce the consumption, to reverse operation, it splits ith layer reverse input data, then distribute to follow processing circuit and carry out the calculation of vector multiplication vector, can distribute the calculated amount to a plurality of processing circuit (main, from the structure) parallel computation like this, improve the operating speed, save the operating time, and then reduce the consumption, therefore it has the advantage that reduces training time, reduce the consumption.

The training of the ith layer can be the operation of one layer in a convolutional neural network, and for a multilayer convolutional neural network, the implementation process is that in the forward operation, after the execution of the convolutional neural network of the previous layer is completed, the operation instruction of the next layer takes the output neuron calculated in the operation unit as the input neuron of the next layer to perform operation (or performs some operation on the output neuron and then takes the output neuron as the input neuron of the next layer), and meanwhile, the weight is replaced by the weight of the next layer; in the reverse operation, after the reverse operation of the artificial neural network of the previous layer is completed, the operation instruction of the next layer takes the input neuron gradient calculated in the operation unit as the output neuron gradient of the next layer to perform operation (or performs some operation on the input neuron gradient and then takes the input neuron gradient as the output neuron gradient of the next layer), and at the same time, the weight value is replaced by the weight value of the next layer.

For the artificial neural network operation, if the artificial neural network operation has multilayer operation, the input neurons and the output neurons of the multilayer operation do not refer to the neurons in the input layer and the neurons in the output layer of the whole neural network, but for any two adjacent layers in the network, the neurons in the lower layer of the network forward operation are the input neurons, and the neurons in the upper layer of the network forward operation are the output neurons. Taking a convolutional neural network as an example, let a convolutional neural network have L layers, K1, 2.., L-1, for the K-th layer and K + 1-th layer, we will refer to the K-th layer as an input layer, in which the neurons are the input neurons, and the K + 1-th layer as an output layer, in which the neurons are the output neurons. That is, each layer except the topmost layer can be used as an input layer, and the next layer is a corresponding output layer.

Optionally, the computing device may further include: the storage unit 10 and the direct memory access unit 50, the storage unit 10 may include: one or any combination of a register and a cache, specifically, the cache is used for storing the calculation instruction; the register is used for storing the input data and a scalar; the cache is a scratch pad cache. The direct memory access unit 50 is used to read or store data from the storage unit 10.

Optionally, the controller unit includes: an instruction storage unit 110, an instruction processing unit 111, and a storage queue unit 113;

an instruction storage unit 110, configured to store a calculation instruction associated with the artificial neural network operation;

the instruction processing unit 111 is configured to analyze the calculation instruction to obtain a plurality of operation instructions;

a store queue unit 113 for storing an instruction queue, the instruction queue comprising: and a plurality of operation instructions or calculation instructions to be executed according to the front and back sequence of the queue.

For example, in an alternative embodiment, the main operation processing circuit may also include a controller unit, and the controller unit may include a main instruction processing unit, specifically configured to decode instructions into microinstructions. Of course, in another alternative, the slave arithmetic processing circuit may also include another controller unit that includes a slave instruction processing unit, specifically for receiving and processing microinstructions. The micro instruction may be a next-stage instruction of the instruction, and the micro instruction may be obtained by splitting or decoding the instruction, and may be further decoded into control signals of each component, each unit, or each processing circuit.

In one alternative, the structure of the calculation instruction may be as shown in the following table.

Operation code

Registers or immediate data

Register/immediate

...

The ellipses in the above table indicate that multiple registers or immediate numbers may be included.

In another alternative, the computing instructions may include: one or more operation domains and an opcode. The computation instructions may include neural network operation instructions. Taking the neural network operation instruction as an example, as shown in table 1, register number 0, register number 1, register number 2, register number 3, and register number 4 may be operation domains. Each of register number 0, register number 1, register number 2, register number 3, and register number 4 may be a number of one or more registers.

The register may be an off-chip memory, and in practical applications, may also be an on-chip memory for storing data, where the data may specifically be n-dimensional data, where n is an integer greater than or equal to 1, and for example, when n is equal to 1, the data is 1-dimensional data, that is, a vector, and when n is equal to 2, the data is 2-dimensional data, that is, a matrix, and when n is equal to 3 or more, the data is a multidimensional tensor.

Optionally, the controller unit may further include:

the dependency processing unit 108 is configured to determine whether a first operation instruction is associated with a zeroth operation instruction before the first operation instruction when there are multiple operation instructions, cache the first operation instruction in the instruction storage unit if the first operation instruction is associated with the zeroth operation instruction, and extract the first operation instruction from the instruction storage unit and transmit the first operation instruction to the operation unit after the zeroth operation instruction is executed;

the determining whether the first operation instruction has an association relationship with a zeroth operation instruction before the first operation instruction comprises:

extracting a first storage address interval of required data (such as a matrix) in the first operation instruction according to the first operation instruction, extracting a zeroth storage address interval of the required matrix in the zeroth operation instruction according to the zeroth operation instruction, if the first storage address interval and the zeroth storage address interval have an overlapped area, determining that the first operation instruction and the zeroth operation instruction have an association relation, and if the first storage address interval and the zeroth storage address interval do not have an overlapped area, determining that the first operation instruction and the zeroth operation instruction do not have an association relation.

In another alternative embodiment, the arithmetic unit 12 may include a master processing circuit 101 and a plurality of slave processing circuits 102, as shown in fig. 1C. In one embodiment, as shown in FIG. 1C, a plurality of slave processing circuits are distributed in an array; each slave processing circuit is connected with other adjacent slave processing circuits, the master processing circuit is connected with k slave processing circuits in the plurality of slave processing circuits, and the k slave processing circuits are as follows: it should be noted that, as shown in fig. 1C, the K slave processing circuits include only the n slave processing circuits in the 1 st row, the n slave processing circuits in the m th row, and the m slave processing circuits in the 1 st column, that is, the K slave processing circuits are slave processing circuits directly connected to the master processing circuit among the plurality of slave processing circuits.

And the K slave processing circuits are used for forwarding data and instructions between the main processing circuit and the plurality of slave processing circuits.

Optionally, as shown in fig. 1D, the main processing circuit may further include: one or any combination of the conversion processing circuit 110, the activation processing circuit 111, and the addition processing circuit 112;

a conversion processing circuit 110 for performing an interchange between the first data structure and the second data structure (e.g., conversion of continuous data and discrete data) on the data block or intermediate result received by the main processing circuit; or performing an interchange between the first data type and the second data type (e.g., a fixed point type to floating point type conversion) on a data block or intermediate result received by the main processing circuitry;

an activation processing circuit 111 for performing an activation operation of data in the main processing circuit;

and an addition processing circuit 112 for performing addition operation or accumulation operation.

The main processing circuit is configured to determine that the input data is broadcast data, a convolution kernel is distribution data, split the convolution kernel into a plurality of kernel data blocks, and send at least one kernel data block of the plurality of kernel data blocks and at least one operation instruction of the plurality of operation instructions to the K slave processing circuits;

the K slave processing circuits are used for forwarding the core data block, the input data and the operation instruction between the main processing circuit and the plurality of slave processing circuits;

the plurality of slave processing circuits are used for performing convolution operation on the received nuclear data block and the input data according to the operation instruction to obtain an operation result and transmitting the operation result to the K slave processing circuits;

the main processing circuit is used for splicing the operation results sent by the K slave processing circuits to obtain a convolution result, and sending the convolution result to the controller unit;

the main processing circuit is further configured to broadcast the ith layer of output result gradient to the k slave processing circuits, select ith layer of inverse input data subjected to inverse operation from the ith layer of input data according to a convolution window, split the ith layer of inverse input data into a plurality of inverse input data blocks, and distribute the plurality of inverse input data blocks and the plurality of inverse operation instructions to the k slave processing circuits;

the k slave processing circuits are further used for forwarding reverse input data blocks, vector operation results, ith layer output result gradients and reverse operation instructions between the master processing circuit and the plurality of slave processing circuits;

the slave processing circuits are used for executing vector multiplication vector operation on the received input data block and the ith layer output result gradient according to the received inverse operation instruction to obtain a vector operation result; returning the vector operation results to the k slave processing circuits;

and the main processing circuit is used for determining the gradient of the ith layer of convolution kernel according to the vector operation result sent by the k slave processing circuits, and executing update operation on the gradient of the ith layer of convolution kernel and the ith layer of convolution kernel to obtain the updated convolution kernel of the ith layer.

The slave processing circuit includes: a multiplication processing circuit;

the multiplication processing circuit is used for executing multiplication operation on the received data block to obtain a product result;

forwarding processing circuitry (optional) for forwarding the received data block or the product result.

And the accumulation processing circuit is used for performing accumulation operation on the product result to obtain the intermediate result.

In another embodiment, the operation instruction is a matrix by matrix instruction, an accumulation instruction, an activation instruction, or the like.

The following describes a specific calculation method of the calculation apparatus shown in fig. 1A by a neural network operation instruction. For a neural network operation instruction, the formula that actually needs to be executed may be: s-s (∑ wx)_i+ b), wherein the weight w is multiplied by the input data x_iAnd summing, adding a bias b, and performing activation operation s (h) to obtain a final output result s.

In an alternative embodiment, as shown in fig. 1E, the arithmetic unit comprises: a tree module 40, the tree module comprising: a root port 401 and a plurality of branch ports 404, wherein the root port of the tree module is connected with the main processing circuit, and the branch ports of the tree module are respectively connected with one of the plurality of slave processing circuits;

the tree module has a transceiving function, for example, as shown in fig. 1E, the tree module is a transmitting function, and as shown in fig. 2A, the tree module is a receiving function.

And the tree module is used for forwarding data blocks, weights and operation instructions between the main processing circuit and the plurality of slave processing circuits.

Optionally, the tree module is an optional result of the computing device, and may include at least 1 layer of nodes, where the nodes are line structures with forwarding function, and the nodes themselves may not have computing function. If the tree module has zero-level nodes, the tree module is not needed.

Optionally, the tree module may have an n-ary tree structure, for example, a binary tree structure as shown in fig. 1F, or may have a ternary tree structure, where n may be an integer greater than or equal to 2. The present embodiment is not limited to the specific value of n, the number of layers may be 2, and the slave processing circuit may be connected to nodes of other layers than the node of the penultimate layer, for example, the node of the penultimate layer shown in fig. 1F.

Optionally, the operation unit may carry a separate cache, as shown in fig. 1G, and may include: a neuron buffer unit, the neuron buffer unit 63 buffers the input neuron vector data and the output neuron value data of the slave processing circuit.

As shown in fig. 1H, the arithmetic unit may further include: and a weight buffer unit 64, configured to buffer weight data required by the slave processing circuit in the calculation process.

In an alternative embodiment, the arithmetic unit 12, as shown in fig. 1B, may include a branch processing circuit 103; the specific connection structure is shown in fig. 1B, wherein,

the branch processing circuit 103 may include a memory, as shown in fig. 1B, the size of the memory of the branch processing circuit 103 may be between 2 and 2.5 times of the maximum data capacity that a single slave processing circuit needs to store, after such setting, the slave processing circuit does not need to set the memory, and with respect to a branch processing circuit, it only needs to set 2.5 ＊ R (the capacity value required by a single slave processing circuit), if there is no branch processing circuit, 4 ＊ R needs to be set, and the utilization rate of its register is low, so that the structure can effectively reduce the total capacity of the memory and reduce the cost.

The main processing circuit is specifically configured to determine that the input data is broadcast data, the convolution kernel is distribution data, split the convolution kernel into a plurality of kernel data blocks, and send at least one kernel data block of the plurality of kernel data blocks, the input data, and at least one operation instruction of the plurality of operation instructions to the branch processing circuit;

the branch processing circuit is used for forwarding a core data block, input data and an operation instruction between the main processing circuit and the plurality of slave processing circuits;

the slave processing circuits are used for performing convolution operation on the received kernel data block and the input data according to the operation instruction to obtain an operation result and transmitting the operation result to the branch processing circuit;

the main processing circuit is used for splicing the operation results sent by the branch processing circuits to obtain a convolution result;

the main processing circuit is further configured to broadcast the ith layer of output result gradient to the branch processing circuit, select ith layer of inverse input data of inverse operation from the ith layer of input data according to a convolution window, split the ith layer of inverse input data into a plurality of inverse input data blocks, and distribute the plurality of inverse input data blocks and the plurality of inverse operation instructions to the branch processing circuit;

the branch processing circuit is further used for forwarding reverse input data blocks, vector operation results, ith layer output result gradients and reverse operation instructions between the main processing circuit and the plurality of slave processing circuits;

the slave processing circuit is used for executing vector multiplication vector operation on the received reverse input data block and the ith layer output result gradient according to the received reverse operation instruction to obtain a vector operation result; returning the vector operation result to the branch processing circuit;

and the main processing circuit is used for determining the gradient of the ith layer of convolution kernel according to the vector operation result forwarded by the branch processing circuit, and executing update operation on the gradient of the ith layer of convolution kernel and the ith layer of convolution kernel to obtain the updated convolution kernel of the ith layer.

On the other hand, the application also provides a convolutional neural network training method which is applied to a computing device, wherein the convolutional neural network comprises α layers, at least the ith layer in α layers is a convolutional layer, the computing device comprises an arithmetic unit and a controller unit, the arithmetic unit comprises a main processing circuit and a slave processing circuit, α is an integer which is more than or equal to 2, and i is an integer which is less than or equal to α, and the convolutional neural network training method at least comprises the steps of carrying out the convolutional forward operation of the ith layer and carrying out the convolutional backward operation of the ith layer;

the performing the ith layer convolution forward operation comprises: the schematic diagram of the forward operation is shown in fig. 4B.

the performing the ith layer convolution inverse operation includes: the inverse operation diagram is shown in fig. 4C.

Referring to fig. 4D, fig. 4D is a schematic diagram of the operation result being spliced to obtain a splicing diagram in the convolution result, where the splicing manner is as shown in fig. 4D, the minimum value of the column number and the minimum value of the row number in the input data element executing the operation result are determined, the column number of the operation result at the position of the convolution result is determined to be the minimum value of the column number, and the row number is the minimum value of the row number. And traversing all the operation results, and splicing according to the principle to obtain a convolution result.

The application also discloses a convolution training device, which comprises one or more computing devices mentioned in the application, and is used for acquiring data to be operated and control information from other processing devices, executing specified machine learning operation, and transmitting the execution result to peripheral equipment through an I/O interface. Peripheral devices such as cameras, displays, mice, keyboards, network cards, wifi interfaces, servers. When more than one computing device is included, the computing devices may be linked and transmit data through a specific structure, such as through a PCIE bus, to support larger-scale convolutional neural network training operations. At this time, the same control system may be shared, or there may be separate control systems; the memory may be shared or there may be separate memories for each accelerator. In addition, the interconnection mode can be any interconnection topology.

The convolution training device has high compatibility and can be connected with various types of servers through PCIE interfaces.

The application also discloses a combined processing device which comprises the convolution training device, the universal interconnection interface and other processing devices. The machine learning arithmetic device interacts with other processing devices to jointly complete the operation designated by the user. Fig. 2 is a schematic view of a combined treatment apparatus.

Other processing devices include one or more of general purpose/special purpose processors such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), neural network processors, and the like. The number of processors included in the other processing devices is not limited. The other processing devices are used as interfaces of the machine learning arithmetic device and external data and control, and comprise data transportation to finish basic control of starting, stopping and the like of the machine learning arithmetic device; other processing devices may cooperate with the machine learning computing device to perform computing tasks.

And the general interconnection interface is used for transmitting data and control instructions between the convolution training device and other processing devices. The convolution training device acquires required input data from other processing devices and writes the input data into a storage device on a convolution training device chip; control instructions can be obtained from other processing devices and written into a control cache on a convolution training device slice; the data in the memory module of the convolution training device can also be read and transmitted to other processing devices.

Optionally, the structure may further include a storage device, as shown in fig. 3, and the storage device is connected to the convolution training device and the other processing device, respectively. The storage device is used for storing data in the convolution training device and the other processing device, and is particularly suitable for data which is required to be calculated and cannot be stored in the convolution training device or the other processing device.

The combined processing device can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video monitoring equipment, the core area of a control part is effectively reduced, the processing speed is increased, and the overall power consumption is reduced. In this case, the generic interconnect interface of the combined processing device is connected to some component of the apparatus. Some parts are such as camera, display, mouse, keyboard, network card, wifi interface.

In some embodiments, a chip is also claimed, which includes the convolution training device or the combined processing device.

In some embodiments, a chip package structure is provided, which includes the above chip.

In some embodiments, a board card is provided, which includes the above chip package structure. Referring to fig. 3A, fig. 3A provides a card that may include other mating components in addition to the chip 389, including but not limited to: memory device 390, interface device 391 and control device 392;

the memory device 390 is connected to the chip in the chip package structure through a bus for storing data. The memory device may include a plurality of groups of memory cells 393. Each group of the storage units is connected with the chip through a bus. It is understood that each group of the memory cells may be a DDR SDRAM (Double Data Rate SDRAM).

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the storage device may include 4 sets of the storage unit. Each group of the memory cells may include a plurality of DDR4 particles (chips). In one embodiment, the chip may internally include 4 72-bit DDR4 controllers, and 64 bits of the 72-bit DDR4 controller are used for data transmission, and 8 bits are used for ECC check. It can be understood that when DDR 4-3200 particles are adopted in each group of memory cells, the theoretical bandwidth of data transmission can reach 25600 MB/s.

In one embodiment, each group of the memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. And a controller for controlling DDR is arranged in the chip and is used for controlling data transmission and data storage of each memory unit.

The interface device is electrically connected with a chip in the chip packaging structure. The interface device is used for realizing data transmission between the chip and an external device (such as a server or a computer). For example, in one embodiment, the interface device may be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface, so as to implement data transfer. Preferably, when PCIE 3.0X 16 interface transmission is adopted, the theoretical bandwidth can reach 16000 MB/s. In another embodiment, the interface device may also be another interface, and the present application does not limit the concrete expression of the other interface, and the interface unit may implement the switching function. In addition, the calculation result of the chip is still transmitted back to an external device (e.g., a server) by the interface device.

The control device is electrically connected with the chip. The control device is used for monitoring the state of the chip. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may include a single chip Microcomputer (MCU). The chip may include a plurality of processing chips, a plurality of processing cores, or a plurality of processing circuits, and may carry a plurality of loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation and control of the working states of a plurality of processing chips, a plurality of processing andor a plurality of processing circuits in the chip.

In some embodiments, an electronic device is provided that includes the above board card.

The electronic device comprises a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, an intelligent terminal, a mobile phone, a vehicle data recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that the acts and modules referred to are not necessarily required in this application.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software program module.

The integrated units, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A computing device is characterized by being used for executing convolutional neural network training operation, wherein the convolutional neural network comprises α layers, at least the ith layer in α layers is a convolutional layer, the computing device comprises an operation unit and a controller unit, the operation unit comprises a main processing circuit and a slave processing circuit, α is an integer which is more than or equal to 2, i is an integer which is less than or equal to α, and the computing device is used for executing the ith layer of convolutional forward operation and the ith layer of convolutional reverse operation;

the controller unit is further configured to analyze the forward calculation instruction to obtain a plurality of forward operation instructions, and send the input data, the convolution kernel, and the plurality of operation instructions to the main processing circuit;

the main processing circuit is further configured to select ith layer of inverse input data of inverse operation from ith layer of input data according to a convolution window, broadcast the ith layer of output result gradient to the slave processing circuit, split the ith layer of inverse input data into a plurality of inverse input data blocks, and distribute the plurality of inverse input data blocks and a plurality of inverse operation instructions to the slave processing circuit;

2. The apparatus of claim 1, wherein the determining the i-th layer convolution kernel gradient according to the vector operation result comprises:

When c is larger than a threshold t, scaling dw' ═ dw/c × t by all gradients, and updating the value of a convolution kernel according to the scaled gradient of the convolution kernel; and w is a convolution kernel of the slave operation module, and dw is a convolution kernel gradient.

3. The apparatus of claim 1, wherein the computing apparatus further comprises: a storage unit and a direct memory access unit, the storage unit comprising: any combination of a register and a cache;

the cache is used for storing the input data and the convolution kernel;

the register is used for storing scalar data in the input data;

the cache comprises a scratch pad cache;

the controller unit includes: the device comprises an instruction storage unit, an instruction processing unit and a storage queue unit;

the instruction storage unit is used for storing a calculation instruction associated with the convolutional neural network training operation;

the instruction processing unit is used for analyzing the calculation instruction to obtain a plurality of operation instructions;

the storage queue unit is configured to store an instruction queue, where the instruction queue includes: a plurality of operation instructions or calculation instructions to be executed according to the front and back sequence of the queue;

the main processing circuit includes: a dependency processing unit;

the dependency relationship processing unit is configured to determine whether an association relationship exists between a first operation instruction and a zeroth operation instruction before the first operation instruction, if the association relationship exists between the first operation instruction and the zeroth operation instruction, cache the first operation instruction in the instruction storage unit, and after the zeroth operation instruction is executed, extract the first operation instruction from the instruction storage unit and transmit the first operation instruction to the operation unit;

extracting a first storage address interval of required data in the first operation instruction according to the first operation instruction, extracting a zeroth storage address interval of the required data in the zeroth operation instruction according to the zeroth operation instruction, if the first storage address interval and the zeroth storage address interval have an overlapped area, determining that the first operation instruction and the zeroth operation instruction have an association relation, and if the first storage address interval and the zeroth storage address interval do not have an overlapped area, determining that the first operation instruction and the zeroth operation instruction do not have an association relation.

4. The apparatus of claim 1, wherein if the number of the slave processing circuits is plural, the arithmetic unit comprises: a tree module, the tree module comprising: the root port of the tree module is connected with the main processing circuit, and the branch ports of the tree module are respectively connected with one of the plurality of slave processing circuits;

the tree module is used for forwarding input data, convolution kernels, forward operation instructions, operation results, reverse operation instructions and output result gradients between the main processing circuit and the plurality of slave processing circuits.

5. The apparatus of claim 1, wherein if the number of the slave processing circuits is plural, the arithmetic unit further comprises one or more branch processing circuits, each branch processing circuit being connected to at least one slave processing circuit,

6. The apparatus of claim 1, wherein if the number of the slave processing circuits is plural, the plural slave processing circuits are distributed in an array; each slave processing circuit is connected with other adjacent slave processing circuits, the master processing circuit is connected with k slave processing circuits in the plurality of slave processing circuits, and the k slave processing circuits are as follows: n slave processing circuits of row 1, n slave processing circuits of row m, and m slave processing circuits of column 1;

the k slave processing circuits are used for forwarding data and operation instructions between the main processing circuit and the plurality of slave processing circuits;

the slave processing circuits are used for performing convolution operation on the received kernel data block and the input data according to the operation instruction to obtain an operation result and transmitting the operation result to the k slave processing circuits;

7. The apparatus according to any one of claims 5 to 6,

the main processing circuit is specifically configured to combine and sort operation results sent by the plurality of processing circuits to obtain the convolution result.

8. The apparatus of any of claims 5-6, wherein the main processing circuit comprises: a conversion processing circuit;

the conversion processing circuit is configured to perform conversion processing on data, and specifically includes: performing an interchange between the first data structure and the second data structure with the input data, convolution kernel or convolution result received by the main processing circuit; or performing an interchange between the first data type and the second data type using input data received by the main processing circuit, the convolution kernel, or the convolution result.

9. The apparatus of claim 5 or 6, wherein the slave processing circuit comprises: a multiplication processing circuit and an accumulation processing circuit;

the multiplication processing circuit is used for performing product operation on element values in the received nuclear data block and element values at corresponding positions in the input data to obtain a product result;

and the accumulation processing circuit is used for executing accumulation operation on the product result to obtain the convolution result.

10. The apparatus of claim 4, wherein the tree module is an n-ary tree structure, and wherein n is an integer greater than or equal to 2.

11. A convolution training device, characterized in that the convolution training device comprises one or more computing devices according to any one of claims 1 to 10, and is used for acquiring data to be operated on and control information from other processing devices, executing specified convolution operation, and transmitting the execution result to other processing devices through an I/O interface;

12. A combined processing apparatus, characterized in that it comprises the convolution training apparatus of claim 11, a generic interconnect interface and other processing means;

13. The combined processing device according to claim 12, further comprising: and the storage device is respectively connected with the convolution training device and the other processing devices and is used for storing the data of the convolution training device and the other processing devices.

14. A neural network chip, comprising the computing device of claim 1 or the convolution training device of claim 11 or the combinatorial processing device of claim 13.

15. An electronic device, characterized in that it comprises a chip according to claim 14.

16. The utility model provides a board card, its characterized in that, the board card includes: a memory device, an interface apparatus and a control device and the neural network chip of claim 15;

the storage device is used for storing data;

and the control device is used for monitoring the state of the chip.

17. The board of claim 16,

the memory device includes: a plurality of groups of memory cells, each group of memory cells is connected with the chip through a bus, and the memory cells are: DDR SDRAM;

the chip includes: the DDR controller is used for controlling data transmission and data storage of each memory unit;

the interface device is as follows: a standard PCIE interface.

18. A convolutional neural network training method is applied to a computing device, wherein the convolutional neural network comprises α layers, at least the ith layer in α layers is a convolutional layer, the computing device comprises an arithmetic unit and a controller unit, the arithmetic unit comprises a main processing circuit and a slave processing circuit, α is an integer which is more than or equal to 2, i is an integer which is less than or equal to α, and the convolutional neural network training method at least comprises the steps of carrying out the forward operation of the ith layer of convolution and carrying out the reverse operation of the ith layer of convolution;

the performing the ith layer convolution forward operation comprises:

the controller unit acquires ith layer of input data, ith layer of convolution kernel and ith layer of forward calculation instruction; analyzing the forward calculation instruction to obtain a plurality of forward operation instructions, and sending the input data, the convolution kernel and the plurality of operation instructions to the main processing circuit;

the performing the ith layer convolution inverse operation includes:

the main processing circuit selects ith layer of reverse input data of reverse operation from ith layer of input data according to a convolution window, broadcasts the ith layer of output result gradient to the slave processing circuit, splits the ith layer of reverse input data into a plurality of reverse input data blocks, and distributes the plurality of reverse input data blocks and a plurality of reverse operation instructions to the slave processing circuit;

19. The method according to claim 18, wherein if the number of the slave processing circuits is plural, the arithmetic unit further comprises one or more branch processing circuits, each branch processing circuit being connected to at least one slave processing circuit,

the main processing circuit determines that the input data is broadcast data, the convolution kernel is distribution data, the convolution kernel is split into a plurality of kernel data blocks, and at least one kernel data block in the plurality of kernel data blocks, the input data and at least one operation instruction in the plurality of operation instructions are sent to the branch processing circuit;

the branch processing circuit forwards core data blocks, input data and operation instructions between the main processing circuit and the plurality of slave processing circuits;

the plurality of slave processing circuits execute convolution operation on the received nuclear data blocks and the input data according to the operation instruction to obtain operation results, and transmit the operation results to the branch processing circuit;

the main processing circuit splices the operation results sent by the branch processing circuits to obtain a convolution result;

the main processing circuit broadcasts the ith layer of output result gradient to the branch processing circuit, selects ith layer of reverse input data of reverse operation from ith layer of input data according to a convolution window, splits the ith layer of reverse input data into a plurality of reverse input data blocks, and distributes the plurality of reverse input data blocks and a plurality of reverse operation instructions to the branch processing circuit;

the branch processing circuit forwards an inverse input data block, a vector operation result, an ith layer output result gradient and an inverse operation instruction between the main processing circuit and the plurality of slave processing circuits;

the slave processing circuit performs vector multiplication vector operation on the received reverse input data block and the ith output result gradient according to the received reverse operation instruction to obtain a vector operation result; returning the vector operation result to the branch processing circuit;

and the main processing circuit determines the gradient of the ith layer of convolution kernel according to the vector operation result forwarded by the branch processing circuit, and executes updating operation on the gradient of the ith layer of convolution kernel and the ith layer of convolution kernel to obtain the ith layer of updated convolution kernel.

20. The method of claim 18, wherein if the number of the slave processing circuits is plural, the plural slave processing circuits are distributed in an array; each slave processing circuit is connected with other adjacent slave processing circuits, the master processing circuit is connected with k slave processing circuits in the plurality of slave processing circuits, and the k slave processing circuits are as follows: n slave processing circuits of row 1, n slave processing circuits of row m, and m slave processing circuits of column 1;

forwarding of data and arithmetic instructions by the k slave processing circuits between the master processing circuit and a plurality of slave processing circuits;

the main processing circuit determines that the input data are broadcast data, a convolution kernel is distribution data, the convolution kernel is split into a plurality of kernel data blocks, and at least one kernel data block in the plurality of kernel data blocks and at least one operation instruction in a plurality of operation instructions are sent to the k slave processing circuits;

the k slave processing circuits forward core data blocks, input data and arithmetic instructions between the master processing circuit and the plurality of slave processing circuits;

the slave processing circuits perform convolution operation on the received kernel data blocks and the input data according to the operation instruction to obtain operation results, and transmit the operation results to the k slave processing circuits;

the main processing circuit splices the operation results sent by the k slave processing circuits to obtain a convolution result, and sends the convolution result to the controller unit;

the main processing circuit broadcasts the ith layer of output result gradient to the k slave processing circuits, selects ith layer of reverse input data of reverse operation from the ith layer of input data according to a convolution window, splits the ith layer of reverse input data into a plurality of reverse input data blocks, and distributes the plurality of reverse input data blocks and a plurality of reverse operation instructions to the k slave processing circuits;

the k slave processing circuits forward reverse input data blocks, vector operation results, ith layer output result gradients and reverse operation instructions between the master processing circuit and the plurality of slave processing circuits;

the slave processing circuits execute vector multiplication vector operation on the received input data block and the ith output result gradient according to the received inverse operation instruction to obtain a vector operation result; returning the vector operation results to the k slave processing circuits;

and the main processing circuit determines the gradient of the ith layer of convolution kernel according to the vector operation result sent by the k slave processing circuits, and executes updating operation on the gradient of the ith layer of convolution kernel and the ith layer of convolution kernel to obtain the ith layer of updated convolution kernel.