JPH0934687A - Arithmetic circuit and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a high speed calculation by operating two addition circuits in parallel. SOLUTION: Because an adder 5 adds the value which is twice as many as the addition value outputted from a selector 3 next to an initial value, the even numbered addition value is to be added to the initial value. Because the unmagnified value of the addition value is inputted at first and the value which is twice as many as the addition value is inputted from the next time in an adder 7, the odd numbered addition value is to be added to the initial value. A selector 10 selects either one of the outputs of XOR gates 12 and 13 in accordance with the selection signal from a control circuit 11 and outputs the output as the carry of the whole of the circuit shown by a figure. Namely, the circuit is provided with a first arithmetic means adding the value which is odd number times as many as a second constant to a first constant, a second arithmetic means adding the value which is even number times as many as the second constant to the first constant and an output means outputting a carry signal based on the addition result of the first and second arithmetic means, and these first and second arithmetic means operate in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic circuit and an arithmetic method, for example, an arithmetic circuit and an arithmetic method for performing an arithmetic operation of two constants.

[0002]

2. Description of the Related Art As a means for performing high-speed addition, there is a look-ahead carry circuit in which an arithmetic circuit is divided into a plurality of parts, each partial sum is calculated, and a carry is passed from the carry of each circuit to the next circuit. DDA (digital integrator)
In this example, this is used when an addition value is added to a certain constant and the carry output is used to process image and audio data.

[0003]

However, the above-mentioned technique has the following problems.

When the speed is increased by the above technique, a circuit for generating a carry passing from the partial sum to the higher rank becomes large.
For example, in order to realize this circuit with a C-MOS gate array, the circuit scale becomes large, the wiring length and the chip area become large, and the capacitive load increases, which limits the speeding up.

The present invention is intended to solve the above problems, and an object thereof is to provide an arithmetic circuit and an arithmetic method capable of performing high-speed arithmetic.

[0006]

The present invention has the following structure as one means for achieving the above object.

An arithmetic circuit according to the present invention is an arithmetic circuit for performing an arithmetic operation of two constants, which comprises first arithmetic means for adding an odd multiple of the second constant to the first constant, and the first arithmetic means. A second arithmetic means for adding an even multiple of the second constant to a constant, and an output means for outputting a carry signal based on the addition result of the first and second arithmetic means, The second arithmetic means operates in parallel.

The calculation method according to the present invention is a calculation method for calculating two constants, which comprises a first calculation step of adding an odd multiple of the second constant to the first constant, A second calculation step for adding an even multiple of the second constant to one constant, and an output step for outputting a carry signal based on the addition result of the first and second calculation steps, It is characterized in that the first and second calculation steps are executed in parallel.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an arithmetic circuit according to an embodiment of the present invention will be described in detail with reference to the drawings.

[Configuration] FIG. 1 is a block diagram showing a configuration example of an arithmetic circuit of one embodiment according to the present invention.

In the figure, 11 is a control circuit for controlling the sequence of the entire circuit, which is initialized by a reset signal input from the outside.

1 is a latch that stores a first constant (hereinafter referred to as "initial value"), 2 is a latch that stores a second constant (hereinafter referred to as "added value"), and 3 and 4 each have two inputs The one-output data selector selects and outputs either the initial value stored in the latch 1 or the added value stored in the latch 2 according to the selection signal from the control circuit 11.

Numeral 6 is a double / one-size selector, which switches the added value output from the selector 4 between single and double according to a selection signal from the control circuit 11.

8 and 9 are flip-flops for holding the accumulated value
(F / F), 5 is an adder that adds the cumulative value held in F / F8 and the data output from the selector 3, 7 is the cumulative value held in F / F9 and the output from the selector 6 An adder for adding data, 12 is an XOR gate for XORing the highest output of adder 5 and the highest output of F / F9, and 13 is the highest output of adder 7 and F / F8 It is an XOR gate for XORing the highest output of.

A selector 10 selects either one of the outputs of the XOR gates 12 and 13 according to a selection signal from the control circuit 11 and outputs it as a carry of the entire circuit shown in FIG.

[Operation] Next, the operation of the circuit shown in FIG. 1 will be described. Hereinafter, a case of handling n-bit data from the (n-1) th to the 0th bit will be described.

The selector 3 inputs the initial value of the n-bit width stored in the latch 1 to the A input, and also selects the n-1th to 1st bits of the added value of the n-bit width stored in the latch 2. Input "0" to B input in the least significant bit. That is, the added value is shifted by 1 bit to the left (doubled) and input. Further, the selector 4 inputs the initial value of the n-bit width stored in the latch 1 to the B input and also stores it in the latch 2.
Input the addition value of n-bit width to A input.

FIG. 2 is a block diagram showing a configuration example of the double / same-size selector 6, and 201 is a selection signal S inputted from the control circuit 11.
AND gate for calculating the AND of nth bit of the input data A, 202 is a selector, respectively, according to the selection signal S,
Select the bit data (An-1 to A0) input to either I0 input or I1 input. Reference numeral 204 is an inverter for inverting the selection signal S, 205 is the 0th bit of the input data and the inverter 20.
It is an AND gate that obtains the logical product with the output of 4. This time /
The same size selector 6 outputs the input data as it is when the selection signal S is '0' (actual size operation), and shifts the input data 1 bit to the left (double) when the selection signal S is '1'. Output (double operation).

The adder 5, to which the output of the F / F 8 and the output of the selector 3 are input, outputs the initial values from the n−1th bit to the 0th bit output from the selector 3 to the initial value, and outputs them from the selector 3 to the next. Since the doubled added value is added, the even-numbered added value is accumulated with respect to the initial value. Where F / F8
Is n bits wide and holds the nth bit to the 1st bit.
The highest nth bit represents a carry when adding values are sequentially added to the initial value.

The adder 7 also performs the same addition as the adder 5, except that a value equal to the addition value is input first, and then a value equal to twice the addition value is input. . That is,
The adder 7 accumulates odd-numbered addition values with respect to the initial value.

Since the F / Fs 8 and 9 hold the outputs of the adders 5 and 7, respectively, at the falling edge of the clock, at the m-th clock from the start of the calculation, the m-2, m-1, and m-th values are You can get it, and you are calculating the m + 1st value.
FIG. 3 is a timing chart showing the situation.

In FIG. 3, 100 is the system clock, and 10
5 is an enable signal for arithmetic operation, these are control circuits 11
Is a signal input to.

Reference numeral 101 is a clear signal for F / F8 and 9, which is cleared by'L '. Reference numeral 102 is an F / F8 clock, 103 is an F / F9 clock, 104 is a selection signal of the selectors 3 and 4, 106 is a selection signal of the double / magnification selector 6, and 113 is a selection signal of the selector 10. These are signals output by the control circuit 11. The clock 103 rises almost at the same time as the addition enable signal 105 rises, and the addition enable signal 105
Rises, half a clock cycle later, the clock 104 rises, and the selection signal 106 and the selection signal 113 are set.

107 is the output of the selector 3, 108 is the output of the selector 4, 109 is the output of the adder 5, 110 is the output of the adder 7, and 111
Is the output of F / F8, and 112 is the output of F / F9. In addition, adder 5
Since the outputs of 7 and 7 are not latched, the fixed value is not output until a certain time has elapsed after the input changed, but in the present embodiment, assuming that the output is fixed within 1 clock cycle, In FIG. 3, for ease of explanation, it is described that the value is fixed in synchronization with the F / F clock.

Further, 111 and 112 are for explaining the meaning of the signal output from the selector 10.

Before the addition enable 105 rises, F / F
After 8 and 9 are cleared once and the initial value (0) is set,
A clock for one clock is supplied to both F / Fs, and the selection signal
104 flips from'L 'to'H'. Therefore, the initial value i is held in both F / F, and the output of the adder 5 is i + 2j (j: added value)
Then, the output of the adder 7 becomes i + j.

After that, when the addition enable 105 rises, the supply of the clock to the F / Fs 8 and 9 is started, and the selection signal 106 of the double / equal magnification selector 6 is'L 'during the half cycle of the clock when the addition enable 105 rises. It becomes'H 'after that. Therefore, the output of adder 5 (F / F8 hold value) is i + 2j
From i + 4j, i + 6j,… (i + 2mj), the output of adder 7 (F /
The holding value of F9) increases from i + j to i + 3j, i + 5j, ... (i + (2m-1) j).

First, since the selection signal 113 of the selector 10 is'L ', the selector 10 selects the output of the XOR 13 and sets it as the carry output. XOR13 calculates the exclusive OR of the most significant bit of the output of F / F8 and the most significant bit of the output of adder 7. At this time, the output of F / F8 is i and the output of adder 7 is i + j, and if i and i + j have the same highest bit, it is understood that there is no carry from the lower bit.

Similarly, the most significant bits of the mth and m-1th outputs (the outputs of the F / F8 and the adder 7 or the outputs of the adder 5 and the F / F9) are exclusive ORed, By outputting the exclusive OR, it is possible to inform whether or not there is a overflow in the m-th calculation.

The clocks 102 and 103 supplied to both F / Fs are out of phase with each other by a half cycle. Therefore, when this is combined with the output of the adder, a carry output is obtained every half cycle of the clock. Therefore, a carry output can be obtained only once per clock with one F / F, but according to this embodiment, a carry output can be obtained twice per clock.

Although an example in which two adder circuits are operated in parallel has been described above, the present invention is not limited to this, and, for example, three or more adder circuits may be operated in parallel to each other. Even if the adder circuit is caused to perform accumulation at the added value pitch corresponding to the parallel number, it is possible to similarly notify from the mth and m-1th outputs whether or not there is a digit overflow in the mth calculation. .

As described above, according to the present embodiment, when the constant value is added to the initial value and the carry output is obtained, the carry output is taken out an integral multiple times as compared with the normal adder circuit. It is possible to significantly improve the calculation speed.

[0033]

As described above, according to the present invention,
An arithmetic circuit and an arithmetic method for performing high-speed arithmetic can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an arithmetic circuit according to an embodiment of the present invention,

2 is a block diagram showing a configuration example of a double / one-size selector shown in FIG.

FIG. 3 is a timing chart showing an operation example of the present embodiment.

Claims (4)

[Claims] 1. An arithmetic circuit for arithmetically operating two constants, comprising: first arithmetic means for adding an odd multiple of a second constant to the first constant; and the second constant to the first constant. Second arithmetic means for adding an even multiple of a constant, and output means for outputting a carry signal based on the addition result of the first and second arithmetic means, the first and second arithmetic means An arithmetic circuit that operates in parallel. 2. The first arithmetic means adds the second constant to the first constant, and then repeatedly adds twice the second constant to the addition result to obtain the odd number. Accumulating the addition result of double, the second operation means, by repeatedly adding twice the second constant to the first constant, to accumulate the addition result of the even multiple The arithmetic circuit according to claim 1, which is characterized in that. 3. The output means of the first computing means
The result of exclusive ORing the (m-1) th and the most significant bit of the operation result and the most significant bit of the mth operation result of the second operation means is output as a carry signal. The arithmetic circuit described in 2. 4. A calculation method for calculating two constants, comprising: a first calculation step of adding an odd multiple of a second constant to the first constant; and the second constant to the first constant. A second operation step of adding an even multiple of a constant, and an output step of outputting a carry signal based on the addition result of the first and second operation steps, the first and second operation steps An arithmetic method characterized by being executed in parallel.