JP3270659B2 - Arithmetic circuit and arithmetic method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic circuit and an arithmetic method, for example, to an arithmetic circuit and an arithmetic method for calculating two constants.

[0002]

2. Description of the Related Art As means for performing high-speed addition, there is a look-ahead carry circuit that divides an arithmetic circuit into a plurality of circuits, calculates partial sums, and creates a carry from each carry to the next circuit. DDA (Digital Integrator)
Is used in this example when an addition value is added to a certain constant and the carry output is used to process image and audio data.

[0003]

However, the above technique has the following problems.

[0004] When the speed is pursued by the above technique, a circuit for generating a carry that passes from a partial sum to a higher order becomes larger.
For example, when this circuit is to be realized by a C-MOS gate array, the circuit scale becomes large, the wiring length and the chip area become large, so that the capacitive load increases and the speedup is limited.

An object of the present invention is to solve the above-mentioned problem, and an object of the present invention is to provide an arithmetic circuit and an arithmetic method capable of performing high-speed arithmetic.

[0006]

The present invention has the following arrangement as one means for achieving the above object.

An arithmetic circuit according to the present invention is an arithmetic circuit for calculating two constants, the first arithmetic means for adding an odd multiple of the second constant to the first constant, and the first arithmetic means. A second calculating means for adding an even multiple of the second constant to the constant, and an output means for outputting a carry signal based on an addition result of the first and second calculating means, The second operation means operates in parallel.

[0008] The operation method according to the present invention is an operation method for performing an operation of two constants, wherein a first operation step of adding an odd multiple of a second constant to a first constant; A second operation step of adding an even multiple of the second constant to one constant, and an output step of outputting a carry signal based on an addition result of the first and second operation steps, It is characterized in that the first and second operation steps are executed in parallel.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an arithmetic circuit according to an embodiment of the present invention will be described in detail with reference to the drawings.

[Configuration] FIG. 1 is a block diagram showing a configuration example of an arithmetic circuit according to an embodiment of the present invention.

In FIG. 1, reference numeral 11 denotes a control circuit for controlling the sequence of the entire circuit, which is initialized by a reset signal input from the outside.

1 is a latch for storing a first constant (hereinafter referred to as an "initial value"), 2 is a latch for storing a second constant (hereinafter referred to as an "addition value"), and 3 and 4 are two inputs, respectively. A one-output data selector selects and outputs either the initial value stored in the latch 1 or the added value stored in the latch 2 in accordance with a selection signal from the control circuit 11.

Reference numeral 6 denotes a double / single-size selector, which switches the added value output from the selector 4 to one or two according to a selection signal from the control circuit 11.

8 and 9 are flip-flops for holding the accumulated values
(F / F), 5 is an adder for adding the accumulated value held in F / F8 and the data output from selector 3, and 7 is the accumulated value held in F / F9 and output from selector 6. An adder for adding data, 12 is an XOR gate for exclusive-ORing the most significant output of the adder 5 and the most significant output of F / F9, and 13 is the most significant output of the adder 7 and F / F8 This is an XOR gate for taking the exclusive OR of the top output of.

A selector 10 selects one of the outputs of the XOR gates 12 and 13 in accordance with a selection signal from the control circuit 11 and outputs it as a carry for the entire circuit shown in FIG.

[Operation] Next, the operation of the circuit shown in FIG. 1 will be described. Hereinafter, the case of handling n-bit data from the (n-1) th bit to the 0th bit will be described.

The selector 3 inputs the initial value of the n-bit width stored in the latch 1 to the A input, and outputs the n-th to first bits of the added value of the n-bit width stored in the latch 2. Input '0' to the B input as the least significant bit. That is, the added value is input after being shifted left by one bit (doubled). In addition, the selector 4 inputs the initial value of the n-bit width stored in the latch 1 to the B input, and stores the initial value in the latch 2
Input the addition value of n bit width to A input.

FIG. 2 is a block diagram showing an example of the configuration of the double / single-size selector 6. Reference numeral 201 denotes a selection signal S input from the control circuit 11.
And an AND gate 202 for calculating the logical product of the input data A and the (n-1) th bit of the input data A, each of which is a selector, according to the selection signal S,
The bit data (An-1 to A0) input to either the I0 input or the I1 input is selected. 204 is an inverter for inverting the selection signal S, 205 is the 0th bit of the input data and the inverter 20
This is an AND gate that calculates the logical product with the output of 4. This times /
When the selection signal S is “0”, the equal-size selector 6 outputs the input data as it is (actual-magnification operation), and when the selection signal S is “1”, shifts the input data to the left by one bit (doubles). Output (double operation).

The adder 5 to which the output of the F / F 8 and the output of the selector 3 are input is set to an initial value from the (n-1) th bit to the 0th bit which is first output from the selector 3 and to the next output from the selector 3 Since twice the added value is added, the even-numbered added value is accumulated with respect to the initial value. Where F / F8
Is n bits wide and holds the nth to first bits.
The n-th most significant bit indicates an overflow (carry) when the added value is sequentially added to the initial value.

The adder 7 also performs the same addition as the adder 5, except that a value equal to the added value is input first, and a value twice the added value is input thereafter. . That is,
The adder 7 accumulates the odd-numbered added value with respect to the initial value.

Since the F / Fs 8 and 9 hold the outputs of the adders 5 and 7 at the falling edge of the clock, respectively, at the m-th clock from the start of the operation, the F / Fs 8 and 9 That is, we are calculating the (m + 1) th value.
FIG. 3 is a timing chart showing this state.

In FIG. 3, reference numeral 100 denotes a system clock;
Numeral 5 is an enable signal for the arithmetic operation.
This is the signal input to.

Reference numeral 101 denotes a clear signal for the F / Fs 8 and 9, which is cleared when it is 'L'. Reference numeral 102 denotes an F / F8 clock, 103 denotes an F / F9 clock, 104 denotes a selection signal of the selectors 3 and 4, 106 denotes a selection signal of the double / single-size selector 6, and 113 denotes a selection signal of the selector 10. These are signals output by the control circuit 11. The clock 103 rises almost simultaneously with the rise of the addition enable signal 105, and the addition enable signal 105
The clock 104 rises half a cycle after the clock rises, and the selection signal 106 and the selection signal 113 are set.

107 is the output of the selector 3, 108 is the output of the selector 4, 109 is the output of the adder 5, 110 is the output of the adder 7, 111
Is the output of F / F8, and 112 is the output of F / F9. Note that adder 5
Since the outputs of (7) and (7) are not latched, a fixed value is not output unless a certain time has elapsed after the input has changed, but in the present embodiment, it is assumed that the output is fixed within one clock cycle. In FIG. 3, for ease of explanation, it is described that the value is determined in synchronization with the clock of the F / F.

Further, reference numerals 111 and 112 explain the meaning of the signal output from the selector 10.

Before the addition enable 105 rises, the F / F
8 and 9 are cleared once, the initial value (0) is set,
A clock for one clock is supplied to both F / Fs and the selection signal
104 is inverted from 'L' to 'H'. Therefore, the initial value i is held in both F / Fs, and the output of the adder 5 is i + 2j (j: added value)
Then, the output of the adder 7 becomes i + j.

After that, when the addition enable 105 rises, the clock supply to the F / Fs 8 and 9 is started, and the selection signal 106 of the double / single-size selector 6 is set to “L” for a half cycle of the clock at which the addition enable 105 rises. ', And after that it becomes'H'. Therefore, the output of the adder 5 (the value held by F / F8) is i + 2j
, I + 4j, i + 6j,... (I + 2mj), and the output of the adder 7 (F /
F9) increases from i + j to i + 3j, i + 5j,... (I + (2m−1) j).

First, since the selection signal 113 of the selector 10 is “L”, the selector 10 selects the output of the XOR 13 and makes it the carry output. The XOR 13 obtains an exclusive OR of the most significant bit of the output of the F / F 8 and the most significant bit of the output of the adder 7.At this time, the output of the F / F 8 is i and the output of the adder 7 is i. + j, and if the top of i and i + j match, it is understood that there is no carry from the lower bit.

Similarly, the most significant bits of the m-th and (m-1) -th outputs (the output of the F / F 8 and the adder 7 or the output of the adder 5 and the F / F 9) are exclusive-ORed, and By outputting an exclusive OR, it can be notified whether or not an overflow has occurred in the m-th calculation.

Since the clocks 102 and 103 supplied to both F / Fs are out of phase by a half cycle, when this is combined with the output of the adder, a carry output is obtained every half cycle of the clock. Accordingly, a carry output can be obtained only once per clock in one F / F, but according to the present embodiment, a carry output can be obtained twice in one clock.

In the above description, an example in which two adder circuits are operated in parallel has been described. However, the present invention is not limited to this. For example, three or more adder circuits are operated in parallel, Even if you let the adder perform accumulation at the added value pitch that is twice as many as the parallel number, you can also inform the m-th and m-1 outputs if there is an overflow in the m-th calculation. .

As described above, according to the present embodiment, when a fixed constant is added to an initial value and a carry output is obtained, a carry output is taken out an integral number of times as compared with a normal addition circuit. And the calculation speed can be remarkably improved.

[0033]

As described above, according to the present invention,
An operation circuit and an operation method for performing high-speed operation can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of an arithmetic circuit according to an embodiment of the present invention;

FIG. 2 is a block diagram showing a configuration example of a double / actual-size selector shown in FIG. 1;

FIG. 3 is a timing chart showing an operation example of the embodiment.

Claims (4)

(57) [Claims] 1. An arithmetic circuit for performing an operation of two constants, comprising: first operation means for adding an odd multiple of a second constant to a first constant; and a second operation means for adding the second constant to the first constant. A second operation unit for adding an even multiple of a constant, and an output unit for outputting a carry signal based on an addition result of the first and second operation units, wherein the first and second operation units are An arithmetic circuit which operates in parallel. 2. The first arithmetic means adds the second constant to the first constant, and repeatedly adds twice the second constant to the addition result, thereby obtaining the odd number. Accumulating the doubled addition result, wherein the second operation means accumulates the even-numbered addition result by repeatedly adding twice the second constant to the first constant. The arithmetic circuit according to claim 1, wherein: 3. The output means according to claim 1, wherein
An exclusive OR operation of the (m-1) th and the most significant bit of the operation result and the most significant bit of the (m) th operation result of the second operation means, and outputs a result as a carry signal. The arithmetic circuit described in 2. 4. An operation method for performing an operation of two constants, wherein a first operation step of adding an odd multiple of a second constant to a first constant; A second operation step of adding an even multiple of a constant, and an output step of outputting a carry signal based on the addition result of the first and second operation steps, wherein the first and second operation steps An arithmetic method characterized by being executed in parallel.