JP2001034457A - Adding and subtracting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an adding and subtracting circuit for causing no decrease of a system clock speed by reducing the number of gates between the input and output of a signal. SOLUTION: This adding circuit 10 is provided with a first holding circuit 11 for holding the bit string of an augend X, a second holding circuit 12 for holding the bit string of an addend Y, a carrier signal generating circuit 15 for successively inputted each bit string held in the first and second holding circuits from the least significant bit synchronously with a prescribed synchronizing signal, and for generating a carry signal being transited to a first state when both the inputted bits are 1, and to a second state when both the inputted signals are 0, an exclusive logical sum circuit 14 for inputting the carry signal and each bit in the next stage of the bits being the basis of the carry signal in the first and second holding circuits and for outputting the exclusive OR thereof, and a third holding circuit 13 for holding a bit string outputted from the exclusive logical sum circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital signal addition / subtraction circuit.

[0002]

2. Description of the Related Art In communication devices and computers, addition and subtraction operations are essential for digital signal processing. FIG. 8 shows a general addition circuit constituted by gates. The addition circuit 80 uses the exclusive OR (XOR) of each bit to be added as an addition result, and outputs a carry as a carry to the next stage when both bits are 1s. As a circuit configuration, a half adder that carries a logical product (AND) of both bits shown in FIG. 9A and a full adder that performs addition including the carry from the preceding stage shown in FIG. 9B Is configured by combining

On the other hand, a subtraction circuit is generally realized by using an addition circuit. That is, subtraction AB of inputs A and B
Can be realized by an addition process by using a complement as in the following equation.

A−B = A + not B + 1

[0005] Here, not B represents bit inversion of all bits of B.

[0006]

However, in the above-mentioned addition circuit, since the addition in the upper bit is performed by adding the result of the carry in the lower bit, a multi-stage gate is provided between the input and output of the addition circuit. Will enter. The number of stages of this gate increases as the number of input bits increases.

An FPGA (Field Prog) constituting an adder circuit
In a ramable gate array, a delay of about several ns per gate occurs. Therefore, when the addition or subtraction processing is performed using an addition circuit having a large number of input bits, there is a problem that the delay between registers increases and the clock speed of the system decreases.

Accordingly, it is an object of the present invention to provide an adder circuit which does not reduce the system clock speed by reducing the number of gates between signal input and output.

It is another object of the present invention that the subtraction of an input signal can be calculated without using its complement.
An object of the present invention is to provide a subtraction circuit having a high operation speed.

Another object of the present invention is to provide an addition / subtraction circuit which can perform addition and subtraction of input signals and has a high operation speed.

[0011]

To achieve the above object, an adder circuit according to the present invention comprises a first holding circuit for holding a bit string of an augend X and a second holding circuit for holding a bit string of an addend Y. Circuit, and the bit strings held in the first and second holding circuits are sequentially input from the least significant bit in synchronization with a predetermined synchronization signal, and when both of the input bits are 1, A carry signal generating circuit for generating a carry signal which is transited to a first state and which is transited to a second state when both of the inputted signals are 0, the carry signal; Inputting each bit of the next stage of the bit on which the carry signal is based in the holding circuit of No. 2;
An exclusive OR circuit that outputs the exclusive OR,
A third holding circuit for holding a bit string output from the exclusive OR circuit.

Further, the subtraction circuit of the present invention comprises a first holding circuit for holding a bit string of the minuend X, and a subtraction Y (where X
> Y), and the respective bit strings held in the first and second holding circuits are sequentially input from the least significant bit in synchronization with a predetermined synchronization signal. Of the input bits, the bit from the first holding circuit is 0, and the bit from the second holding circuit is 1
, The state is transited to the first state, and when the bit from the first holding circuit is 1 in the input signal and the bit from the second holding circuit is 0, A borrow signal generating circuit for generating a borrow signal to be transitioned to a state, and inputting the borrow signal and each bit of a stage next to the bit on which the borrow signal is based in the first and second holding circuits. , An exclusive-OR circuit for outputting these exclusive-ORs, and a third holding circuit for holding a bit string output from the exclusive-OR circuit.

Further, the addition / subtraction circuit of the present invention comprises a first holding circuit for holding a bit string of the number X, and a number Y (where X>
Y) a second holding circuit for holding the bit string;
And a selector for outputting the bit sequence from the negation circuit based on the command signal for addition and outputting the bit sequence from the first storage circuit based on the command signal for subtraction. And when the bit strings from the selector and the second holding circuit are sequentially input from the least significant bit in synchronization with a predetermined synchronization signal, and when the addition of the numbers X and Y is performed, the input bits When both are 1, the state is transited to the first state, when both of the input signals are 0, the state is transited to the second state, and when subtracting Y from the number X, When the bit from the selector among the input bits is 0,
When the bit from the second holding circuit is 1, the first
And a signal that generates a signal that is shifted to the second state when the bit from the selector is 1 and the bit from the second holding circuit is 0 in the input signal. An exclusive OR that inputs a generation circuit, the signal, and each bit of a stage next to the bit on which the signal is based in the first and second holding circuits, and outputs an exclusive OR of these And a third holding circuit for holding a bit string output from the exclusive OR circuit.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on one embodiment shown in the drawings. FIG. 1 is a block diagram of an adding circuit according to an embodiment of the present invention. As shown in the figure, an adder circuit 10 includes two registers 11 and 12 for holding two numbers to be added, that is, an augend X and an addend Y, a register 13 for holding an addition result Z, and an addition of input signals. , A synchronous latch 15 for generating a carry signal, a logic circuit 16 for latch setting, and a logic circuit 17 for latch reset.

The registers 11 and 12 are shift registers, each of which stores a bit string stored in synchronization with a clock signal.
Shift right by bit, and the least significant bit (LSB)
Output in order.

The XOR circuit 14 receives the bit of the augend X from the register 11, the bit of the addend Y from the register 12, and the carry signal from the synchronous latch 15, and outputs the result of exclusive ORing them. Output. The bits sequentially output from the XOR circuit 14 are accumulated in the register 13, and when the operation on all the bits is completed, the register 13 stores the result Z obtained by adding X and Y.

The synchronous latch 15 is for generating a carry signal when the bit strings of the numbers X and Y are added.
When a carry occurs during the addition, the transition is made to 1 based on the set signal, and when both of the addition bits are 0, the transition is made to 0 based on the reset signal. A logic circuit 16 that generates a set signal for the synchronous latch 15 is configured by an AND circuit connected to the registers 11 and 12, and outputs a logical product of input bits as a set signal for the synchronous latch 15. That is, the logic circuit 16 outputs 1 when the bits from both registers are 1 and sets the synchronous latch 15 to transition the output carry signal to 1. On the other hand, the logic circuit 17 for generating the reset signal of the synchronous latch 15 is constituted by an AND circuit having NOT circuits at both input terminals thereof, and the logical product of the inverted bits of the registers 11 and 12 is synchronously calculated. This is output as a reset signal for the latch 15. That is, the logic circuit 17
Outputs 1 when the bits from both registers are 1, resets the synchronous latch 15 and changes its output carry signal to 0.

Next, the operation of the adding circuit 10 will be described with reference to the timing chart shown in FIG. In FIG.
Output bits X_LSB and Y_LS from registers 11 and 12
B, output signals FIND_11 and FIND_0 of the logic circuits 16 and 17
0, output carry signal CARRY and XO of synchronous latch 15
The output signal OUT of the R circuit 14 is shown. Hereinafter, the augend X “10111001101100” stored in the register 11
The operation of the adder circuit 10 according to the present invention will be described along with an example of adding the addend Y “01001111100000” stored in the register 12.

As shown in the figure, carry signal CARRY is
Initially reset to zero. Each bit from the registers 11 and 12 is sequentially input to the XOR circuit 14 and the logic circuits 16 and 17 in synchronization with the clock signal. First four
Regarding the bit, any of X_LSB and Y_LSB is 0, so no carry occurs, and the carry signal CARRY of the synchronous latch 15
Is left at 0, and the XOR circuit 14 outputs X_LSB, Y_LSB
Is output to the register 13 as the addition result OUT. In the next bit, X_LSB and Y_LSB are both 1
Therefore, the logic circuit 16 detects this, and the FIND_11 signal transitions to 1. As a result, the synchronous latch 15
Is the output carry signal CA at the next rising of the clock signal.
Transition RRY to 1. This state is maintained until the reset signal is input to the synchronous latch 15. The carry signal is input to the XOR circuit 14, where the next X_LSB, Y
An exclusive OR operation with _LSB is performed, and the operation result is output to the register 13.

In the tenth bit of the input signal, X_LSB
When both 0 and Y_LSB are provided with 0, the logic circuit 17 detects this, and the FIND_00 signal transitions to 1. As a result, the synchronous latch 15 changes the carry signal CARRY to 0 at the next rising edge of the clock signal. In this input signal, since both bits do not become 1 in subsequent bits, this state is maintained until the last bit. As described above, the operation result Z of the addend X and the addend Y
Is stored in the register 13.

Next, a subtraction circuit according to an embodiment of the present invention will be described. FIG. 3 is a block diagram of a subtraction circuit according to one embodiment of the present invention. As shown in the figure, the subtraction circuit 30 includes two registers 31 and 32 for holding two numbers to be subtracted, that is, a minuend X and a subtrahend Y, and a subtraction result Z.
33, an XOR circuit 34 for performing an exclusive OR of input signals, a synchronous latch 35 for generating a borrow signal, a logic circuit 36 for latch setting, and a logic circuit 37 for latch reset. Is done.

Each of the registers 31 and 32 is a shift register, and stores a bit string stored in synchronization with a clock signal into one.
Shift right by bit, and the least significant bit (LSB)
Output in order. In the subtraction circuit, the register 31
Is the minuend X stored in the register 32.
Must be greater than X> Y.

The XOR circuit 34 receives the bit of the minuend X from the register 31, the bit of the minuend Y from the register 32, and the borrow signal from the synchronous latch 35, and outputs the result of exclusive ORing them. The bits sequentially output from the XOR circuit 34 are accumulated in the register 33, and when the operation for all the bits is completed, the result 33 obtained by subtracting X and Y is stored in the register 33.

The synchronous latch 35 is used to generate a borrow signal when the bit strings of the numbers X and Y are subtracted. When a carry occurs during the subtraction, the latch changes to 1 based on the set signal. In addition, when the bit from the register 31 is 1 and the bit from the register 32 is 0, a transition is made to 0 based on the reset signal. A logic circuit 36 for generating the set signal of the synchronous latch 35 is connected to the registers 31 and 32 and is constituted by an AND circuit having a NOT circuit at the input end of the register 31. It is output as 15 set signals. That is, the logic circuit 36 outputs 1 when the bit from the register 31 is 0 and the bit from the register 32 is 1, sets the synchronous latch 35, and changes the output borrow signal to 1. On the other hand, the logic circuit 37 for generating the reset signal of the synchronous latch 35 is constituted by an AND circuit having a NOT circuit at the input end of the register 32, and outputs the logical product of the input bits as the reset signal of the synchronous latch 35. I do. That is, the logic circuit 37 includes the register 31
When the bit from is 1 and the bit of the register 32 is 0, 1 is output, and the synchronous latch 35 is reset to change its output borrow signal to 0.

Next, the operation of the subtraction circuit 30 will be described with reference to the timing chart shown in FIG. In FIG.
Output bits X_LSB and Y_LS from registers 31 and 32
B, output signals FIND_01 and FIND_1 of the logic circuits 36 and 37
0, output borrow signals BORROW and XO of synchronous latch 35
The output signal OUT of the R circuit 34 is shown. Hereinafter, the subtrahend X “10111001101100” stored in the register 31 is converted to the subtrahend Y “0100111110000” stored in the register 32.
According to the example of subtracting “0”, the subtraction circuit 30 according to the present invention is used.
Will be described.

As shown in the figure, the borrow signal BORROW is initially reset to zero. Each bit from the registers 31 and 32 is sequentially input to the XOR circuit 34 and the logic circuits 36 and 37 in synchronization with the clock signal. Regarding the first bit, since Y_LSB is 0, no carry-down occurs, and the borrow signal BORROW of the synchronous latch 35 remains 0,
In the XOR circuit 34, the exclusive OR of X_LSB and Y_LSB is output to the register 33 as the subtraction result OUT. In the next bit, since X_LSB is 0 and Y_LSB is 1,
The logic circuit 36 detects this, and the FIND_01 signal transitions to 1. Thus, the synchronous latch 35 changes the output borrow signal BORROW to 1 at the next rising of the clock signal. This state is maintained until the reset signal is input to the synchronous latch 35. The borrow signal is input to the XOR circuit 34, where it is subjected to an exclusive OR operation with the next X_LSB and Y_LSB, and the result is output to the register 33.

In the third bit of the input signal, when 1 is given to X_LSB and 0 is given to Y_LSB, the logic circuit 37
Detects this, and the FIND_10 signal transits to 1. Accordingly, the synchronous latch 35 changes the borrow signal BORROW to 0 at the next rising edge of the clock signal. Similarly,
When 0 is given to X_LSB and 1 is given to Y_LSB at the sixth bit of the input signal, the synchronous latch 35 outputs the borrow signal BORR.
OW transitions to 1, which means that X_
It is maintained until 1 is given to LSB and 0 is given to Y_LSB, and transitions to 0 at the next rise of the clock signal. As described above, the calculation result Z of the minuend X and the subtrahend Y
Is stored in the register 33.

Next, an adding / subtracting circuit according to an embodiment of the present invention will be described. FIG. 5 is a block diagram of an addition / subtraction circuit according to one embodiment of the present invention. As shown in the figure, an addition / subtraction circuit 50 includes two registers 51 and 52 for holding two numbers X and Y to be added / subtracted, a register 53 for holding a result Z of addition / subtraction, and an XOR circuit for performing exclusive OR of an input signal. 54, a synchronous latch 55 for generating a carry or borrow signal, a logic circuit 56 for latch set, a logic circuit 57 for latch reset, a selector 58 and a NOT circuit 59. That is, the addition / subtraction circuit 5
0 indicates that the selector 58 and N
This is configured by adding an OT circuit 59.

The selector 58 is provided between the register 51 and the logic circuit 56, and supplies the input bit of the register 51 or its inverted bit to the logic circuit 58. The selector 58 is controlled by the AS_SEL signal and is switched before execution of the operation. That is, when performing addition,
The AS_SEL signal is set to 0, the signal from the NOT circuit 59 (the inverted bit of the register 51) is supplied to the logic circuit 58, and when the subtraction is executed, the AS_SEL signal is set to 1 and the register 51 is set.
Is applied to the logic circuit 58. The other components are the same as the components of the subtraction circuit 30 described above, and a description thereof will be omitted. Here, the output signal DIGIT_UD of the synchronous latch 55 functions as a carry signal when performing addition in the present addition / subtraction circuit, and functions as a borrow signal when performing subtraction.

Next, the operation of the addition / subtraction circuit 50 will be described with reference to FIG.
And a timing chart shown in FIG.
FIGS. 6 and 7 are timing charts for the case of addition (AS_SEL = 0) and the case of subtraction (AS_SEL = 1), respectively, in which the output bits X_LS from the registers 51 and 52 are shown.
B and Y_LSB, output bit X_IN of selector 58, output signals ON and OFF of logic circuits 56 and 57, synchronous latch 55
Output signal DIGIT_UD and the output signal OUT of the XOR circuit 54
It is shown. First, the operation of the addition / subtraction circuit 50 according to the present invention will be described along with an example of adding the augend X “10111001101100” stored in the register 51 and the addend Y “01001111100000” stored in the register 52. .

As shown in FIG. 6, the output signal DIGIT_UD of the synchronous latch 55 is first reset to 0, and the AS_SEL signal of the selector 58 is set to 0. Each bit from the registers 51 and 52 is sequentially input to the XOR circuit 54 and the logic circuit 57 in synchronization with the clock signal. The input signal X_IN to the logic circuit 56 is turned into an inverted bit of the register 51 by the selector 58. Regarding the first four bits, any one of X_LSB and Y_LSB is 0, so no carry occurs, the output signal DIGIT_UD of the synchronous latch 55 remains 0, and the XOR circuit 54 outputs the exclusive logic of X_LSB and Y_LSB. The sum is output to the register 53 as the addition result OUT. In the next bit, X_IN is 0 and Y_LSB is 1
Therefore, the logic circuit 56 detects this, and the ON signal becomes 1
Is transited to. As a result, the synchronous latch 55 changes the output signal DIGIT_UD to 1 at the next rise of the clock signal. This state is maintained until the reset signal is input to the synchronous latch 55. The signal DIGIT_UD is XOR
The signal is input to the circuit 54, where it is subjected to an exclusive OR operation with the next X_LSB and Y_LSB, and the operation result is output to the register 53.

In the tenth bit of the input signal, X_LSB
When 0 (X_IN becomes 1) is given to both of the signals and Y_LSB, the logic circuit 57 detects this and the OFF signal is transited to 1. As a result, the synchronous latch 55 changes the output signal DIGIT_UD to 0 at the next rise of the clock signal. In this input signal, since both bits do not become 1 in subsequent bits, this state is maintained until the last bit. As described above, the addend X and the addend Y
Is accumulated in the register 53.

Next, the minuend X stored in the register 51
The operation of the addition / subtraction circuit 50 according to the present invention will be described along an example of subtracting the subtraction Y “01001111100000” stored in the register 52 from “10111001101100”.

As shown in FIG. 7, the output signal DIGIT_UD of the synchronous latch 55 is first reset to 0, and the AS_SEL signal of the selector 58 is set to 1. Each bit from the registers 51 and 52 is sequentially input to the XOR circuit 54 and the logic circuits 56 and 57 in synchronization with the clock signal. The input signal X_IN to the logic circuit 56 is supplied to the selector 58
As a result, the signal of the register 51 remains unchanged. Regarding the first bit, since Y_LSB is 0, no carry-down occurs, the output signal DIGIT_UD of the synchronous latch 55 remains 0, and the XOR circuit 54 calculates the exclusive OR of X_LSB and Y_LSB as the subtraction result OUT. Is output to the register 53. In the next bit, since X_IN is 0 and Y_LSB is 1, the logic circuit 56 detects this, and the ON signal transits to 1. As a result, the synchronous latch 55 changes the output signal DIGIT_UD to 1 at the next rise of the clock signal. This state is maintained until the reset signal is input to the synchronous latch 55. The signal DIGIT_UD is input to the XOR circuit 54, where it is subjected to an exclusive OR operation with the next X_LSB, Y_LSB, and the result is output to the register 53.

In the third bit of the input signal, X_LSB (=
When 1 is given to (X_IN) and 0 is given to Y_LSB, the logic circuit 57 detects this, and the OFF signal is changed to 1.
As a result, the synchronous latch 55 changes the output signal DIGIT_UD to 0 at the next rise of the clock signal. Similarly, at the sixth bit of the input signal, 0 is given to X_LSB and Y_L
When 1 is given to SB, the synchronous latch 55 outputs the output signal DI.
GIT_UD transitions to 1, which is maintained until X_LSB is set to 1 and Y_LSB is set to 0 at the 11th bit of the input signal, and is changed to 0 at the next rising edge of the clock signal. As described above, the operation result Z of the minuend X and the subtrahend Y is accumulated in the register 53.

The embodiment of the present invention has been described with reference to the drawings. However, it is apparent that the present invention is not limited to the matters described in the above embodiments, and that changes, improvements, and the like can be made based on the description in the claims.

[0037]

As described above, according to the present invention, in the addition / subtraction circuit, the number of gates between the input and output of signals is reduced, so that the system clock speed does not decrease.

Further, according to the present invention, the circuit scale of the addition / subtraction circuit can be made extremely small regardless of the number of bits of the input signal.

[Brief description of the drawings]

FIG. 1 is a block diagram of an adding circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of the adding circuit of FIG. 1;

FIG. 3 is a block diagram of a subtraction circuit according to one embodiment of the present invention.

FIG. 4 is a timing chart of the subtraction circuit of FIG. 3;

FIG. 5 is a block diagram of an addition / subtraction circuit according to an embodiment of the present invention.

6 is a timing chart in the case of an addition operation in the addition / subtraction circuit of FIG. 5;

FIG. 7 is a timing chart in the case of a subtraction operation in the addition / subtraction circuit of FIG. 5;

FIG. 8 is a block diagram of a conventional addition / subtraction circuit.

9 is a block diagram of (A) a half adder and (B) a full adder which constitute the addition / subtraction circuit of FIG. 8;

[Explanation of symbols]

 Reference Signs List 10 adder circuit 11-13 register 14 XOR circuit 15 synchronous latch 16, 17 logic circuit 30 subtraction circuit 31-33 register 34 XOR circuit 35 synchronous latch 36, 37 logic circuit 50 addition / subtraction circuit 51-53 register 54 XOR circuit 55 synchronous Expression latch 56, 57 Logic circuit 58 Selector 59 NOT circuit

Claims (3)

[Claims] 1. A first holding circuit for holding a bit string of an augend X, a second holding circuit for holding a bit string of an augend Y, and each of the first and second holding circuits held in the first and second holding circuits. A bit string is sequentially input from the least significant bit in synchronization with a predetermined synchronization signal, and when both of the input bits are 1, a transition is made to the first state, and both of the input signals are 0. And a carry signal generation circuit that generates a carry signal that transits to the second state when the carry signal is generated, and the carry signal and a bit next to the bit on which the carry signal is based in the first and second holding circuits. An exclusive OR circuit that inputs each bit of the stage and outputs an exclusive OR thereof, and a third holding circuit that holds a bit string output from the exclusive OR circuit. Addition circuit characterized. 2. A first holding circuit for holding a bit string of a minuend X, a second holding circuit for holding a bit string of a decrement Y (where X> Y), and The held bit strings are sequentially input from the least significant bit in synchronization with a predetermined synchronization signal, and when the bit from the first holding circuit is 0 among the input bits, the second holding circuit Is transitioned to the first state when the bit from is 1, and the bit from the first holding circuit in the input signal is 1,
When the bit from the second holding circuit is 0, the second
A borrow signal generation circuit that generates a borrow signal that is transitioned to the state described above, and inputs the borrow signal and each bit of a stage next to the bit on which the borrow signal is based in the first and second holding circuits. A subtraction circuit, comprising: an exclusive-OR circuit that outputs the exclusive-OR, and a third holding circuit that holds a bit string output from the exclusive-OR circuit. 3. A first holding circuit for holding a bit string of a number X, a second holding circuit for holding a bit string of a number Y (where X> Y), and a bit string from the first holding circuit. An inverting circuit for inverting, a selector for outputting a bit string from the negating circuit based on an instruction signal for addition, and outputting a bit string from the first holding circuit based on an instruction signal for subtraction; 2 are sequentially input from the least significant bit in synchronization with a predetermined synchronization signal, and when adding the numbers X and Y, when both of the input bits are 1 To the first state, and to the second state when both of the input signals are 0, and to perform the subtraction of Y from the number X, Bits from the selector 0, the second bit from the holding circuit is a transition to the first state when it is 1, bits from the selector of the input signal is 1, the second
A signal generation circuit that generates a signal that is transitioned to a second state when a bit from the holding circuit is 0, and the signal and the signal in the first and second holding circuits are formed. An exclusive-OR circuit that inputs each bit of the next stage of the bit and outputs an exclusive-OR thereof, and a third holding circuit that holds a bit string output from the exclusive-OR circuit. An addition / subtraction circuit, comprising: