JP2004234110A - Parity prediction circuit for full adder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To construct a parity prediction circuit of a full adder from a small number of inputs and a small number of elements. <P>SOLUTION: The parity prediction circuit has computing units, each with a first selector which receives the inputs of carry four parity CP [k-1, 0] and CP [k-1, 1] when carry-in Cin=0 and 1 (k is an integer of not more than n) and which outputs either the input CP [k-1, 0] or CP [k-1, 1] as a carry four parity cp [k, 0] according to a generation bit g[k-2] resulting from addition inputs A[k-2] and B[k-2], and a second selector which receives the inputs of the carry four parity CP [k-1, 0] and CP [k-1, 1] and which outputs either the input CP [k-1, 0] or CP [k-1, 1] as an inverted signal of the carry four parity cp [k, 1] according to a propagation bit p [k-2] resulting from the addition inputs A[k-2] and B[k-2]. The computing units are interconnected in a plurality of rows, and either the carry four parity cp [n, 0] or cp [n, 1] is output as a carry four parity CPn according to the carry in Cin at the final selector. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

即ち、最下位ビット（第３ビット）へのキャリーインｃ［３］は、下位からのキャリインＣｉｎである（式（１））。また、次の第２ビットへのキャリーインｃ［２］は、最下位ビットのジェネレーションｇ［３］がｇ［３］＝１か、プロパゲーションｐ［３］がｐ［３］＝１で且つキャリーインＣｉｎがＣｉｎ＝１の時に発生する（式（２））。更に、第１ビットへのキャリーインｃ［１］は、第２ビットのジェネレーションｇ［２］がｇ［２］＝１か、プロパゲーションｐ［２］がｐ［２］＝１でありかつ第２ビットへのキャリーインｃ［２］がｃ［２］＝１の時に発生する（式（３））。この式（３）に式（２）を代入すると、上記式（４）が求められる。
【００２４】
同様に、第０ビット（最上位ビット）へのキャリーインｃ［０］は、第１ビットのジェネレーションｇ［１］がｇ［１］＝１か、プロパゲーションｐ［１］がｐ［１］＝１でありかつ第１ビットへのキャリーインｃ［１］がｃ［１］＝１の時に発生する（式（５））。この式（５）に式（４）を代入すると、上記式（６）が求められる。
【００２５】
上記から理解されるとおり、キャリーインの一般式は、次の通りである。
【００２６】
ｃ［ｎ］＝ｇ［ｎ＋１］ ｜ （ｐ［ｎ＋１］ ・ ｃ［ｎ＋１］））
従って、キャリーアウト生成回路１２は、次の演算式の論理回路で構成される。
【００２７】
Ｃｏｕｔ＝ｇ［０］ ｜ （ｐ［０］ ・ ｃ［０］））
さて、加算値とキャリーアウトを求める回路と共に、入力データＡ，Ｂのパリティビットから予測パリティビットを求める回路が設けられる。この回路は、ＣＰ（Ｃａｒｒｙ ｆｏｒ Ｐａｒｉｔｙ）生成回路１８と、予測パリティ生成回路１４とからなる。入力データＡ，ＢのパリティビットＡ［Ｐ］、Ｂ［Ｐ］の不良の有無を示す情報をそのまま加算値ＳのパリティビットＳ［Ｐ］にも伝播させる予測パリティビットＳ［Ｐ］は、次の演算式で求められることが知られている。
【００２８】
Ｓ［Ｐ］ ＝ Ａ［Ｐ］ ｖ Ｂ［Ｐ］ ｖ ＣＰ４ （７）
ここで、ＣＰ４は、各ビット（各桁）での桁上げによるパリティビットへの影響を示すビットであり、キャリーフォーパリティ（パリティビットのキャリー）と称される。このキャリーフォーパリティＣＰ４は、各ビット（各桁）へのキャリーインｃ［０］，ｃ［１］，ｃ［２］，ｃ［３］が何回発生したかを示すビットであり、次の一般的に知られた演算式により求められる。
【００２９】
ＣＰ４ ＝ ｃ［０］ ｖ ｃ［１］ ｖ ｃ［２］ ｖ ｃ［３］ （８）
つまり、排他的論理和ｖは、「１」の時反転し、「０」の時反転しないことと等価であるので、結局、キャリフォーパリティＣＰ４は、各桁へのキャリーインの回数が奇数（ＣＰ４＝０）か偶数（ＣＰ４＝１）かを示すビットデータである。
【００３０】
上記式（８）に上記式（１）（２）（４）（６）をそれぞれ代入して展開すると、次の通りである。
【００３１】
ＣＰ４ ＝ ［（ｇ［１］ ・ 〜ｇ［２］ ・ 〜ｇ［３］） ｜ （〜ｐ［１］ ・ ｇ［２］ ・ 〜ｇ［３］） ｜
（〜ｇ［１］ ・ 〜ｐ［２］ ・ ｇ［３］） ｜ （ｐ［１］ ・ ｐ［２］ ・ ｇ［３］）］ ： ｉｆ Ｃｉｎ ＝ ０
［（〜ｇ［１］ ・ 〜ｇ［２］ ・ 〜ｐ［３］） ｜ （ｐ［１］ ・ ｇ［２］ ・ 〜ｐ［３］） ｜
（ｇ［１］ ・ 〜ｐ［２］ ・ ｐ［３］） ｜ （〜ｐ［１］ ・ ｐ［２］ ・ ｐ［３］）］ ： ｉｆ Ｃｉｎ ＝ １ （９）
この演算式（９）は、キャリーインＣｉｎが「０」の場合と「１」の場合とに区分して構成されているが、それぞれの演算式は、前段階で生成されるジェネレーションｇとプロパゲーションｐの反転、非反転ビットを入力とする論理回路で構成可能である。この演算式は、一般的に知られている。
【００３２】
図２は、キャリーフォーパリティ生成回路１８の論理回路図である。この論理回路図は、演算式（９）をそのまま論理回路に展開している。即ち、ＮＡＮＤゲート２０〜２３とそれらの出力のＮＡＮＤゲート２４とで、ＡＮＤ回路とＯＲ回路とが生成され、演算式（９）のＣｉｎ＝０の場合の項が演算される。また、ＮＡＮＤゲート２５〜２８とそれらの出力のＮＡＮＤゲート２９とで、ＡＮＤ回路とＯＲ回路とが生成され、演算式（９）のＣｉｎ＝１の場合の項が演算される。そして、セレクタ３０が、ゲート２４，２９の出力を、Ｃｉｎ＝１の時とＣｉｎ＝０の時とに応じて、選択する。
【００３３】
図２のキャリーフォーパリティ生成回路１８は、演算式（９）をそのまま論理回路に展開した構成になっている。この生成回路１８は、３入力のゲート２０〜２３、２５〜２８を８個、４入力のゲート２４，２９を２個、そして、セレクタ３０を有する。３入力のＮＡＮＤゲートは、ＣＭＯＳ回路で構成されると６トランジスタを必要とする。また、４入力のＮＡＮＤゲートは、ＣＭＯＳ回路で構成されると８トランジスタを必要とする。従って、図２の回路では、ＮＡＮＤゲートだけで６４個のトランジスタを必要とし、セレクタ３０が４トランジスタで構成されるとすると、全部で６８個のトランジスタを必要とする。これが６ビット、８ビットと入力データのビット数が大きくなると、そのトランジスタの個数は指数関数的に増大することになり、高集積化を阻害する要因になる。
【００３４】
そこで、本発明者は、パストランジスタ回路のみによるキャリーフォーパリティ生成回路を新たに発明した。パストランジスタとは、逆相のコントロールビットに応じて、２つの入力の一方を選択するセレクタであり、ＣＭＯＳ回路で構成すると、逆相のコントロールビットが使用可能状態であれば、４個のトランジスタで実現できる。
【００３５】
図３は、ＣＭＯＳ回路で構成されたパストランジスタの回路図の一例を示す図である。パストランジスタ回路は、一種のセレクタであり、制御信号Ｓが「１」の時に入力Ａを出力Ｘとして選択し、制御信号Ｓが「０」の時に入力Ｂを出力Ｘとして選択する。第１のトランスファーゲートを構成するＮチャネルトランジスタＮ１とＰチャネルトランジスタＰ１は、制御信号ＳがＨレベル（Ｓ＝１）の時に入力Ａを通過させる。また、第２のトランスファーゲートを構成するＮチャネルトランジスタＮ２とＰチャネルトランジスタＰ２は、制御信号ＳがＬレベル（Ｓ＝０）の時に入力Ｂを通過させる。そこで、このようなパストランジスタ回路で構成されるセレクタＳＥＬを、図３に示されるように表記することにする。
【００３６】
そして、出力Ｘの演算式として、次のような表記を採用することにする。
【００３７】
Ｘ＝（Ｓ・Ａ）｜（〜Ｓ・Ｂ）＝Ｓ＜Ａ，Ｂ＞ （１０）
この演算式は、Ｘが、Ｓ＝１のときにＡ、Ｓ＝０のときにＢであることを示す。
この演算式は、入力Ａ，Ｂ、制御信号Ｓからなるセレクタに対応する。
【００３８】
そこで、キャリーフォーパリティＣＰを求める演算式を、上記の演算式（１０）を利用して表記することで、図３のパストランジスタ回路によるセレクタを利用してキャリーフォーパリティ発生回路１８を構成することができる。
【００３９】
更に新たな表記方法として、ｎビットに対するキャリーフォーパリティＣＰｎを、下位からのキャリインＣｉｎ＝０ｏｒ１に対して、ｃｐ［ｎ，０］、ｃｐ［ｎ，１］と表すことにする。こうすることにより、次のように式（１０）の形式で表すことができる。
【００４０】
ＣＰｎ＝Ｃｉｎ＜ｃｐ［ｎ，１］，ｃｐ［ｎ，０］＞ （１１）
この式は、前述の式１０と同等であり、図３のパストランジスタ回路により実現可能である。
【００４１】
図４は、キャリーフォーパリティを説明する図である。図４を参照しながら、１ビット〜４ビット及びｎビットに対するキャリーフォーパリティＣＰ１〜ＣＰ４、ＣＰ４について説明すると共に、その再帰性について説明する。ｎビットに対しては、最上位を第０ビット、最下位を第ｎ−１ビットとしたことに伴い、図４では、ビット数が増加するたびに第１ビット、第２ビット、第３ビット．．．第ｎ−１ビットと最下位ビットが付加されるように表記される。このように表記することで、キャリーフォーパリティの再帰性の説明が容易になる。
【００４２】
図４（１）は１ビット（１桁）の場合であり、１ビットの場合は、前述の式８に示したとおり、キャリーフォーパリティＣＰ１は、下位からのキャリーＣｉｎがあるかないかによって決まる。つまり、ＣＰ１＝ｃ［０］＝Ｃｉｎであるので、結局、１桁の場合のキャリーフォーパリティＣＰ１は、次の式群（１２）の通りである。
【００４３】
ＣＰ１＝Ｃｉｎ＜ｃｐ［１，１］，ｃｐ［１，０］＞＝Ｃｉｎ＜１，０＞
ｃｐ［１，０］ ＝０
ｃｐ［１，１］ ＝１ （１２）
図４（２）は２ビット（２桁）の場合である。２ビットの場合は、１ビットの第０桁に対してキャリーが発生するか否かと考えることにより、２ビットのキャリーフォーパリティＣＰ２を１ビットのキャリーフォーパリティＣＰ１のｃｐ［１，１］，ｃｐ［１，０］を利用して表現することができる。つまり、キャリーインＣｉｎ＝０の場合は、最下位の第１ビットにキャリー（桁上げ）が発生するか否かを示すジェネレーションｇ［１］が、上位の１ビット（第０ビット）に対するキャリーインＣｉｎに対応するので、
ｃｐ［２，０］＝ｇ［１］＜ｃｐ［１，１］，ｃｐ［１，０］＞
更に、キャリーインＣｉｎ＝１の場合は、そのキャリーインによる最下位の第１ビットでの反転と、最下位の第１ビットのプロパゲーションｐ［１］が、上位の１ビット（第０ビット）に対するキャリーインＣｉｎに対応することとを考慮すると、
ｃｐ［２，１］＝〜ｐ［１］ ＜ｃｐ［１，１］，ｃｐ［１，０］＞
となる。
【００４４】
以上をまとめると、２桁の場合のキャリーフォーパリティＣＰ２は、以下の式群（１３）の通りである。
【００４５】
ＣＰ２＝Ｃｉｎ＜ｃｐ［２，１］，ｃｐ［２，０］＞
ｃｐ［２，０］＝ｇ［１］＜ｃｐ［１，１］，ｃｐ［１，０］＞＝ｇ［１］
ｃｐ［２，１］＝〜（ｐ［１］＜ｃｐ［１，１］，ｃｐ［１，０］＞）＝〜ｐ［１］ （１３）
図４（３）は３ビット（３桁）の場合である。３ビットの場合は、２ビットの第０、１桁に対してキャリーが発生するか否かと考えることにより、３ビットのキャリーフォーパリティＣＰ３を２ビットのキャリーフォーパリティＣＰ２のｃｐ［２，１］，ｃｐ［２，０］を利用して表現することができる。つまり、キャリーインＣｉｎ＝０の場合は、最下位の第２ビットにキャリー（桁上げ）が発生するか否かを示すジェネレーションｇ［２］が、上位の２ビット（第０、１ビット）に対するキャリーインＣｉｎに対応するので、
ｃｐ［３，０］＝ｇ［２］＜ｃｐ［２，１］，ｃｐ［２，０］＞
更に、キャリーインＣｉｎ＝１の場合は、そのキャリーインによる最下位の第２ビットでの反転と、最下位の第２ビットのプロパゲーションｐ［２］が、上位の２ビット（第０、１ビット）に対するキャリーインＣｉｎに対応することを考慮すると、
ｃｐ［３，１］＝〜ｐ［２］ ＜ｃｐ［２，１］，ｃｐ［２，０］＞
となる。
【００４６】
従って、３桁の場合のキャリーフォーパリティＣＰ３は、以下の式群（１４）の通りである。
【００４７】

図４（４）は４ビット（４桁）の場合である。４ビットの場合は、２ビットの第０〜２桁に対してキャリーが発生するか否かと考えることにより、４ビットのキャリーフォーパリティＣＰ４を３ビットのキャリーフォーパリティＣＰ３のｃｐ［３，１］，ｃｐ［３，０］を利用して表現することができる。つまり、キャリーインＣｉｎ＝０の場合は、最下位の第３ビットにキャリー（桁上げ）が発生するか否かを示すジェネレーションｇ［３］が、上位の３ビット（第０〜２ビット）に対するキャリーインＣｉｎに対応するので、
ｃｐ［４，０］＝ｇ［３］＜ｃｐ［３，１］，ｃｐ［３，０］＞
更に、キャリーインＣｉｎ＝１の場合は、そのキャリーインによる最下位の第３ビットでの反転と、最下位の第３ビットのプロパゲーションｐ［３］が、上位の３ビット（第０〜２ビット）に対するキャリーインＣｉｎに対応することを考慮すると、
ｃｐ［４，１］＝〜ｐ［３］ ＜ｃｐ［３，１］，ｃｐ［３，０］＞
となる。
【００４８】
結局、４桁の場合のキャリーフォーパリティＣＰ４は、以下の式群（１５）の通りである。
【００４９】

この展開式は前述の式（９）と一致している。
【００５０】
図４（５）はｎビットに一般化した場合を示し、上記と同様の再帰性を利用すると、ｎビットの全加算器でのキャリーフォーパリティＣＰｎは、
ＣＰｎ ＝ Ｃｉｎ＜ｃｐ［ｎ，１］， ｃｐ［ｎ，０］＞
ｃｐ［ｎ，０］ ＝ （ｇ［ｎ−１］＜ｃｐ［ｎ−１，１］， ｃｐ［ｎ−１，０］＞）
ｃｐ［ｎ，１］ ＝ 〜（ｐ［ｎ−１］＜ｃｐ［ｎ−１，１］， ｃｐ［ｎ−１，０］＞） （１６）
上記の式（１２）〜（１６）を並べて記載すると、再帰的な関係を有していることが理解される。
【００５１】
ｃｐ［ｎ，０］ ＝ （ｇ［ｎ−１］＜ｃｐ［ｎ−１，１］， ｃｐ［ｎ−１，０］＞）
ｃｐ［ｎ，１］ ＝ 〜（ｐ［ｎ−１］＜ｃｐ［ｎ−１，１］， ｃｐ［ｎ−１，０］＞）
ｃｐ［ｎ−１，０］ ＝ （ｇ［ｎ−２］＜ｃｐ［ｎ−２，１］， ｃｐ［ｎ−２，０］＞）
ｃｐ［ｎ−１，１］ ＝ 〜（ｐ［ｎ−２］＜ｃｐ［ｎ−２，１］， ｃｐ［ｎ−２，０］＞）
．．．．．．．．
ｃｐ［４，０］ ＝ （ｇ［３］＜ｃｐ［３，１］， ｃｐ［３，０］＞）
ｃｐ［４，１］ ＝ 〜（ｐ［３］＜ｃｐ［３，１］， ｃｐ［３，０］＞）
ｃｐ［３，０］ ＝ （ｇ［２］＜ｃｐ［２，１］， ｃｐ［２，０］＞）
ｃｐ［３，１］ ＝ 〜（ｐ［２］＜ｃｐ［２，１］， ｃｐ［２，０］＞）
ｃｐ［２，０］ ＝ （ｇ［１］＜ｃｐ［１，１］， ｃｐ［１，０］＞） ＝ ｇ［１］
ｃｐ［２，１］ ＝ 〜（ｐ［１］＜ｃｐ［１，１］， ｃｐ［１，０］＞） ＝ 〜ｐ［１］
ｃｐ［１，０］ ＝ Ｃｉｎ ＝ ０
ｃｐ［１，１］ ＝ Ｃｉｎ ＝ １ （１７）
図５は、キャリーフォーパリティＣＰｎを求める論理回路図である。この論理回路は、上記式群（１６）をセレクタＳＥＬ１、ＳＥＬ２、ＳＥＬｅと、インバータ４０とで構成している。各セレクタは、図３のパストランジスタ回路がそれぞれ利用される。つまり、セレクタＳＥＬｅが次の式に対応し、
ＣＰｎ ＝ Ｃｉｎ＜ｃｐ［ｎ，１］， ｃｐ［ｎ，０］＞
セレクタＳＥＬ１が次の式に対応し、
ｃｐ［ｎ，０］ ＝ （ｇ［ｎ−１］＜ｃｐ［ｎ−１，１］， ｃｐ［ｎ−１，０］＞）
セレクタＳＥＬ２が次の式に対応する。
【００５２】
ｃｐ［ｎ，１］ ＝ 〜（ｐ［ｎ−１］＜ｃｐ［ｎ−１，１］， ｃｐ［ｎ−１，０］＞）
そして、図５の回路からセレクタＳＥＬｅを除いた部分が、ユニット回路ＵＮＩＴｎを構成する。このユニット回路は、ｎを減じて、より前段のユニット回路を構成することができる。
【００５３】
図６は、前段のユニット回路を示す図である。つまり、図５の前段には、ユニット回路ＵＮＩＴｎ−１が、その前段にはユニット回路ＵＮＩＴｎ−２が構成される。そして、ｎ＝３のユニット回路まで展開すると、ｎビット幅の全加算器のためのキャリーフォーパリティＣＰｎを求める論理回路が完成する。
【００５４】
図７は、４ビット幅の全加算器用のキャリーフォーパリティＣＰ４を生成する回路１８の論理回路である。この回路では、２段のユニット回路ＵＮＩＴ３、ＵＮＩＴ４と、最終段のキャリーインＣｉｎを制御信号とするセレクタＳＥＬｅとで構成され、前述の式（１７）のｃｐ［４，０］，ｃｐ［４，１］、ｃｐ［３，０］，ｃｐ［３，１］が、セレクタ１２、１３及び１０、１１により求められる。従って、この論理回路は、各セレクタＳＥＬ１０〜ＳＥＬ１３、ＳＥＬｅで４個のトランジスタ、各インバータ４１，４２で２個のトランジスタの、合計で２４個のトランジスタで構成可能である。尚、各セレクタの制御信号ｇ［１］，ｇ［２］，ｇ［３］，ｐ［１］，ｐ［２］，ｐ［３］とその反転信号は、図１のプロパゲーション生成回路Ｐ、ジェネレーション生成回路Ｇでそれぞれ生成されているものとする。
【００５５】
図７の出力であるキャリーフォーパリティ信号ＣＰ４は、図１に示されるとおり、予測パリティ生成回路１４に入力され、入力データＡ，ＢのパリティビットＡ［Ｐ］とＢ［Ｐ］との排他的論理和が求められて、加算値の予測パリティＳ［Ｐ］が生成される。つまり、本実施の形態のパリティ予測回路は、ＣＰ生成回路１８と予測パリティ生成回路１４とで構成される。そして、予測パリティ生成回路１４は、排他的論理和演算をすればよいので、この排他的論理和回路も、周知のとおり、セレクタを組み合わせることで構成可能である。
【００５６】
図８は、４ビット幅の全加算器用のキャリーフォーパリティＣＰ４を生成する回路１８の論理回路の変形例である。図７の回路では、セレクタＳＥＬ１０とＳＥＬ１２とＳＥＬｅとが縦列に接続されている。従って、図８の回路では、伝搬信号の波形成形のために、各ユニットＵＮＩＴ３，４の境界に波形成型用のバッファ４３，４５が設けられる。同様に、セレクタＳＥＬ１１、ＳＥＬ１３、ＳＥＬｅの信号伝搬経路にも、波形成型用のバッファ４４，４６が設けられる。但し、この経路には、インバータ４１，４２が設けられているので、これらのバッファ４４，４６を省略することもできる。
【００５７】
図９は、図７のキャリーフォーパリティ生成回路をｎビット幅まで拡張した論理回路である。この回路でも複数段のユニット回路ＵＮＩＴ３〜ｎが縦列に接続される。ユニット回路ＵＮＩＴ１、ＵＮＩＴ２とは、図７のユニット回路ＵＮＩＴ３，４に対応する。つまり、ユニットＵＮＩＴｋが、ｋ＝３〜ｎまで繰り返され、最終段のセレクタ回路ＳＥＬｅには、ユニットＵＮＩＴｎのセレクタの出力が入力される。
【００５８】
即ち、図９のキャリーフォーパリティ生成回路は、
加算入力Ａ［１］とＢ［１］のジェネレーションビットｇ［１］またはプロパゲーションビットｐ［１］ の反転信号のいずれかを、加算入力Ａ［２］とＢ［２］のジェネレーションビットｇ［２］に応じて選択して出力する第５のセレクタＳＥＬ５と、
ジェネレーションビットｇ［１］またはプロパゲーションビットｐ［１］ の反転信号のいずれかを、加算入力Ａ［２］とＢ［２］のプロパゲーションビットｐ［２］に応じて選択して出力する第６のセレクタＳＥＬ６と、を有する第３のユニットＵＮＩＴ３を有する。
【００５９】
そして、第２ｋ−３（但しｋは１〜ｎ−３の整数）のセレクタの出力または第２ｋ−２のセレクタの出力の反転信号のいずれかを、加算入力Ａ［ｋ−１］とＢ［ｋ−１］のジェネレーションビットｇ［ｋ−１］に応じて選択して出力する第２ｋ−１のセレクタと、
前記第２ｋ−３のセレクタの出力または前記第２ｋ−２のセレクタの出力の反転信号のいずれかを、前記加算入力Ａ［ｋ−１］とＢ［ｋ−１］のプロパゲーションビットｐ［ｋ−１］に応じて選択して出力する第２ｋのセレクタと、を有する第ｋのユニットＵＮＩＴｋが、ｋ＝３〜ｎまで繰り返し縦列に接続される。即ち、第３のユニットＵＮＩＴ３〜第ｎのユニットＵＮＩＴｎが、縦列に接続される。
【００６０】
更に、最終段のユニットＵＮＩＴｎの第２ｎ−１のセレクタの出力または第２ｎのセレクタの出力の反転信号のいずれかを、キャリーインＣｉｎに応じて選択して、キャリーフォーパリティＣＰｎとして出力する最終段セレクタＳＥＬｅを有する。
【００６１】
図９の論理回路においても、各ユニット間には、図８のようにバッファゲートを設けて、波形成形を行うことが好ましい。また、各セレクタが、パストランジスタで構成されることで、信号伝播を高速化して、キャリーフォーパリティビットＣＰｎの生成を高速化することができる。
【００６２】
以上のとおり、本実施の形態でのキャリーフォーパリティ信号生成回路は、少ない素子数と少ない入力数で構成することができる。従って、全加算器のパリティ予測回路を、少ない入力数、素子数で構成することができる。しかも、セレクタにパストランジスタを利用することで、高速にキャリーフォーパリティ信号を生成することができる。
【００６３】
以上、実施の形態例をまとめると以下の付記の通りである。
【００６４】
（付記１）ｎビット幅のパリティビット付き加算入力Ａ［０：ｎ−１，Ｐ］とＢ［０：ｎ−１，Ｐ］とキャリーインＣｉｎとから、予測パリティビット付き加算値Ｓ［０：ｎ−１，Ｐ］を求める全加算器におけるパリティ予測回路において、
前記予測パリティビットＳ［Ｐ］は、前記加算入力のパリティビットＡ［Ｐ］、Ｂ［Ｐ］と、各桁へのキャリービットｃ［ｉ］ （但しｉは０〜ｎ−１の整数）の排他的論理和であるキャリーフォーパリティＣＰｎと、の排他的論理和により生成され、
前記キャリーフォーパリティＣＰｎの演算式は、
ＣＰｎ＝Ｃｉｎ＜ｃｐ［ｎ，１］， ｃｐ［ｎ，０］＞
で表されるものとし（但し、Ｓ＜Ｘ，Ｙ＞は、Ｓ＝１の時はＸを、Ｓ＝０の時はＹを出力するものとし、更に、ｃｐ［ｎ，１］は前記キャリーインＣｉｎ＝１の時のキャリーフォーパリティＣＰｎを、ｃｐ［ｎ，０］は前記キャリーインＣｉｎ＝０の時のキャリーフォーパリティＣＰｎをそれぞれ示すものとする。）、
前記パリティ予測回路は、
前記キャリーインＣｉｎ＝０及び１の場合のキャリーフォーパリティＣＰ［ｋ−１，０］及びＣＰ［ｋ−１，１］を入力とし（但しｋはｎ以下の整数）、加算入力Ａ［ｋ−１］とＢ［ｋ−１］とのジェネレーションビットｇ［ｋ−１］に応じて、前記入力ＣＰ［ｋ−１，０］またはＣＰ［ｋ−１，１］のいずれかをキャリーフォーパリティｃｐ［ｋ，０］として出力する第１のセレクタと、前記キャリーフォーパリティＣＰ［ｋ−１，０］及びＣＰ［ｋ−１，１］を入力とし、前記加算入力Ａ［ｋ−１］とＢ［ｋ−１］とのプロパゲーションビットｐ［ｋ−１］に応じて、前記入力ＣＰ［ｋ−１，０］またはＣＰ［ｋ−１，１］のいずれかをキャリーフォーパリティｃｐ［ｋ，１］の反転信号として出力する第２のセレクタとを有する演算ユニットを有し、
当該演算ユニットが複数段、縦列に接続され、
更に、最終段に、キャリーインＣｉｎに応じて、キャリーフォーパリティｃｐ［ｎ，０］またはｃｐ［ｎ，１］のいずれかをキャリーフォーパリティＣＰｎとして出力する最終段セレクタを有することを特徴とするパリティ予測回路。
【００６５】
（付記２）付記１において、
前記演算ユニットの第１及び第２のセレクタの出力が、後段の演算ユニットの入力として供給されるように縦列に接続されることを特徴とするパリティ予測回路。
【００６６】
（付記３）付記２において、
前記各演算ユニットは、前記第２のセレクタの出力に接続されたインバータを有することを特徴とするパリティ予測回路。
【００６７】
（付記４）付記２において、
前記各演算ユニットは、後段の演算ユニットとの間に、バッファゲートを有することを特徴とするパリティ予測回路。
【００６８】
（付記５）付記１において、
前記第１、第２及び最終段のセレクタが、前記ジェネレーションビットｇ［ｋ−１］、プロパゲーションビットｐ［ｋ−１］、キャリーインビットＣｉｎを制御信号とするパストランジスタ回路で構成されていることを特徴とするパリティ予測回路。
【００６９】
（付記６）４ビット幅のパリティビット付き入力Ａ［０：３，Ｐ］とＢ［０：３，Ｐ］とキャリーインＣｉｎとから、予測パリティビット付き加算値Ｓ［０：３，Ｐ］を求める全加算器におけるパリティ予測回路において、
前記予測パリティビットＳ［Ｐ］は、前記入力のパリティビットＡ［Ｐ］、Ｂ［Ｐ］と、各桁へのキャリービットｃ［ｉ］ （但しｉは０〜３の整数）の排他的論理和であるキャリーフォーパリティＣＰ４との排他的論理和により生成され、
前記パリティ予測回路は、前記キャリーフォーパリティＣＰ４を生成する回路を有し、
当該キャリーフォーパリティＣＰ４生成回路は、
前記加算入力Ａ［１］とＢ［１］のジェネレーションビットｇ［１］またはプロパゲーションビットｐ［１］の反転信号のいずれかを、前記加算入力Ａ［２］とＢ［２］のジェネレーションビットｇ［２］に応じて選択して出力する第１のセレクタと、
前記ジェネレーションビットｇ［１］またはプロパゲーションビットｐ［１］ の反転信号のいずれかを、前記加算入力Ａ［２］とＢ［２］のプロパゲーションビットｐ［２］に応じて選択して出力する第２のセレクタと、
前記第１のセレクタの出力または前記第２のセレクタの出力の反転信号のいずれかを、前記加算入力Ａ［３］とＢ［３］のジェネレーションビットｇ［３］に応じて選択して出力する第３のセレクタと、
前記第１のセレクタの出力または前記第２のセレクタの出力の反転信号のいずれかを、前記加算入力Ａ［３］とＢ［３］のプロパゲーションビットｐ［３］に応じて選択して出力する第４のセレクタと、
前記第１のセレクタの出力または前記第２のセレクタの出力の反転信号のいずれかを、前記キャリーインＣｉｎに応じて選択して、前記キャリーフォーパリティＣＰ４として出力する最終段セレクタとを有することを特徴とするパリティ予測回路。
【００７０】
（付記７）付記６において、
更に、前記第２及び第４のセレクタの出力に接続されたインバータを有することを特徴とするパリティ予測回路。
【００７１】
（付記８）付記６において、
前記セレクタは、制御信号に応じていずれか一方の入力を通過させるパストランジスタ回路により構成されることを特徴とするパリティ予測回路。
【００７２】
（付記９）ｎビット幅のパリティビット付き入力Ａ［０：ｎ−１，Ｐ］とＢ［０：ｎ−１，Ｐ］とキャリーインＣｉｎとから、予測パリティビット付き加算値Ｓ［０：ｎ−１，Ｐ］を求める全加算器におけるパリティ予測回路において、
前記予測パリティビットＳ［Ｐ］は、前記入力のパリティビットＡ［Ｐ］、Ｂ［Ｐ］と、各桁へのキャリービットｃ［ｉ］ （但しｉは０〜ｎ−１の整数）の排他的論理和であるキャリーフォーパリティＣＰｎとの排他的論理和により生成され、
前記パリティ予測回路は、前記キャリーフォーパリティＣＰｎを生成する回路を有し、
当該キャリーフォーパリティＣＰｎ生成回路は、
前記加算入力Ａ［１］とＢ［１］のジェネレーションビットｇ［１］またはプロパゲーションビットｐ［１］ の反転信号のいずれかを、前記加算入力Ａ［２］とＢ［２］のジェネレーションビットｇ［２］に応じて選択して出力する第５のセレクタと、
前記ジェネレーションビットｇ［１］またはプロパゲーションビットｐ［１］ の反転信号のいずれかを、前記加算入力Ａ［２］とＢ［２］のプロパゲーションビットｐ［２］に応じて選択して出力する第６のセレクタと、
第２ｋ−３（但しｋは４〜ｎの整数）のセレクタの出力または第２ｋ−２のセレクタの出力の反転信号のいずれかを、前記加算入力Ａ［ｋ−１］とＢ［ｋ−１］のジェネレーションビットｇ［ｋ−１］に応じて選択して出力する第２ｋ−１のセレクタと、
前記第２ｋ−３のセレクタの出力または前記第２ｋ−２のセレクタの出力の反転信号のいずれかを、前記加算入力Ａ［ｋ−１］とＢ［ｋ−１］のプロパゲーションビットｐ［ｋ−１］に応じて選択して出力する第２ｋのセレクタとを有し、
前記第２ｋ−１のセレクタと第２ｋのセレクタとが、ｋ＝４〜ｎまで繰り返し縦列に接続され、
更に、前記第２ｎ−１のセレクタの出力または前記第２ｎのセレクタの出力の反転信号のいずれかを、前記キャリーインＣｉｎに応じて選択して、前記キャリーフォーパリティＣＰｎとして出力する最終段セレクタを有することを特徴とするパリティ予測回路。
【００７３】
（付記１０）付記９において、
更に、前記第２ｋのセレクタの出力にそれぞれ接続されたインバータを有することを特徴とするパリティ予測回路。
【００７４】
（付記１１）付記９において、
前記セレクタは、制御信号に応じていずれか一方の入力を通過させるパストランジスタ回路により構成されることを特徴とするパリティ予測回路。
【００７５】
【発明の効果】
以上、本発明によれば、全加算器のパリティ予測回路を、少ない入力数、素子数で構成することができる。
【図面の簡単な説明】
【図１】本実施の形態に適用される全加算器とパリティ予測回路とを示す図である。
【図２】キャリーフォーパリティ生成回路１８の論理回路図である。
【図３】ＣＭＯＳ回路で構成されたパストランジスタの回路図の一例を示す図である。
【図４】キャリーフォーパリティを説明する図である。
【図５】キャリーフォーパリティＣＰｎを求める論理回路図である。
【図６】前段のユニット回路を示す図である。
【図７】４ビット幅の全加算器用のキャリーフォーパリティＣＰ４を生成する回路１８の論理回路である。
【図８】４ビット幅の全加算器用のキャリーフォーパリティＣＰ４を生成する回路１８の論理回路の変形例である。
【図９】ｎビット幅の全加算器用のキャリーフォーパリティＣＰｎを生成する回路１８の論理回路である。
【符号の説明】
ＳＥＬ セレクタ、ＵＮＩＴ ユニット、ｇ ジェネレーションビット、ｐ プロパゲーションビット、ｈ ハーフサムビット、Ａ，Ｂ 加算入力、Ｓ 加算値、Ｃｉｎ
キャリーイン、ＣＰｎ キャリーフォーパリティ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a parity prediction circuit provided in a full adder, and more particularly, to a novel parity prediction circuit with a reduced number of inputs and elements.
[0002]
[Prior art]
Full adders are built in various places in a semiconductor integrated circuit. The full adder generates an addition value S and a carryout Cout from inputs A and B of predetermined bits (predetermined digits) and the carry-in Cin from the lower order. The most common full adder is a 4-bit addition value S [0: 3] in which one block is composed of 4-bit inputs A [0: 3] and B [0: 3] and a 1-bit carry-in Cin. And a 1-bit carry-out Cout is generated. In this specification, for the sake of explanation, the most significant bit (MSB) is the 0th bit (or the 0th digit) and the least significant bit (LSB) is the (n-1) th bit (or the nth bit) for an n-bit value. -1 digit).
[0003]
Further, for example, data A [0: 3] and B [0: 3] read from a predetermined memory propagate through a predetermined transmission path and are input to a full adder, and the addition result is further transmitted. When the input data propagates through a predetermined transmission path and the output data also propagates through another transmission path, such as output to a path, a parity bit is added to the input data. A parity prediction circuit is provided in addition to the full adder circuit so that the parity bit of the addition output has the information on the presence / absence of bit inversion during propagation of these parity bits. The parity prediction circuit generates a predicted parity bit by calculating an exclusive OR of the parity bit of the two input data and the carry at each digit in the addition operation.
[0004]
In the full adder and the parity prediction circuit, a generation g, a propagation p, and a half sum h obtained from input data A [0: 3] and B [0: 3] are included in a preceding stage. , And a logic circuit that generates the added value S [0: 3] and the predicted parity bit S [P] from these g, p, and h is configured.
[0005]
A data operation circuit with parity is described in Patent Document 1 below.
[0006]
[Patent Document 1]
JP-A-4-288629
[0007]
[Problems to be solved by the invention]
However, since the parity prediction circuit that generates the predicted parity bits takes a configuration in which the theoretically calculated prediction parity bit arithmetic expression is directly replaced with NAND or NOR logic gates, the number of inputs increases and the number of logic gates also increases. There is a tendency for circuits to increase in scale. In particular, when the number of digits of the input data increases, the circuit scale increases exponentially, which is a problem of high integration.
[0008]
Therefore, an object of the present invention is to provide a parity bit prediction circuit that generates a predicted parity bit with a small circuit scale.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, according to one aspect of the present invention, a circuit for calculating a carry-for-parity CPn of a parity prediction circuit included in an n-bit-wide full adder is configured to perform one of the circuits according to a control signal. Is configured by a plurality of selectors for selecting the input.
[0010]
Now, a full adder having an n-bit width generates an added value S [0: 0] from the addition inputs A [0: n-1, P] and B [0: n-1, P] and the carry-in Cin from the lower order. n−1, P], the logical formula is
S [0: n-1, P] = A [0: n-1, P] + B [0: n-1, P] + Cin
It becomes. The logical expression for calculating the predicted parity S [P] in this case is:
S [P] = A [P] vB [P] vCPn
CPn = c [0] vc [1] v. . . vc [n-1]
Here, A [P] and B [P] are parity bits of inputs A and B, c [i] is carry-in from the lower bit of the ith bit, CPn is carry-for-parity, and v is exclusive OR. . And, as a premise, the carry for parity CPn is
CPn = Cin <cp [n, 1], cp [n, 0]>
It is assumed that Here, S <X, Y> indicates (S · X) | (〜S · Y). For inputs X and Y, when S = 1, X is given, and when S = 0, X is given. This corresponds to a selector that outputs Y. Further, cp [n, 1] is a carry-for-parity CPn for n bits when carry-in Cin = 1, and cp [n, 0] is a carry-for-parity CPn for n bits when carry-in Cin = 0. Shall be shown. That is, n in cp [n, 1] and cp [n, 0] indicates the number of bits.
[0011]
When the calculation is performed on the above assumptions, the following calculation expression is obtained.
[0012]
cp [n, 0] = (g [n−1] <cp [n−1,1], cp [n−1,0]>)
cp [n, 1] = 〜 (p [n−1] <cp [n−1,1], cp [n−1,0]>)
cp [n-1,0] = (g [n-2] <cp [n-2,1], cp [n-2,0]>)
cp [n−1,1] = 〜 (p [n−2] <cp [n−2,1], cp [n−2,0]>)
. . . . . . . .
cp [4,0] = (g [3] <cp [3,1], cp [3,0]>)
cp [4,1] = (p [3] <cp [3,1], cp [3,0]>)
cp [3,0] = (g [2] <cp [2,1], cp [2,0]>)
cp [3,1] = (p [2] <cp [2,1], cp [2,0]>)
cp [2,0] = (g [1] <cp [1,1], cp [1,0]>) = g [1]
cp [2,1] = (p [1] <cp [1,1], cp [1,0]>) = p [1]
cp [1,0] = 0 (= Cin)
cp [1,1] = 1 (= Cin)
Therefore, according to the above arithmetic expression, the parity prediction circuit of the present invention receives the carry-in parity CP [k-1,0] and CP [k-1,1] in the case of carry-in Cin = 0 and 1. (Where k is an integer equal to or less than n), and the input CP [k−1,0] according to the generation bits g [k−1] of the addition inputs A [k−1] and B [k−1]. Alternatively, a first selector that outputs any one of CP [k−1, 1] as carry-for-parity cp [k, 0], and a first selector that outputs the carry-for-parities CP [k−1, 0] and CP [k−1, 1] as input and the input CP [k-1,0] or CP [k-1] according to the propagation bit p [k-1] of the addition input A [k-1] and B [k-1]. k−1, 1] to carry for parity cp [k, 1]. An arithmetic unit and a second selector for outputting the inverted signal,
The arithmetic units are connected in a plurality of stages and columns,
The parity further comprising a final-stage selector that outputs either carry-for-parity cp [n, 0] or cp [n, 1] as carry-for-parity CPn in the last stage according to carry-in Cin. It is a prediction circuit.
[0013]
According to the parity prediction circuit described above, since it is configured by connecting arithmetic units having two selectors in cascade, it can be configured with a small number of elements.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the scope of protection of the present invention is not limited to the following embodiments, but extends to the inventions described in the claims and their equivalents.
[0015]
FIG. 1 is a diagram showing a full adder and a parity prediction circuit applied to the present embodiment. In this example, a 4-bit addition value S with a predicted parity bit is obtained from a 4-bit input A [0: 3, P] and B [0: 3, P] with a parity bit and a carry-in Cin from the lower side. [0: 3, P] and the carry-out Cout are generated. That is, the arithmetic expression of this full adder is
S [0: 3, P] = A [0: 3, P] + B [0: 3, P] + Cin
It is.
[0016]
As described above, as a premise, the least significant bit (LSB) of 4-bit data is represented by "3" and the most significant bit (MSB) is represented by "0". Therefore, in the case of n + 1-bit data, the least significant bit is represented by “n” and the most significant bit is represented by “0”. In this specification, “「 ”is used as an inversion symbol.
[0017]
As a previous stage, for each bit of 4-bit input A [0: 3] and B [0: 3], propagation p [0: 3], generation g [0: 3], and half sum h [0: 3] are generated by the propagation generation circuit P, the generation generation circuit G, and the half sum generation circuit H, respectively. Here, the propagation p [0: 3], the generation g [0: 3], and the half sum h [0: 3] are obtained by the following logical expressions.
[0018]
p [0: 3] = A [0: 3] | B [0: 3] (| is a logical sum (OR))
g [0: 3] = A [0: 3] B [0: 3] (where is a logical product (AND))
h [0: 3] = A [0: 3] v B [0: 3] (v is exclusive OR (EOR))
That is, the propagation p becomes “1” when either of the inputs A and B is “1”, and becomes “0” when both are “0”. In other words, the propagation p is a bit indicating whether, when a carry (carry) from the lower bit occurs, the carry is propagated to the upper bit (p = 1) or not propagated (p = 0). It is. For example, when the propagation p [n] of the data A [n] and B [n] of the n-th bit is "1", if there is a carry from the lower n + 1 bits, the carry is carried to the upper n-1 bits. Is generated, but when the propagation p [n] is “0”, even if a carry occurs from the lower n + 1 bits, no carry occurs in the upper n−1 bits.
[0019]
Generation g becomes "1" when both inputs A and B are "1", and becomes "0" when either input is "0". That is, the generation g is a bit indicating whether a carry to an upper bit is generated at that digit (g = 1) or not (g = 0) even if a carry from the lower bit does not occur. . For example, when the generation g [n] of the data A [n] and B [n] of the n-th bit is “1”, the carry is carried out in the upper n−1 bits without carrying from the lower n + 1 bits. However, when generation g [n] is “0”, if there is no carry from the lower n + 1 bits, no carry occurs in the upper n−1 bits.
[0020]
The half sum h becomes "1" when the inputs A and B are different, and becomes "0" when the inputs A and B are the same. That is, the half sum h is a bit indicating the addition result of the inputs A and B. For example, when A [n] and B [n] are 1,0 or 0,1 in the n-th bit, the half sum h [n] becomes "1", and A [n] and B [n] ] Is 0, 0 or 1, 1, the half sum h [n] becomes “0”.
[0021]
Accordingly, the addition value generation circuit 10 is configured by an exclusive OR circuit based on the following arithmetic expression, and generates the addition value S [0: 3].
[0022]
S [0] = h [0] vc [0]
S [1] = h [1] vc [1]
S [2] = h [2] vc [2]
S [3] = h [3] vc [3]
Here, c [0], c [1], c [2], c [3] are carry-in (carry) bits for each bit, and these carry bits c are Generated by The carry generation circuit 16 is configured by a logic circuit based on the following arithmetic expression.
[0023]

That is, the carry-in c [3] to the least significant bit (third bit) is the carry-in Cin from the lower bit (Equation (1)). Also, the carry-in c [2] to the next second bit is that the generation g [3] of the least significant bit is g [3] = 1, the propagation p [3] is p [3] = 1 and This occurs when the carry-in Cin is Cin = 1 (Equation (2)). Further, the carry-in c [1] to the first bit is such that the generation g [2] of the second bit is g [2] = 1, the propagation p [2] is p [2] = 1 and This occurs when carry-in c [2] to two bits is c [2] = 1 (Equation (3)). By substituting equation (2) into equation (3), equation (4) is obtained.
[0024]
Similarly, the carry-in c [0] to the 0-th bit (most significant bit) is such that the generation g [1] of the first bit is g [1] = 1 or the propagation p [1] is p [1]. = 1 and the carry-in c [1] to the first bit is c [1] = 1 (Equation (5)). By substituting equation (4) into equation (5), equation (6) is obtained.
[0025]
As understood from the above, the general formula of carry-in is as follows.
[0026]
c [n] = g [n + 1] | (p [n + 1] .c [n + 1]))
Therefore, the carry-out generation circuit 12 is constituted by a logic circuit of the following arithmetic expression.
[0027]
Cout = g [0] | (p [0] · c [0]))
By the way, a circuit for obtaining a predicted parity bit from the parity bits of the input data A and B is provided together with a circuit for obtaining the addition value and the carry-out. This circuit includes a CP (Carry for Parity) generation circuit 18 and a predicted parity generation circuit 14. The predicted parity bit S [P] that directly propagates information indicating the presence or absence of a defect in the parity bits A [P] and B [P] of the input data A and B to the parity bit S [P] of the addition value S is as follows. It is known that it is obtained by the following arithmetic expression.
[0028]
S [P] = A [P] vB [P] vCP4 (7)
Here, CP4 is a bit indicating the effect on the parity bit due to the carry of each bit (each digit), and is referred to as carry for parity (carry of parity bit). The carry for parity CP4 is a bit indicating how many times carry-in c [0], c [1], c [2], c [3] to each bit (each digit) has occurred. It is obtained by a generally known arithmetic expression.
[0029]
CP4 = c [0] vc [1] vc [2] vc [3] (8)
In other words, the exclusive OR v is equivalent to inversion when "1" and not inversion when "0", so that the carry-parity CP4 has an odd number of carry-ins to each digit. This is bit data indicating whether CP4 = 0) or an even number (CP4 = 1).
[0030]
When the above equations (1), (2), (4), and (6) are substituted into the above equation (8) and expanded, the following is obtained.
[0031]
CP4 = [(g [1] · 〜g [2] · ・ g [3]) | (〜p [1] · g [2] · 〜g [3]) |
(〜G [1] · 〜p [2] · g [3]) | (p [1] · p [2] · g [3])]: if Cin = 0
[(~ G [1] · ~ g [2] · ~ p [3]) | (p [1] · g [2] · ~ p [3]) |
(G [1] · 〜p [2] · p [3]) | (〜p [1] · p [2] · p [3])]: if Cin = 1 (9)
The operation expression (9) is configured to be divided into a case where the carry-in Cin is “0” and a case where the carry-in Cin is “1”, and each operation expression is composed of the generation g and the property generated in the previous stage. It can be configured by a logic circuit that receives the inverted and non-inverted bits of the gate p. This arithmetic expression is generally known.
[0032]
FIG. 2 is a logic circuit diagram of the carry-for-parity generating circuit 18. In this logic circuit diagram, the arithmetic expression (9) is developed as it is in a logic circuit. That is, an AND circuit and an OR circuit are generated by the NAND gates 20 to 23 and their output NAND gate 24, and the term in the case of Cin = 0 in the arithmetic expression (9) is calculated. An AND circuit and an OR circuit are generated by the NAND gates 25 to 28 and the output NAND gate 29, and the term in the case where Cin = 1 in the arithmetic expression (9) is calculated. Then, the selector 30 selects the output of the gates 24 and 29 according to the case where Cin = 1 and the case where Cin = 0.
[0033]
The carry-for-parity generating circuit 18 in FIG. 2 has a configuration in which the arithmetic expression (9) is directly expanded into a logic circuit. The generation circuit 18 has eight 3-input gates 20 to 23, 25 to 28, two 4-input gates 24 and 29, and a selector 30. A three-input NAND gate requires six transistors when configured with a CMOS circuit. In addition, a 4-input NAND gate requires eight transistors when configured with a CMOS circuit. Therefore, the circuit of FIG. 2 requires 64 transistors only with the NAND gate, and if the selector 30 is composed of 4 transistors, a total of 68 transistors are required. When the number of bits of input data is increased to 6 bits or 8 bits, the number of transistors increases exponentially, which hinders high integration.
[0034]
Therefore, the inventor has newly invented a carry-for-parity generating circuit using only a pass transistor circuit. A pass transistor is a selector that selects one of two inputs according to a control bit of the opposite phase. When configured with a CMOS circuit, if the control bit of the opposite phase can be used, four transistors are used. realizable.
[0035]
FIG. 3 is a diagram showing an example of a circuit diagram of a pass transistor constituted by a CMOS circuit. The pass transistor circuit is a kind of selector, and selects the input A as the output X when the control signal S is “1”, and selects the input B as the output X when the control signal S is “0”. The N-channel transistor N1 and the P-channel transistor P1 constituting the first transfer gate allow the input A to pass when the control signal S is at the H level (S = 1). Further, the N-channel transistor N2 and the P-channel transistor P2 constituting the second transfer gate allow the input B to pass when the control signal S is at the L level (S = 0). Therefore, a selector SEL configured with such a pass transistor circuit will be described as shown in FIG.
[0036]
Then, the following notation will be adopted as the arithmetic expression of the output X.
[0037]
X = (SA) | (~ SB) = S <A, B> (10)
This arithmetic expression indicates that X is A when S = 1 and B when S = 0.
This operation expression corresponds to a selector including inputs A and B and a control signal S.
[0038]
Accordingly, the arithmetic expression for calculating the carry-for-parity CP is expressed using the above-described arithmetic expression (10), whereby the carry-for-parity generating circuit 18 is configured using the selector formed by the pass transistor circuit in FIG. Can be.
[0039]
As a new notation, the carry-for-parity CPn for n bits is expressed as cp [n, 0] and cp [n, 1] with respect to the carry-in Cin = 0 or 1 from the lower order. By doing so, it can be expressed in the form of Expression (10) as follows.
[0040]
CPn = Cin <cp [n, 1], cp [n, 0]> (11)
This equation is equivalent to Equation 10 described above, and can be realized by the pass transistor circuit of FIG.
[0041]
FIG. 4 is a diagram illustrating the carry for parity. With reference to FIG. 4, carry-for-parities CP1 to CP4 and CP4 for 1 to 4 bits and n bits will be described, and their recursiveness will be described. With respect to n bits, the most significant bit is the 0th bit and the least significant bit is the (n-1) th bit. In FIG. 4, the first bit, the second bit, and the third bit each time the number of bits increases. . . . It is described so that the (n-1) th bit and the least significant bit are added. Such notation facilitates the description of the recursiveness of the carry-for-parity.
[0042]
FIG. 4A shows the case of one bit (one digit). In the case of one bit, the carry-for-parity CP1 is determined by whether or not there is a carry Cin from the lower order, as shown in the above-described Expression 8. That is, since CP1 = c [0] = Cin, after all, the carry-for-parity CP1 in the case of one digit is represented by the following formula group (12).
[0043]
CP1 = Cin <cp [1,1], cp [1,0]> = Cin <1,0>
cp [1,0] = 0
cp [1,1] = 1 (12)
FIG. 4B shows a case of two bits (two digits). In the case of 2 bits, it is considered whether or not a carry occurs in the 0th digit of 1 bit, and the carry for parity CP2 of 2 bits is changed to cp [1, 1], cp of the carry for parity CP1 of 1 bit. It can be expressed using [1,0]. In other words, when carry-in Cin = 0, generation g [1] indicating whether or not a carry (carry) occurs in the least significant first bit is the carry-in for the upper one bit (the 0th bit). Because it corresponds to Cin,
cp [2,0] = g [1] <cp [1,1], cp [1,0]>
Further, in the case of carry-in Cin = 1, the inversion of the least significant first bit by the carry-in and the propagation p [1] of the least significant first bit become the upper one bit (0th bit). Considering that it corresponds to carry-in Cin for
cp [2,1] = 〜p [1] <cp [1,1], cp [1,0]>
It becomes.
[0044]
To summarize the above, the carry-for-parity CP2 in the case of two digits is represented by the following formula group (13).
[0045]
CP2 = Cin <cp [2,1], cp [2,0]>
cp [2,0] = g [1] <cp [1,1], cp [1,0]> = g [1]
cp [2,1] = 〜 (p [1] <cp [1,1], cp [1,0]>) = 〜p [1] (13)
FIG. 4C shows a case of three bits (three digits). In the case of 3 bits, it is considered whether or not a carry occurs for the 0th and 1st digits of the 2 bits, so that the carry for parity CP3 of 3 bits is changed to cp [2, 1] of the carry for parity CP2 of 2 bits. , Cp [2,0]. In other words, when carry-in Cin = 0, generation g [2] indicating whether or not a carry (carry) occurs in the second least significant bit is generated for the upper two bits (0th and 1st bits). Because it corresponds to carry-in Cin,
cp [3,0] = g [2] <cp [2,1], cp [2,0]>
Further, when carry-in Cin = 1, the inversion of the least significant second bit by the carry-in and the propagation p [2] of the least significant second bit are performed by the upper two bits (0th and 1st bits). Considering the corresponding carry-in Cin
cp [3,1] = 〜p [2] <cp [2,1], cp [2,0]>
It becomes.
[0046]
Therefore, the carry-for-parity CP3 in the case of three digits is represented by the following formula group (14).
[0047]

FIG. 4D shows a case of 4 bits (4 digits). In the case of 4 bits, by considering whether or not a carry occurs for the 0th to 2nd digits of the 2 bits, the carry for parity CP4 of 4 bits is changed to cp [3,1] of the carry for parity CP3 of 3 bits. , Cp [3,0]. In other words, when carry-in Cin = 0, generation g [3] indicating whether or not a carry (carry) occurs in the least significant third bit is determined with respect to the upper three bits (0th to 2nd bits). Because it corresponds to carry-in Cin,
cp [4,0] = g [3] <cp [3,1], cp [3,0]>
Further, when carry-in Cin = 1, the inversion of the least significant third bit by the carry-in and the propagation p [3] of the least significant third bit are replaced by the upper three bits (0th to 2nd bits). Considering the corresponding carry-in Cin
cp [4,1] = 〜p [3] <cp [3,1], cp [3,0]>
It becomes.
[0048]
After all, the carry for parity CP4 in the case of four digits is as shown in the following formula group (15).
[0049]

This expansion equation matches the above-mentioned equation (9).
[0050]
FIG. 4 (5) shows a case where the generalization is made to n bits. Using the same recursiveness as above, the carry-for-parity CPn in the n-bit full adder becomes
CPn = Cin <cp [n, 1], cp [n, 0]>
cp [n, 0] = (g [n−1] <cp [n−1,1], cp [n−1,0]>)
cp [n, 1] = (p [n−1] <cp [n−1,1], cp [n−1,0]>) (16)
If the above equations (12) to (16) are described side by side, it is understood that they have a recursive relationship.
[0051]
cp [n, 0] = (g [n−1] <cp [n−1,1], cp [n−1,0]>)
cp [n, 1] = 〜 (p [n−1] <cp [n−1,1], cp [n−1,0]>)
cp [n-1,0] = (g [n-2] <cp [n-2,1], cp [n-2,0]>)
cp [n−1,1] = 〜 (p [n−2] <cp [n−2,1], cp [n−2,0]>)
. . . . . . . .
cp [4,0] = (g [3] <cp [3,1], cp [3,0]>)
cp [4,1] = (p [3] <cp [3,1], cp [3,0]>)
cp [3,0] = (g [2] <cp [2,1], cp [2,0]>)
cp [3,1] = (p [2] <cp [2,1], cp [2,0]>)
cp [2,0] = (g [1] <cp [1,1], cp [1,0]>) = g [1]
cp [2,1] = (p [1] <cp [1,1], cp [1,0]>) = p [1]
cp [1,0] = Cin = 0
cp [1,1] = Cin = 1 (17)
FIG. 5 is a logic circuit diagram for determining carry for parity CPn. In this logic circuit, the above formula group (16) is configured by selectors SEL1, SEL2, and SELe, and an inverter 40. Each selector uses the pass transistor circuit of FIG. That is, the selector SELe corresponds to the following equation,
CPn = Cin <cp [n, 1], cp [n, 0]>
The selector SEL1 corresponds to the following equation,
cp [n, 0] = (g [n−1] <cp [n−1,1], cp [n−1,0]>)
The selector SEL2 corresponds to the following equation.
[0052]
cp [n, 1] = 〜 (p [n−1] <cp [n−1,1], cp [n−1,0]>)
The portion excluding the selector SELe from the circuit of FIG. 5 constitutes a unit circuit UNITn. This unit circuit can constitute a unit circuit at a preceding stage by reducing n.
[0053]
FIG. 6 is a diagram showing a unit circuit in the preceding stage. That is, the unit circuit UNITn-1 is configured at the preceding stage in FIG. 5, and the unit circuit UNITn-2 is configured at the preceding stage. Then, when the processing is expanded up to the unit circuit of n = 3, a logic circuit for obtaining the carry-for-parity CPn for the full adder having the n-bit width is completed.
[0054]
FIG. 7 shows a logic circuit of the circuit 18 for generating a carry-for-parity CP4 for a 4-bit width full adder. This circuit is composed of two-stage unit circuits UNIT3 and UNIT4 and a selector SELe that uses the carry-in Cin of the last stage as a control signal, and cp [4,0] and cp [4, 1], cp [3,0], cp [3,1] are obtained by the selectors 12, 13 and 10, 11. Therefore, this logic circuit can be constituted by a total of 24 transistors, that is, four transistors in each of the selectors SEL10 to SEL13 and SELe, and two transistors in each of the inverters 41 and 42. The control signals g [1], g [2], g [3], p [1], p [2], and p [3] of each selector and their inverted signals are represented by the propagation generation circuit P in FIG. , Are generated by the generation generation circuit G.
[0055]
The carry-for-parity signal CP4, which is the output of FIG. 7, is input to the predicted parity generation circuit 14 as shown in FIG. 1, and the exclusive bits of the parity bits A [P] and B [P] of the input data A and B are exclusive. The logical sum is obtained, and a predicted parity S [P] of the added value is generated. That is, the parity prediction circuit according to the present embodiment includes the CP generation circuit 18 and the predicted parity generation circuit 14. Then, since the predicted parity generation circuit 14 only needs to perform an exclusive OR operation, this exclusive OR circuit can also be configured by combining selectors, as is well known.
[0056]
FIG. 8 shows a modification of the logic circuit of the circuit 18 for generating the carry-for-parity CP4 for the 4-bit full adder. In the circuit of FIG. 7, the selectors SEL10, SEL12, and SELe are connected in cascade. Therefore, in the circuit of FIG. 8, buffers 43 and 45 for shaping the waveform are provided at the boundaries between the units UNIT 3 and 4 for shaping the waveform of the propagation signal. Similarly, waveform shaping buffers 44 and 46 are provided in the signal propagation paths of the selectors SEL11, SEL13, and SELe. However, since the inverters 41 and 42 are provided on this path, these buffers 44 and 46 can be omitted.
[0057]
FIG. 9 shows a logic circuit obtained by extending the carry-for-parity generating circuit of FIG. 7 to an n-bit width. Also in this circuit, a plurality of unit circuits UNIT3 to UNITn are connected in cascade. The unit circuits UNIT1 and UNIT2 correspond to the unit circuits UNIT3 and UNIT4 in FIG. That is, the unit UNITk is repeated from k = 3 to n, and the output of the selector of the unit UNITn is input to the selector circuit SELe at the last stage.
[0058]
That is, the carry-for-parity generating circuit of FIG.
Either the generation bit g [1] of the addition inputs A [1] and B [1] or the inverted signal of the propagation bit p [1] is converted to the generation bits g [of the addition inputs A [2] and B [2]. A fifth selector SEL5 that selects and outputs the selected signal according to [2],
Either the generation bit g [1] or the inverted signal of the propagation bit p [1] is selected and output according to the addition bits A [2] and the propagation bit p [2] of B [2]. And a third unit UNIT 3 having six selectors SEL6.
[0059]
Then, either the output of the 2k-3 (where k is an integer of 1 to n-3) selector or the inverted signal of the output of the 2k-2 selector is added to the addition inputs A [k-1] and B [ k-1] selectors for selecting and outputting according to the generation bits g [k-1] of k-1];
Either the output of the 2k-3th selector or the inverted signal of the output of the 2k-2th selector is output to the addition bits p [k-1] of the addition inputs A [k-1] and B [k-1]. -1], and a k-th unit UNITk having a 2k-th selector for selecting and outputting according to -1] is repeatedly connected in cascade from k = 3 to n. That is, the third unit UNIT3 to the n-th unit UNITn are connected in cascade.
[0060]
Further, a final stage in which either the output of the 2n-1st selector or the inverted signal of the output of the 2n selector of the last unit UNITn is selected according to the carry-in Cin, and is output as the carry-for parity CPn. It has a selector SELe.
[0061]
In the logic circuit of FIG. 9 as well, it is preferable to provide a buffer gate between the units as shown in FIG. 8 to perform waveform shaping. In addition, since each selector is configured by a pass transistor, signal propagation can be speeded up, and generation of the carry-for-parity bit CPn can be sped up.
[0062]
As described above, the carry-for-parity signal generation circuit in the present embodiment can be configured with a small number of elements and a small number of inputs. Therefore, the parity prediction circuit of the full adder can be configured with a small number of inputs and a small number of elements. Moreover, by using a pass transistor for the selector, a carry-for-parity signal can be generated at high speed.
[0063]
As described above, the embodiments are summarized as follows.
[0064]
(Supplementary Note 1) From the addition inputs A [0: n−1, P] and B [0: n−1, P] with parity bits of n-bit width and the carry-in Cin, the addition value S [0 with prediction parity bits : N-1, P] in a parity prediction circuit in a full adder,
The predicted parity bit S [P] is composed of the parity bits A [P] and B [P] of the addition input and the carry bit c [i] (where i is an integer of 0 to n-1). It is generated by exclusive OR of the carry-or-parity CPn, which is an exclusive OR,
The arithmetic expression of the carry for parity CPn is:
CPn = Cin <cp [n, 1], cp [n, 0]>
(Where S <X, Y> outputs X when S = 1 and Y when S = 0, and furthermore, cp [n, 1] is the carry Carry-in parity CPn when in Cin = 1, and cp [n, 0] indicate carry-in parity CPn when carry-in Cin = 0, respectively),
The parity prediction circuit,
The carry for parities CP [k−1,0] and CP [k−1,1] when the carry-in Cin = 0 and 1 are input (where k is an integer of n or less), and an addition input A [k− 1] and B [k-1], either carry-in parity CP [k-1,0] or CP [k-1,1] according to generation bit g [k-1] of B [k-1]. A first selector for outputting as [k, 0], and the carry for parities CP [k−1, 0] and CP [k−1, 1] as inputs, and the addition inputs A [k−1] and B According to the propagation bit p [k-1] with [k-1], either the input CP [k-1,0] or CP [k-1,1] is carried for parity cp [k, 1] that outputs an inverted signal of [1]. It has a Tsu door,
The arithmetic units are connected in a plurality of stages and columns,
Furthermore, the final stage has a final stage selector that outputs either the carry for parity cp [n, 0] or cp [n, 1] as the carry for parity CPn according to the carry-in Cin. Parity prediction circuit.
[0065]
(Supplementary Note 2) In Supplementary Note 1,
A parity prediction circuit, wherein outputs of the first and second selectors of the arithmetic unit are connected in cascade so as to be supplied as inputs of a subsequent arithmetic unit.
[0066]
(Supplementary Note 3) In Supplementary note 2,
A parity predicting circuit, wherein each of the arithmetic units has an inverter connected to an output of the second selector.
[0067]
(Supplementary Note 4) In supplementary note 2,
A parity prediction circuit, wherein each of the operation units has a buffer gate between the operation unit and a subsequent operation unit.
[0068]
(Supplementary Note 5) In Supplementary Note 1,
The first, second, and last-stage selectors are configured by pass transistor circuits that use the generation bit g [k-1], the propagation bit p [k-1], and the carry-in bit Cin as control signals. A parity prediction circuit characterized in that:
[0069]
(Supplementary Note 6) Addition value S [0: 3, P] with a predicted parity bit from inputs A [0: 3, P] and B [0: 3, P] with a parity bit having a 4-bit width and carry-in Cin In a parity prediction circuit in a full adder for
The predicted parity bit S [P] is an exclusive logic of the input parity bits A [P] and B [P] and a carry bit c [i] (where i is an integer of 0 to 3) for each digit. It is generated by exclusive OR with the carry for parity CP4 that is the sum,
The parity prediction circuit has a circuit that generates the carry for parity CP4,
The carry-for-parity CP4 generation circuit includes:
Either the generation bit g [1] of the addition inputs A [1] and B [1] or the inverted signal of the propagation bit p [1] is converted to the generation bits of the addition inputs A [2] and B [2]. a first selector for selecting and outputting according to g [2];
Either the generation bit g [1] or the inverted signal of the propagation bit p [1] is selected and output according to the addition bits A [2] and B [2] of the propagation bit p [2]. A second selector to
Either the output of the first selector or the inverted signal of the output of the second selector is selected and output according to the generation bits g [3] of the addition inputs A [3] and B [3]. A third selector;
Either the output of the first selector or the inverted signal of the output of the second selector is selected and output according to the propagation bits p [3] of the addition inputs A [3] and B [3]. A fourth selector,
A final-stage selector that selects either the output of the first selector or the inverted signal of the output of the second selector according to the carry-in Cin and outputs the selected signal as the carry-for parity CP4. Characteristic parity prediction circuit.
[0070]
(Supplementary Note 7) In Supplementary note 6,
The parity prediction circuit further includes an inverter connected to outputs of the second and fourth selectors.
[0071]
(Supplementary Note 8) In supplementary note 6,
A parity predicting circuit, wherein the selector is constituted by a pass transistor circuit that allows any one of the inputs to pass according to a control signal.
[0072]
(Supplementary note 9) The addition value S [0: n−1, P] in a full adder,
The predicted parity bit S [P] is exclusive of the input parity bits A [P] and B [P] and the carry bit c [i] (where i is an integer from 0 to n-1) to each digit. Generated by an exclusive OR with a carry-or-parity CPn that is a logical OR,
The parity prediction circuit has a circuit that generates the carry for parity CPn,
The carry-for-parity CPn generation circuit includes:
Either the generation bit g [1] of the addition inputs A [1] and B [1] or the inverted signal of the propagation bit p [1] is converted to the generation bits of the addition inputs A [2] and B [2]. a fifth selector for selecting and outputting according to g [2];
Either the generation bit g [1] or the inverted signal of the propagation bit p [1] is selected and output according to the addition bits A [2] and B [2] of the propagation bit p [2]. A sixth selector,
Either the output of the 2k-3th (where k is an integer of 4 to n) selector or the inverted signal of the output of the 2k-2th selector is output to the addition inputs A [k-1] and B [k-1]. 2k-1 selector for selecting and outputting according to the generation bit g [k-1]
Either the output of the 2k-3th selector or the inverted signal of the output of the 2k-2th selector is output to the addition bits p [k-1] of the addition inputs A [k-1] and B [k-1]. -1] and a 2k selector for selecting and outputting the selected signal according to
The 2k-1th selector and the 2kth selector are repeatedly connected in cascade from k = 4 to n,
Further, a final-stage selector that selects either the output of the 2n-1 selector or the inverted signal of the output of the 2n selector according to the carry-in Cin and outputs the selected output as the carry-for parity CPn. A parity prediction circuit comprising:
[0073]
(Supplementary Note 10) In Supplementary Note 9,
The parity prediction circuit further includes an inverter connected to an output of the second k selector.
[0074]
(Supplementary Note 11) In supplementary note 9,
A parity predicting circuit, wherein the selector is constituted by a pass transistor circuit that allows any one of the inputs to pass according to a control signal.
[0075]
【The invention's effect】
As described above, according to the present invention, the parity prediction circuit of the full adder can be configured with a small number of inputs and a small number of elements.
[Brief description of the drawings]
FIG. 1 is a diagram showing a full adder and a parity prediction circuit applied to the present embodiment.
FIG. 2 is a logic circuit diagram of a carry-for-parity generating circuit 18;
FIG. 3 is a diagram showing an example of a circuit diagram of a pass transistor formed of a CMOS circuit.
FIG. 4 is a diagram for explaining carry for parity.
FIG. 5 is a logic circuit diagram for determining carry for parity CPn.
FIG. 6 is a diagram showing a unit circuit in a preceding stage.
FIG. 7 is a logic circuit of a circuit 18 for generating a carry-for-parity CP4 for a 4-bit wide full adder.
FIG. 8 is a modified example of the logic circuit of the circuit 18 for generating the carry-for-parity CP4 for the 4-bit width full adder.
FIG. 9 is a logic circuit of a circuit 18 that generates a carry-for-parity CPn for a full adder having an n-bit width.
[Explanation of symbols]
SEL selector, UNIT unit, g generation bit, p propagation bit, h half sum bit, A, B addition input, S addition value, Cin
Carry in, CPn Carry for parity

Claims (10)

From the addition inputs A [0: n−1, P] and B [0: n−1, P] with parity bits having n-bit width and the carry-in Cin, the addition value S [0: n−1 with prediction parity bits is obtained. , P] in the parity predicting circuit in the full adder,
The predicted parity bit S [P] is composed of the parity bits A [P] and B [P] of the addition input and the carry bit c [i] (where i is an integer of 0 to n-1). It is generated by exclusive OR of the carry-or-parity CPn, which is an exclusive OR,
The arithmetic expression of the carry for parity CPn is:
CPn = Cin <cp [n, 1], cp [n, 0]>
(Where S <X, Y> outputs X when S = 1 and Y when S = 0, and furthermore, cp [n, 1] is the carry Carry-in parity CPn when in Cin = 1, and cp [n, 0] indicate carry-in parity CPn when carry-in Cin = 0, respectively),
The parity prediction circuit,
The carry for parities CP [k−1,0] and CP [k−1,1] when the carry-in Cin = 0 and 1 are input (where k is an integer of n or less), and an addition input A [k− 1] and B [k-1], either carry-in parity CP [k-1,0] or CP [k-1,1] according to generation bit g [k-1] of B [k-1]. A first selector for outputting as [k, 0], and the carry for parities CP [k−1, 0] and CP [k−1, 1] as inputs, and the addition inputs A [k−1] and B According to the propagation bit p [k-1] with [k-1], either the input CP [k-1,0] or CP [k-1,1] is carried for parity cp [k, 1] that outputs an inverted signal of [1]. It has a Tsu door,
The arithmetic units are connected in a plurality of stages and columns,
Furthermore, the final stage has a final stage selector that outputs either the carry for parity cp [n, 0] or cp [n, 1] as the carry for parity CPn according to the carry-in Cin. Parity prediction circuit. In claim 1,
A parity prediction circuit, wherein outputs of the first and second selectors of the arithmetic unit are connected in cascade so as to be supplied as inputs of a subsequent arithmetic unit. In claim 2,
A parity predicting circuit, wherein each of the arithmetic units has an inverter connected to an output of the second selector. In Appendix 1,
The first, second, and last-stage selectors are configured by pass transistor circuits that use the generation bit g [k-1], the propagation bit p [k-1], and the carry-in bit Cin as control signals. A parity prediction circuit characterized in that: Appendix 6 (Supplementary Note 6) From the inputs A [0: 3, P] and B [0: 3, P] with a parity bit having a 4-bit width and the carry-in Cin, an addition value S [0: 3, with a predicted parity bit] P] in a parity predicting circuit in a full adder,
The predicted parity bit S [P] is an exclusive logic of the input parity bits A [P] and B [P] and a carry bit c [i] (where i is an integer of 0 to 3) for each digit. It is generated by exclusive OR with the carry for parity CP4 that is the sum,
The parity prediction circuit has a circuit that generates the carry for parity CP4,
The carry-for-parity CP4 generation circuit includes:
Either the generation bit g [1] of the addition inputs A [1] and B [1] or the inverted signal of the propagation bit p [1] is converted to the generation bits of the addition inputs A [2] and B [2]. a first selector for selecting and outputting according to g [2];
Either the generation bit g [1] or the inverted signal of the propagation bit p [1] is selected and output according to the addition bits A [2] and B [2] of the propagation bit p [2]. A second selector to
Either the output of the first selector or the inverted signal of the output of the second selector is selected and output according to the generation bits g [3] of the addition inputs A [3] and B [3]. A third selector;
Either the output of the first selector or the inverted signal of the output of the second selector is selected and output according to the propagation bits p [3] of the addition inputs A [3] and B [3]. A fourth selector,
A final-stage selector that selects either the output of the first selector or the inverted signal of the output of the second selector according to the carry-in Cin and outputs the selected signal as the carry-for parity CP4. Characteristic parity prediction circuit. In claim 5,
The parity prediction circuit further includes an inverter connected to outputs of the second and fourth selectors. In claim 5,
A parity predicting circuit, wherein the selector is constituted by a pass transistor circuit that allows any one of the inputs to pass according to a control signal. From the inputs A [0: n−1, P] with parity bits and B [0: n−1, P] and the carry-in Cin having the n-bit width, the addition value S [0: n−1, P] in a parity predicting circuit in a full adder,
The predicted parity bit S [P] is exclusive of the input parity bits A [P] and B [P] and the carry bit c [i] (where i is an integer from 0 to n-1) to each digit. Generated by an exclusive OR with a carry-or-parity CPn that is a logical OR,
The parity prediction circuit has a circuit that generates the carry for parity CPn,
The carry-for-parity CPn generation circuit includes:
Either the generation bit g [1] of the addition inputs A [1] and B [1] or the inverted signal of the propagation bit p [1] is converted to the generation bits of the addition inputs A [2] and B [2]. a fifth selector for selecting and outputting according to g [2];
Either the generation bit g [1] or the inverted signal of the propagation bit p [1] is selected and output according to the addition bits A [2] and B [2] of the propagation bit p [2]. A sixth selector,
Either the output of the 2k-3th (where k is an integer of 4 to n) selector or the inverted signal of the output of the 2k-2th selector is output to the addition inputs A [k-1] and B [k-1]. 2k-1 selector for selecting and outputting according to the generation bit g [k-1]
Either the output of the 2k-3th selector or the inverted signal of the output of the 2k-2th selector is output to the addition bits p [k-1] of the addition inputs A [k-1] and B [k-1]. -1] and a 2k selector for selecting and outputting the selected signal according to
The 2k-1th selector and the 2kth selector are repeatedly connected in cascade from k = 4 to n,
Further, a final-stage selector that selects either the output of the 2n-1 selector or the inverted signal of the output of the 2n selector according to the carry-in Cin and outputs the selected output as the carry-for parity CPn. A parity prediction circuit comprising: In claim 8,
The parity prediction circuit further includes an inverter connected to an output of the second k selector. In claim 8,
A parity predicting circuit, wherein the selector is constituted by a pass transistor circuit that allows any one of the inputs to pass according to a control signal.

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