JPH0398346A - Cell synchronization circuit - Google Patents

Abstract

PURPOSE:To attain high speed operation of a cell synchronization circuit and to facilitate circuit integration by applying pipeline processing to the CRC(cyclic redundancy check) operation. CONSTITUTION:A CRC arithmetic means has exclusive OR circuit networks 11, 13 dividing an input data 100 into plural number in the order of input and obtaining a residual in parallel with them by a generation polynomial as plural CRC partial arithmetic means. Then a latch circuit 12 and an exclusive OR circuit network 14 are provided, which processes outputs of the plural CRC partial arithmetic means in the order of input and obtains the residual by the generation polynomial as to the entire data series and the CRC operation is realized by the pipeline system. Thus, the parallel processing number is selected properly to realize a cell synchronization circuit at a desired operating speed regardless of 1-bit immediate shift form. Moreover, in the case of LSI processing, since the plural exclusive OR networks applying the plural CRC partial arithmetic operations are of the same constitution, the design of the LSI is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is used in digital communications. In particular, the present invention relates to a method of transmitting a cell in which a header is added to an information string as an information unit. For more details, please refer to CRC (cyclic re
(dunduncy chech) Since the data string with added bits is divisible by CRC calculation, the CRC bit is added to the header and transmitted, and on the receiving side, the data string that is divisible by CRC calculation is regarded as a synchronization pattern and cell synchronization is established. Regarding cell synchronization circuits.

The present invention enables high-speed operation of a cell synchronization circuit and facilitates integration by performing pipeline processing on CRC calculations.

[Conventional technology]

In order to detect and correct errors in received signals, a method is known in which a CRC bit is added to an information signal and then transmitted.

The CRC bits are given as the remainder when the information signal is divided by the generator polynomial. To obtain m CRC bits, an m-th order generator polynomial is used. The data string to which this CRC bit is added is the same generator polynomial or a polynomial obtained by factorizing the polynomial, for example, m- D by CRC operation (division) using first-order generator polynomial
It has the property that all 1 bits are ``0'' (divisible).

FIG. 3 shows an example of how CRC bits are used. In this example, when the transmission unit is a cell with a header added to the information string, the header is a signal indicating the destination and a C
This uses the RC bit.

When transmitting cells, if a data string with a CRC bit added as a header is used, this can be used for cell synchronization. In other words, when the header length is n bits, if no bit errors occur on the transmission path, CR
Since the remainder when a data string of code length n bits including C bits is divided by the CRC calculation circuit is all bits "0", this pattern is regarded as a cell synchronization pattern and cell synchronization is performed.

FIG. 4 is a block diagram showing an example of a CRC calculation circuit. Here, we will show a general example when the generating polynomial is x8+x''+x+1. Operates on data clock.

Here, the code length n is assumed to be 40 bits. If the contents of the flip-flops F1 to F8 are all set to "0" at the beginning, when the input of the 40-bit code is completed, the data arranged in the flip-flops F1 to F8 becomes the remainder of the CRC operation. A pattern in which all bits are "0" as a remainder is used as a cell synchronization pattern.

This method usually requires a 1-bit instant shift type cell synchronization circuit in order to shorten the cell synchronization recovery time. That is, it is necessary to execute the CRC operation for a code length of n bits within one clock of the human data string. For this purpose, it is utilized that in the above calculation, the data ultimately remaining in each flip-flop F1 to F8 is the cumulative value of the CRC calculation for each bit of a 40-bit code. That is, if each bit of the 40-bit code is represented by D1 to D40, the data 21 to Z8 that ultimately remain in the flip-flops F1 to F8 are as follows. However, "+" indicates exclusive OR. FIG. 5 shows a block diagram of a conventional cell synchronization circuit using equation (1).

This cell synchronization circuit consists of a 40-bit long shift register l.
1 exclusive OR circuit network 2, latch circuit 3, OR circuit 4
, AND circuits 5 and 6, a frame synchronization protection circuit 7, a frame counter 8, and an AND circuit 9 with an inverter input. Input data 100 and a clock 200 extracted from this input data 100 are manually input to the shift register 1. Further, the same clock 200 is supplied to the latch circuit 3 and the AND circuit 9.

The shift register 1 shifts data using a clock 200.

The exclusive OR circuit network 2 performs the calculation of equation (1) and outputs data ZI-Z8. D1 to D4o in equation (1) correspond to the outputs of the flip-flops Fl to F40 in the shift register 1.

The frame synchronization protection circuit 7 is constituted by, for example, a reset counting type circuit. In a reset counting type circuit, when "1" is input continuously, the internal state becomes set state, and the output becomes "1" indicating frame synchronization is out.
”. Further, when "0" is input continuously, the internal state becomes a reset state, and the output becomes "0" indicating a frame synchronization state.

Here, assuming that the output of the frame synchronization protection circuit 7 is "1", the synchronization recovery operation of this cell synchronization circuit will be explained.

First, shift register l shifts input data using a clock and outputs 40 new pieces of data. This output is subjected to a CRC operation by the exclusive OR circuit network 2, and the obtained data Z, to Z8 are output to the latch circuit 3. The latch circuit 3 takes in data 21 to Z8 at the next clock. At the same time, shift register 1 shifts the data,
Exclusive OR network 2 performs CR for the new 40 bits.
Perform C calculation.

If the input data of the exclusive OR circuit network 2, that is, the contents of the shift register 1, is a correct 40-bit long code including the CRC bit (if a header is input), or if it is a data string of the same series as that, , data ZI
~Z8 are all "0". However, most of the time other than that, at least one of the data 21 to Z8 is "1" and the output of the OR circuit 4 is "1".

When no frame pulse appears in the frame counter 8, the output of the AND circuit 5 becomes "0", so the output of the AND circuit 6 becomes "0", and a clock is obtained at the output of the AND circuit 9. Frame counter 8 continues counting operation. When a frame pulse appears at the output of the frame counter 8, the output of the AND circuit 5 becomes "1", so the AND circuits 6 and 9 cause the frame counter 8 to change the output of the OR circuit 4 from the next input clock. The counting operation is stopped until the count reaches "0", and the state in which frame pulses are output is maintained.

The contents of shift register 1 are correct including the CRC bits 4
When the code has a length of 0 bits, the output of the OR circuit 4 becomes "0" at the next clock, at which point cell synchronization is restored, and the frame counter 8 starts counting at the next clock. After that, the output of the OR circuit 4 becomes "0" at the frame pulse position, so the frame synchronization protection circuit 7
"0" is continuously input to , and the frame synchronization protection circuit 7 goes into a reset state and then into a synchronized state.

Although the latch circuit 3 is used in this circuit, the output of the exclusive OR network 2 can also be input directly to the OR circuit 4.

[Problem to be solved by the invention]

In order for the conventional cell synchronization circuit shown in FIG.
must be less than l clocks. Furthermore, when the latch circuit 3 is not used, the sum of the above-mentioned delays plus the delays caused by the OR circuit 4 and the AND circuits 5 and 6 must be less than one clock.

However, in order for the exclusive OR circuit network to perform the CRC operation at once, it is necessary to pass the signal through the exclusive OR circuits connected in multiple stages. In the example shown in FIG. 5, the signal passes through up to five stages of exclusive OR circuits. The delay time per stage of the exclusive OR circuit is equal to or greater than the delay time of a flip-flop, which is a component of a shift register and a latch circuit.

Therefore, this cell synchronization circuit is not suitable for high-speed operation.

However, it is also possible to speed up the cell synchronization circuit shown in FIG. 5 by providing a latch circuit in the middle of the exclusive OR network. However, this requires an increase in the amount of hardware. In the example shown in FIG. 5, shift register l1
The combined hardware scale of the exclusive OR circuit network 2 and the latch circuit 3 is 89 exclusive OR circuits and 48 flip-flops, assuming that the same arithmetic circuit is used. In order to increase the speed, 11 flip-flops are required to provide a latch circuit between the 4th and 5th stage exclusive OR circuits of the exclusive AND circuit 2. To further speed up 3
In order to provide a latch circuit between the exclusive OR circuits of the 4th and 4th stages, nine additional flip-flops are required.

In addition, such an exclusive OR circuit network has a complicated connection structure, which makes wiring design difficult when integrated.

An object of the present invention is to solve the above problems and provide a cell synchronization circuit that can operate at high speed and is easy to integrate.

[Means to solve the problem]

In the cell synchronization circuit of the present invention, the CRC calculation means divides the data string of the received cell into a plurality of parts in the order of input, performs CRC calculation on each in parallel, processes the calculation results in the above-mentioned manual order, and processes the data string as a whole. It is characterized by finding the remainder by the generator polynomial for .

That is, CRC partial calculation means that perform parallel processing are connected in cascade via latch circuits, and the CRC calculation is processed in a pipeline.

The cell synchronization circuit of the present invention transmits a cell in which a header with a code length of n bits including m CRC bits is added to an information string as a unit, and on the receiving side, the CRC bits are used to detect errors in signals in the header. In a transmission system that performs correction, CRC bits are used to establish cell synchronization.

11 12 Each of the CRC partial calculation means uses the m-th order generator polynomial used to obtain the C'RC bit on the transmitting side, or if this m-th order generator polynomial can be separated into 1st-order and m-1-th order generator polynomials. CRC using an m-1 order generator polynomial for
Perform calculations. In the following, the degree of the generator polynomial used by the CRC partial calculation means will be expressed as "m'".

Here, it is assumed that the number of bits processed by each CRC partial calculation means is expressed by the number of parallel processing l, and this value is the same for each CRC partial calculation means. However, 1≦R<n. Further, let the quotient of n divided by 1 be [n/1], and the remainder be R.

The data string of the received cell is [
n/A] (#-1>+1, if n is not divisible by l, it is input to a shift register with a length of [n/j!)(f-1)+R. This shift register operates with the clock of the data string.

A CRC portion is calculated for each of the outputs of the first to lth stages from the head of this shift register, and the m' bit outputs are inputted to the m' flip-flops of the first stage, respectively, using the above clock. Each output of the m' flip-flops in the first stage and Il to 2l-1 from the beginning of the shift register
The CRC parallel partial calculation is performed again using each output of the second stage, and the m' outputs are inputted to the m' flip-flops of the second stage using the above clocks.

Similarly, from the beginning of the shift register above, [n/R]<1
-1) -j! +2 ~[n/ji! ') (A-1
) + each output of the first stage and I:n/j! ]-1st stage m′
CRC parallel partial calculations are performed using the respective outputs of the flip-flops, and the m' outputs are inputted to the m' flip-flops at the [n/1] stage using the above clock.

If n is not divisible by l, then from the beginning of the shift register (n/A) (j!-1>-1~(n/A)
(A-1) Each output of the 10th R stage and m of the [n/l] stage
A parallel CRC calculation is performed using each output of the ' flip-flops, and the m' outputs are manually inputted to the m' flip-flops in the Cn#)+1st stage using the above clock.

13 14 The outputs of the m' flip-flops in the final stage obtained in this manner are logically summed, and the logical product of this logical sum and the output (frame pulse) of the frame counter operating with the above clock is calculated as a frame. Input to synchronization protection circuit. If the logical product of this logical product and the output of the frame synchronization protection circuit is "1", the counting operation of the frame counter is stopped for one clock.

[For production]

In order for the cell synchronization circuit to operate, it is sufficient that the delay of each CRC partial calculation means that performs parallel processing is one clock or less. Further, by reducing the number of parallel processes l, the scale of the CRC partial calculation means becomes smaller and the delay time becomes shorter. Therefore, the operation of the cell synchronization circuit can be made faster. moreover,
By appropriately selecting the number of parallel processes, a cell synchronization circuit with a desired operating speed can be realized.

Further, if the number of parallel processing is the same, all the CRC partial calculation means have the same structure. Therefore, design for integration becomes easy.

〔Example〕

FIG. 1 is a block diagram of a cell synchronization circuit according to a first embodiment of the present invention. This example shows a case where the code length n is 40 bits, the generating polynomial of the CRC calculation means is x8+x2+x+'l, and the number of parallel processings of the CRC partial calculation means is 20.

This cell synchronization circuit uses a receiving cell to which a header including a CRC bit is added to a digital information string manually, and calculates a remainder using a generating polynomial equivalent to that used to obtain the above CRC bit for the data string of this receiving cell. C
Exclusive OR circuit networks 11, 13, 1 as RC calculation means
4 and a latch circuit 12, as means for establishing cell synchronization by detecting from the output of the CRC calculation means that the data string is divisible by the generating polynomial, the latch circuit 3, the OR circuit 4, and the AND circuit. 5, 6, a frame synchronization protection circuit 7, a frame counter 8, and an AND circuit 9 with an inverter input.

The data string of the received cell is supplied to the shift register l as input data 100, and furthermore, a clock 200 extracted from this input 15 16 data 100 is input. Further, the same clock 200 is supplied to the latch circuit 3 and the AND circuit 9.

Here, the feature of this embodiment is that the CRC calculation means uses exclusive logic as a plurality of CRC partial calculation means that divides the input data 100 into a plurality of parts in the order of the number of people and calculates the remainder by the above-mentioned generator polynomial for each part in parallel. sum circuit network 1
1. ．． 13, and a latch circuit 12 and an exclusive OR circuit network 14 as means for processing the outputs of the plurality of CRC partial calculation means in the input order and obtaining a remainder by the generator polynomial for the entire data string. There is a particular thing.

Regarding the circuit structure for performing CRC calculations by parallel processing, see ``Parallel Scrambling Techniques for Digital Multiplexers'', AT&T Technical Journal Vol. 65, September 10, 1986.
("Parallel scrambling tech
hniques for digital multi
plexers”, AT&T technical
journal, sep, /oct, l936,
It can be obtained in the same manner as the parallelization method of a self-synchronous scrambler shown in Vol. 65).

According to this document, the circuit configuration when the number of parallel processes is 20 is the matrix given by equation (2). From Ts
"Ts".

is shown in equation (3).

(Hereinafter, this page margin) l7 18 19 The lower right part of the matrix divided into four parts in equation (2) shows the following states of the flip-flops F1 to P8 in the CRC calculation circuit shown in Fig. 4. shows. For example, Max IJxT. The 21st line shows that the next state of flip-flop F2 is the exclusive OR of the input data and the contents of flip-flop FB.

Further, when input data is expressed as D1 to D20, the 20th column indicates D1, the 19th column indicates D2, and the 1st column indicates D20.

Therefore, the flip-flop 11 in the current state
Letting the contents of ~F8 be F1~Fa, respectively, the contents of flip-flops F1~F8 in the next state Z1~Z
8 becomes - (4) from equation (3). Here, "+" represents exclusive OR.

Exclusive OR circuit network 11 of the cell synchronization circuit shown in FIG.
In equation (4), F + = F 2 = F
3 = F 4Fs =;F6 =F”, =Fll =
O, D1 to D2.

21 corresponds to the outputs of the 20th flip-flops F1 to F20 from the beginning of the shift register 1. The output of this exclusive OR network 11 corresponds to the values of F1 to F8 in equation (4). Further, the circuit structure of the exclusive OR circuit network 13 is the same as that of the exclusive OR circuit network 1l, except that the manual data has been shifted by 19 bits. The output of this exclusive OR network 13 is (
This corresponds to the terms D1 to D20 in equation 4). The exclusive OR circuit network 14 calculates the values of Z1 to Z8 in equation (4) from the outputs of the exclusive OR circuit networks 1l and 13, and
Output to.

Since the code length is 40 bits, the CRC operation must be performed on continuous 40 bits of input data. In this embodiment, exclusive OR circuit networks 11 and 13 each perform a 20-bit operation, and the results are processed by exclusive OR circuit network 14.

That is, the exclusive OR circuit network 11 performs a CRC partial operation on each output of the first flip-flop F1 to the 20th flip-flop F20 of the shift register 1, and inputs the result to the latch circuit 12. At this time, the data in the flip-flops F21 to F39 are shifted by l bits to the flip-flops F20 to F38, and new data is input to the flip-flop F39. The exclusive OR circuit network 13 performs a CRC partial operation on the data of the flip-flops F20 to F39 when new data is input. The distance between the input data positions of the exclusive OR network 1l and 3 is not 20 bits but <19 bits.

The exclusive OR circuit networks 11 and 13 perform a CRC partial operation on new input data every clock.

However, based on the data side, the operation of the exclusive OR circuit network 1l is 11 compared to the operation of the exclusive OR circuit network 13.
The clock is ahead. By storing the output of the exclusive OR circuit network 1l in the latch circuit 12, the timings of both coincide. The exclusive OR circuit network 14 receives the output of the latch circuit 12 and the output of the exclusive OR circuit network 13.
The remainder of the CRC operation for the entire data string is determined and the result is output to the latch circuit 3. As a result, latch circuit 3
, the remainder of the CRC operation is obtained every clock.

The operations of the latch circuit 3, OR circuit 4, AND circuits 5, 23 24 6, frame synchronization protection circuit 7, frame counter 8, and AND circuit 9 are the same as in the conventional example shown in FIG.

In this embodiment, the latch circuit 3 can be omitted, but in that case, the signal delay time increases.

The maximum delay time of the exclusive OR circuit networks 11, 13, and 14 in this embodiment is equivalent to four stages of exclusive OR circuits. Moreover, shift register 1, latch circuit 3,
12. All the hardware of the exclusive OR circuit networks 11, 13 and 14 is 88 exclusive OR circuits and 55 flip-flops. Compared to the case where a latch circuit is provided between the fourth and fifth stage exclusive OR circuits of the exclusive OR circuit network, the amount of hardware is smaller.

Furthermore, in the cell synchronization circuit of this embodiment, the exclusive OR circuit networks 11 and 13 have the same structure, making LSI design easy. Furthermore, since the scale of one exclusive OR circuit network is small, there are fewer crossings of wires and fewer connections between wiring layers, which facilitates LSI wiring design.

FIG. 2 shows a block diagram of a cell synchronization circuit according to a second embodiment of the present invention.

In this embodiment, the code length n is 40 bits, and the generating polynomial of the CRC calculation means is x8. +x2+x+l, which shows the case where the number of parallel processings of the CRC partial calculation means is 8.

This embodiment is characterized in that exclusive OR circuit networks 22, 24, 26 and 28 are connected in cascade via latch circuits 23, 25 and 27, respectively, as CRC partial calculation means. The human power of the exclusive OR circuit network 22 is as follows:
A latch circuit 21 is provided.

The circuit structure of this embodiment is obtained by determining Ts8 from the matrix T5, as in the first embodiment.

The operation of this embodiment is such that the number of CRC partial operations increases and C
Just by increasing the number of pipeline processing stages of RC operation,
This is equivalent to the first embodiment.

Although the amount of hardware required for this embodiment is increased compared to the first embodiment, the maximum delay amount for the CRC partial calculation is equivalent to three stages of 25 26 exclusive OR circuits. Therefore, it is suitable for high-speed operation. In addition, exclusive OR circuit networks 22, 24,
Since 26 and 28 have the same circuit structure repeated, LSI design becomes easy.

Note that under the same conditions that the code length is 40 bits and the generator polynomial of the CRC operation is x' + x' + This is equivalent to 3 stages of sum circuit.

The hardware in this case is 83 exclusive OR circuits and 69 flip-flops.

In the conventional example, the conditions for giving the same operating speed are:
This is a case where a latch circuit is provided between the third and fourth stage exclusive OR circuits of the exclusive logic circuit network, but the amount of hardware is smaller than in that case.

In the above explanation, the code length n is 40 and the generator polynomial is x8+
Although the case where x2+x+1 and the code length n is divisible by the number of parallel processes l has been described, the present invention can also be practiced with other values of the code length, other generator polynomials, and cases where n is not divisible by l.

In addition, in the above embodiment, for a data string of code length n-40 bits including m CRC bits, which is the remainder of division by a generator polynomial of degree m=8, the cell synchronization circuit uses a generator polynomial of degree m. An example of CRC calculation using . However, the m-th order generator polynomial on the transmitting side is first-order and m-1
If the cell synchronization circuit can be separated into the following, the present invention can be implemented in the same way even if the cell synchronization circuit performs the CRC operation based on the m-1 order generator polynomial. For example, the generator polynomial x8+x2+x+
1 is (x+l) (x'+x6+x5+x'
+x'+l), the cell synchronization circuit may perform the CRC calculation using the generator polynomial x'+x6+x5+x'+x2+l.

〔Effect of the invention〕

As described above, the cell synchronization circuit of the present invention realizes the CRC operation in a pipeline format by cascade-connecting exclusive OR circuit networks that perform CRC partial operations through parallel processing via latch circuits. Therefore, by appropriately selecting the number of parallel processes, it is possible to realize a cell synchronization circuit with a desired operating speed even though it is a 1-bit instant shift type, which has the effect of increasing the degree of freedom in design.

In addition, when implementing LSI, multiple exclusive OR networks that each perform CRC partial operations have the same structure, so L
This has the effect of facilitating the design of SI.

Furthermore, since the hardware scale of each circuit that performs CRC partial calculations is reduced, there are fewer intersections between wiring lines, and LCI
This has the effect of facilitating wiring design.

1...Shift resist, 2, 11, 13, 14, 22
, 24, 26, 28... exclusive OR circuit network, 3, 1
2, 21, 23, 25, 27... latch circuit, 4...
・OR circuit, 5, 6, 9...AND circuit, 7...
Frame synchronization protection circuit, 8...Frame counter, 3
0: Exclusive OR circuit, F1 to F40: Flip-flop.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a cell synchronization circuit according to a first embodiment of the present invention. FIG. 2 is a block diagram of a cell synchronization circuit according to a second embodiment of the present invention. FIG. 3 is a diagram showing the structure of a cell in which a CRC bit is added in the header. FIG. 4 is a block diagram showing an example of a CRC calculation circuit. FIG. 5 is a block diagram of a conventional cell synchronization circuit. 29 30 JP-A-3 98346 (11)

Claims (1)

[Scope of Claims] 1. A received cell in which a header including a CRC bit is added to a digital information string is input, and a remainder obtained by a generating polynomial equivalent to that used to obtain the above-mentioned CRC bits for the data string of this received cell. In the cell synchronization circuit, the cell synchronization circuit includes a CRC calculation means for calculating the CRC calculation means, and a means for establishing cell synchronization by detecting from the output of the CRC calculation means that the data string is divisible by the generation polynomial, the CRC calculation means comprising: A plurality of CRC partial calculation means divides the data string into a plurality of parts in the order of input, and calculates a remainder by the generator polynomial for each part in parallel; and a plurality of CRC partial calculation means process the outputs of the plurality of CRC partial calculation means in the order of input, A cell synchronization circuit comprising: means for determining a remainder by the generator polynomial for the entire column.