JPH03216037A - Cell synchronizing circuit - Google Patents

Abstract

PURPOSE:To adopt a byte processing form receiver including a cell synchronization circuit by providing a delay means delaying an input data by a code length. CONSTITUTION:A delay means 13 is provided, which retards an input data by a code length (N bits) and after each flip-flop of a CRC arithmetic circuit 22 is reset, while taking a period of the CRC arithmetic circuit 22 as M, an input data is inputted to the CRC arithmetic circuit 22 by a code length (N bits) and an output of the delay means 13 is inputted for each bit while the internal state of the CRC arithmetic circuit 22 is shifted by [M-N] number of times without no input, and a succeeding bit of the input data is inputted while the internal state is shifted by [N-1] number of times without any input repetitively. In this case, the relation between the code length N and the period M of the CRC arithmetic circuit 22 is set optionally within a range that [M-N] is positive or zero. Thus, no restriction exists in cell structure, the header, the CRC bit and the information string in the cell are selected as an integral number of multiple of 8-bit and a byte processing type receiver is adopted including the cell synchronization circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is used in digital communications. In particular, the present invention relates to a method of transmitting a cell in which a header is added to an information string as an information unit. For more details, convert a certain data string to C R C
(cyclic redur1duncy chech
) Since the data string obtained by adding the CRC bit, which is the remainder of the operation, to the original data string is divisible by the CRC operation, the CRC bit is inserted in the header and transmitted, and the receiving side creates a data string that is divisible by the CRC operation. The present invention relates to a cell synchronization circuit that establishes cell synchronization by regarding it as a synchronization pattern.

The present invention uses a code shorter than the CRC operation cycle in a cell synchronization circuit that detects a CRC code to establish synchronization, so that the internal state of the CRC operation circuit is locked for one night and equivalently
By inputting data delayed by the code length and new data to the CRC calculation circuit to complete the RC calculation cycle, cell structure constraints are removed and the C
This increases the number of RC bits.

Furthermore, the present invention makes it possible to reliably establish cell synchronization even if a bit error occurs in an out-of-synchronization state.

[Conventional technology]

FIG. 6 shows an example of a cell configuration used in the cell transmission system.

The cell transmission method is an information transmission method in which an information string is divided into cells of a fixed bit length and transmitted, and each cell is attached with a header containing a bit string indicating its destination (hereinafter referred to as "destination information"). Ru. Furthermore, in order to detect and correct errors in destination information, CRC bits are added to destination information.

In the example shown in FIG. 6, N bits obtained by adding K CRC bits to the destination information are added to the information string as a header. That is, the code length is N. The CRC bit is the remainder when the bit string of the destination information is divided by the CRC calculation circuit, and the number of bits K i;! Equal to the order of the C R C calculation circuit.

The original purpose of using CRC bits is error detection and correction, and when this CRC bit is added to the data string from which the CRC bits are obtained, the data string becomes CRC
It takes advantage of the property that it is divisible by RC calculation. This property of being divisible by CRC calculation can be used to establish cell synchronization.

That is, cell synchronization can be established by regarding a data string that is divisible by CRC calculation as a synchronization pattern.

FIG. 7 is a block diagram of a conventional cell synchronization circuit that establishes cell synchronization by CRC calculation. This conventional example is a circuit shown in Japanese Patent Application No. 63-101917, where 1 is received data, 2 is a clock for received data 1, 3 is a shift register with a length of N bits, 4aq 4b, 4C are AND circuits, 5a and 5b are AND circuits with inverters, 6 is an exclusive OR circuit, 7 is a flip-flop, 8 is a CRC calculation circuit, 9 is an OR circuit, 10 is a frame counter, 11
is a frame pulse, 12 is a hunting pulse, 13 is a delay circuit, 14 is a synchronization protection circuit, 15 is a differentiation circuit, 16 is a control circuit, 17 is a reset pulse, 18 is an AND circuit 4
a control signal, 19 a reset pulse, and 20 an OR circuit.

The shift register 3 shifts the received data 1 by one bit each time the clock 2 is input, thereby delaying the received data 1. The length of the shift register 3 is equal to the code length N.

In this example, the CRC calculation circuit 8 uses an 8th order generator polynomial x8
This corresponds to +x2+X+l.

That is, eight flip-flops 7 connected in cascade and three exclusive OR circuits 6 that add the output of the final stage flip-flop 7 to the inputs of the first, second, and third stages, respectively, are used. This is a circuit in which all outputs of the flip-flop 7 become "0" when the input data is divisible by the above-mentioned generating polynomial. This CRC calculation circuit 8 outputs the outputs of eight flip-flops 7 in parallel.

The OR circuit 9 is configured so that the output of the CRC calculation circuit 8 is
0, the pattern matching detection result is output. This output is a logic "0". When the pattern does not match, the logic “
1" is output.

The frame counter 10 counts input clocks and outputs a frame pulse l1 having a width of one clock every time the count value corresponds to one cell period. The frame counter 10 also outputs a reset pulse 19 at a time N clocks before the frame pulse 11.

The synchronization protection circuit 14 receives the logical product of the frame pulse 11 and the output of the logical sum circuit 9 output from the logical product circuit 4b at the time position of the frame pulse 11.

As a result, the synchronization protection circuit 14 enters a set state when pattern mismatch is continuously detected at the time position of the frame pulse 11, and sets its output to logic "1". Further, when pattern matching is continuously detected at the time position of the frame pulse 11, a reset state is entered, and the output is set to logic "0".

When in the set state, the synchronization protection circuit 14 is in a backward protection state, indicating a state where cell synchronization is out. On the other hand, when in the reset state, the synchronization protection circuit 14 is in a forward protection state, indicating a cell synchronization established state.

The differentiating circuit 15 has an input that changes from logic "0" to logic "1".
outputs a short trigger pulse when the signal changes to . The control circuit 16 is activated by this trigger pulse and outputs a clock-synchronized reset pulse 17 and a control signal 1.
Outputs 8. The output timing of the reset pulse 17 may be delayed from the trigger pulse input. Control signal 1
8 is a signal that is at logic "0" for N clocks immediately after the reset pulse l7 and remains at logic "1" thereafter.

The operation of this synchronous cell circuit from the state out of cell synchronization to the state in which cell synchronization is established will be explained.

First, when the synchronization protection circuit 14 shifts from the cell synchronization established state to the cell synchronization out state, it changes its output to logic "1". - Therefore, the AND circuit 5b is in a gate-off state, and the ON/OFF state of the gate of the AND circuit 4a is determined only by the control signal 18. Further, the differentiating circuit 15 outputs a trigger pulse, and the control circuit 16 is activated. As a result, the control circuit 16 outputs the reset pulse 1.
7 and a control signal 18.

When the CRC calculation circuit 8 is reset by the reset pulse 17, the AND circuit 4a is operated for N bits immediately after that.
is turned off by the control signal 18, and N bits of received data 1 are input to the CRC calculation circuit 8. As a result, the eight flip-flops 7 in the CRC calculation circuit 8 output the calculation results for the reset N bits of the received data 1. Here, the value of N is CRC
If it is equal to the period M of the arithmetic circuit 8, the internal transition state of the CRC arithmetic circuit 8 will be the same state as immediately after reset.

Thereafter, the control signal 18 turns on the gate of the AND circuit 4a. Therefore, the exclusive OR of the received data 1 and the bits obtained by delaying the received data 1 by N bits is input to the CRC calculation circuit 8. The first bit after the gate of the AND circuit 4a is turned on is the same bit as the first bit after the CRC calculation circuit 8 is reset, and is input to the CRC calculation circuit 8 from the output of the shift register 3. become.

In the CRC calculation circuit 8, when the same bit is input an even number of times at the same internal state position, since all internal operations are exclusive OR operations, they cancel each other out, and as a result, it is determined that the bit was not input. become equivalent. therefore,
This means that the reset position of the CRC calculation circuit 8 is shifted backward by one bit. Furthermore, since the received data 1 is also input at the same time, the flip-flop 7 of the CRC calculation circuit 8 can obtain the calculation result for the input data from the second bit after being reset by the reset pulse 17.

When the output of the synchronization protection circuit 14 is logic "1", the output of the AND circuit 4b is logic "1", that is, when the pattern does not match at the time position of the frame pulse 11, the AND circuit 4C is hunting logic "1". Output pulse 12.

This hunting pulse 12 is delayed by a delay circuit 13, and inhibits the next input clock in the AND circuit 5a with an inverter. For this reason, the frame counter 10 is
The state in which the frame pulse 11 is output is maintained.

However, when a pattern match is detected in the OR circuit 9 and the output of the AND circuit 4b becomes logic "0", the frame counter 10 restarts the counting operation because a new clock is input from the next clock.

If the time position of the pattern match detection is the true pattern match detection position, that is, the final hit position in the header of the received data 1, the output of the AND circuit 4b is continuously at the time position of the frame pulse 11. 0". Therefore, the synchronization protection circuit 14 is reset, and its output becomes the logic "
0'', and cell synchronization is established.

When the output of the synchronization protection circuit 14 becomes logic "0", the AND circuit 5b becomes gate-on, so the reset pulse 19 becomes valid, and the AND circuit 4a becomes gate-on. Therefore, the output of the shift register 3 is no longer input to the CRC calculation circuit 8.

Therefore, from now on, the CRC calculation circuit 8 sends the calculation result for only the header portion of the received data 1 to the OR circuit 9 at the time position of the frame pulse 11. As a result, even if an error occurs in a bit in the header part on the transmission path, synchronization is protected by the synchronization protection circuit 14, and the cell synchronization circuit can maintain the cell synchronization established state.

[Problem to be solved by the invention]

However, in the conventional cell synchronization circuit described above, it is necessary to match the period M of the CRC calculation circuit with the length N of the header, which is the code length. Generally, the period M of the generator polynomial is [2K1] when its degree is K-th. However, in the case of the generator polynomial X8+x2+x+l mentioned above, CX+
Since it can be decomposed into the 11th-order term and another 7th-order term, the period M is determined by the 7th-order term, and 2'-1=127. Therefore, in this case, the code length must be 127 bits. Furthermore, the period M is always an odd number.

Due to such limitations, there remains the problem that restrictions are imposed on the cell structure in order to use the above-described cell synchronization circuit. In particular, this poses a major restriction when selecting the header and the information strings in the cells to be integral multiples of 8 bits and making the receiving device including the cell synchronization circuit a byte processing type.

In addition, in order to match the code length N with the period M, the code length N
CRC bit number K cannot be set large for
There remained the problem that the bit error correction ability and bit error detection ability within the header could not be improved.

Furthermore, since the number of bits of the synchronization pattern (equal to the degree of the generating polynomial) for which synchronization pattern match detection is determined is very small compared to the code length N, pseudo synchronization pattern match detection is performed at a point that is not a normal synchronization pattern detection position. The problem remained that the probability of

Further, in the conventional example described above, if a bit error occurs due to noise or other factors in the CRC calculation circuit or shift register when the synchronization is out of synchronization, the CRC calculation circuit will forever be unable to obtain a correct calculation result for the input data. For this reason, the cell synchronization circuit may become permanently unable to shift to the cell synchronization established state.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cell synchronization circuit that solves the above-mentioned problems, removes restrictions on cell structure, and can increase the number of CRC bits relative to the code length.

A further object of the present invention is to provide a cell synchronization circuit that can reliably establish cell synchronization even if a bit error occurs in an out-of-synchronization state.

[Means to solve the problem]

The cell header has a code length N set to be shorter than the period M of the generator polynomial, and is equipped with a delay means for delaying the input data string by N bits, so that the CRC calculation circuit takes in the N-bit data string after being reset, and then outputs the data string. Every clock, the internal state of the CRC calculation circuit changes without any new input.
After shifting M-Nl times, the output of the delay means is this CR.
The output of the delay means and the new data are input to the CRC calculation circuit, and the new data is input to the CRC calculation circuit with its internal state shifted [N-1] times without any new input. and means for inputting the CRC to the CRC calculation circuit.

It is preferable to provide resetting means for resetting the internal state of the CRC calculation circuit when the internal state of the CRC calculation circuit does not shift to the cell synchronization state even after a predetermined period of time has elapsed from the initial state in which the internal state was reset. .

[Function] After resetting each flip-flop of the CRC calculation circuit, input the input data string for the code length (N bits) to the CRC calculation circuit, and the CRC calculation result for the data from the 1st bit to the Nth bit after reset is generated. is obtained. After this, the internal state of the CRC calculation circuit is CM
-N), input the 1st bit data after reset to this, and with no further input [:N-1]
When the CRC operation is completed, one cycle of CRC calculation is completed, and the CR
The data contribution is removed from the C arithmetic circuit. Furthermore, when new data, that is, the N+1-th bit data, is input to the CRC calculation circuit, the CRC for N-bit data from the 2nd bit to the N+1-th bit is
An RC calculation result is obtained. Similarly, a CRC calculation result is obtained for each input bit.

However, actually shifting the internal state of the CRC calculation circuit requires shifting M times for each clock of the input data string. Therefore, in the present invention, the connection between the output of the delay means and the CRC arithmetic circuit is selected to perform equivalent shifting M times.

With this configuration, the code length N and the period M of the CRC calculation circuit can be set to unrelated values within the range where [MN] is correctly positive or zero.

Therefore, there are no restrictions on the cell structure, and the header, CRC bits, and information string in the cell can be selected to be an integer multiple of 8 bits, so the receiving device including the cell synchronization circuit can be of a byte processing type. becomes.

In addition, since the number of CRC bits K can be increased relative to the code length N, the bit error correction ability and bit error detection ability in the header can be improved, and the number of bits in the synchronization pattern used for synchronization pattern matching detection and determination can be increased. Therefore, the probability of pseudo synchronization pattern matching detection at a point that is not a normal synchronization pattern detection position decreases.

Furthermore, in the present invention, if the cell synchronization establishment state is not reached even after a certain period of time has passed from the initial state in which each flip-flop in the CRC calculation circuit is reset, each flip-flop in the CRC calculation circuit is reset again to the initial state. Return to As a result, even if a bit error occurs due to noise or other factors in the CRC calculation circuit or the delay means during an out-of-synchronization state, the operation of the cell synchronization circuit will not be impaired.

〔Example〕

FIG. 1 is a block diagram of a cell synchronization circuit according to a first embodiment of the present invention.

This example circuit takes as input a cell in which a header including a CRC bit is added to a digital information string, and uses a generating polynomial equivalent to that used to obtain the CRC bit for the data string composing this cell, that is, received data 1. Exclusive OR circuit 6 as a CRC calculation circuit for calculating remainder
, 6a, 6b, 6C and a flip-flop 7, and means for establishing cell synchronization by detecting from the output of the CRC calculation circuit 22 that the input data string is divisible by the generating polynomial. As,
It includes AND circuits 4a, 4b, and 4C, an AND circuit 5a with an inverter, an OR circuit 9, a frame counter 10, a delay circuit 13, a synchronization protection circuit 14, a differentiation circuit 15, and a control circuit 16. C when it becomes
As means for resetting the RC arithmetic circuit 22, an AND circuit 5b with an inverter, a control circuit 16, and an OR circuit 20 are provided.

The feature of this embodiment is that the cell header has a code length N (=40) and a period M (=40) of the generating polynomial.
127) A shift register 21 with an N-bit configuration is provided as a delay means that is set shorter and delays received data 1 by N bits, and the CRC calculation circuit 22 takes in the N-bit data string after being reset, and then outputs the clock 2 of received data 1. Each time, the output of the shift register 21 is input to this CRC calculation circuit 22 in a state where the internal state of the CRC calculation circuit 22 has been shifted [M−N] times without any new input, and the internal state is further shifted when a new input is received. As a means of inputting the output of the shift register 21 and new data to the CRC calculation circuit 22, just as new data is input to the CRC calculation circuit 22 after being shifted CN-1E times without
The CRC calculation circuit 22 is provided with exclusive OR circuits 6a, 6b, and 6C in addition to the basic configuration of the CRC calculation circuit.

In this embodiment, as a resetting means, when the internal state of the CRC calculation circuit 22 does not shift to the cell synchronization state even after a predetermined period of time has elapsed from the initial state where the CRC calculation circuit 22 was reset, the CRC calculation circuit 22 is reset. An OR circuit 23, an AND circuit 24, and a counter 25 are provided as resetting means for resetting the internal state.

FIG. 2 is a diagram showing the principle of the operation flow of the serial processing type CRC arithmetic circuit.

After all flip-flops of the CRC calculation circuit are reset (step a), the received data is input to the CRC calculation circuit by N bits equal to the code length (step b).
. At this time, the internal state of the CRC calculation circuit is shifted N times. The process up to this point is the same as the conventional example.

After this, the internal state of the CRC calculation circuit is shifted [M−N] times without input (step C). Next, in this internal state, 1 bit of data obtained by delaying received data 1 by N bits is input (step d). At this time, CR
The internal state of the C arithmetic circuit is shifted once. Furthermore, the internal state is shifted [N-1] times in a state where there is no input (step e), and 1 bit of new data is input in that internal state (step f). At this time, the internal state of the CRC calculation circuit is shifted one more time.

The CRC calculation circuit 22 shown in FIG. 1 does not perform the above operations by actually shifting the data, but equivalently performs the processing of steps C to f (step g) in one step.
Perform every clock.

After resetting all the flip-flops in the CRC calculation circuit, if N bits of data are input and the internal state of the CRC calculation circuit is shifted [MN] times from that state, its internal state as seen on the period of the CRC calculation circuit The state will be the same as the internal state immediately after reset. If 1-bit data obtained by delaying received data 1 by N bits is input to the internal state, the same bit will be input twice in the same internal state. As a result, the influence of the first bit input to the CRC calculation circuit after reset can be removed from the internal state of the CRC calculation circuit.

After this, the internal state is returned to the same internal state position as when N bits of data were input after reset, and 1 bit of new data is input to that internal state. As a result, the CRC calculation circuit outputs the calculation result for N bits of data from the second bit after reset to the newly input bit.

Similarly, CRC calculation results for N-bit input data whose starting point is shifted by 1 bit are obtained bit by bit.

CRC calculation circuit 22 that realizes the above operations in one clock
The configuration of is explained below. In this embodiment, the generating polynomial of the CRC calculation circuit 22 is x8+x"+x+l, which is the same as in the conventional example shown in FIG. 7, and the code length N (equal to the header length) is 40 bits. show.

When there is no input, the change in the internal state of each flip-flop 7 due to one shift is expressed by .

The transition state in which the internal state is shifted [M-N] = 87 times without any input can be obtained by finding T. 7 contents F.1
Assuming ~Foa, the contents Fil~Flat of each flip-flop 7 after shifting 87 times with no input are (hereinafter the margin of this page) F11 = F02 + FO6 + FO7 + FO8 F + 2 - FO
2+ FO3+ FO6) ``(2) becomes. Here, "+" represents an exclusive OR operation.

When data D1 delayed by N bits is input to the internal state shifted 87 times, the contents F21 to F28 of each flip-flop 7 immediately after that become Fzt=F+s F28=FIT.

Furthermore, this internal state is set to [N1)=3 when there is no input.
When new data D41 is input after shifting nine times, each flip-flop . Internal status of knob 7 F31 to F38
is 40 after reset using equations (2) and (3).
The contents of each flip-flop when bit data is input are as follows.

Equation (4) is calculated by inputting 40 bits of data after reset, adding delayed data from the next bit to the second, sixth and seventh stage flip-flops of the basic CRC calculation circuit, and adding the delayed data to the first stage flip-flops. This shows that new data can be added to the flip-flop. Such a circuit is shown as a CRC calculation circuit 22 in FIG. This CRC calculation circuit 22 has a configuration in which exclusive OR circuits 6a, 6b and 6C are added to the basic form of a CRC calculation circuit.

Next, the operation of the entire cell synchronization circuit will be explained with reference to FIG.

This operation includes the internal operation of the CRC calculation circuit 22 (step g) from input of N-bit data until the cell synchronization pattern is detected, and the operation of the OR circuit 23, AND circuit 24, and counter 25 (step g). Steps h and i) are different from the conventional example shown in FIG.

Below, we will explain the operation equivalent to the conventional example and the CR
The internal operation of the C arithmetic circuit 22 will be briefly explained, and the operations of the OR circuit 23, the AND circuit 24, and the counter 25 will be explained in detail.

The synchronization protection circuit 14 detects cell synchronization when the OR circuit 9 continuously outputs pattern mismatch (logic "1") once at the timing of the frame pulse 11. Based on this detection result, all flip-flops 7 in the CRC calculation circuit 22 are reset (step a
). Subsequently, the CRC calculation circuit 22 uses the shift register 21
With the input from the shift register 21 prohibited, N bits of received data 1 are taken in (step b), and received data 2 and the output data of the shift register 21 are taken in for each clock and CRC calculation is performed. When the output of the CRC calculation circuit 22 becomes all "0" and a cell synchronization pattern is detected, the synchronization protection circuit 14 establishes cell synchronization when it detects pattern matching J times in succession at the timing of the frame pulse 11. state. In this state, input from the output of the shift register 21 to the CRC calculation circuit 22 is prohibited, and immediately before the first data of the data string with the correct code length is input to the CRC calculation circuit 22, the All flip-flops 7 are reset.

When the counter 25 is out of synchronization, the differentiating circuit 15
It is reset by the trigger pulse of , and thereafter counts 2 clocks. The counting period of this counter 25 is longer than at least the backward protection time of the J stage of the synchronization protection circuit 14, that is, the time required to return from the cell synchronization state to the cell synchronization established state, and outputs an output pulse every cycle. Occur. The output of this counter 25 is the AND circuit 2
4 and the OR circuit 23, only when the output of the synchronization protection circuit 14 is logic "1", that is, in an out-of-synchronization state,
It is input to the control circuit 16 as a trigger pulse.

In this manner, the function of the counter 25 allows the CRC calculation circuit 22 to be set to the initial state again even if a bit error occurs in the CRC calculation circuit 22 or the shift register 21 due to noise or the like during an out-of-synchronization state. Therefore, the cell synchronization circuit can always return to the cell synchronization established state.

FIG. 4 is a block diagram of a cell synchronization circuit according to a second embodiment of the present invention.

In this embodiment, the received data 26 is input as 8-bit parallel data, and the clock of this parallel data is input as the clock 27. Correspondingly, a parallel processing type CRC calculation circuit 31 is provided as a CRC calculation circuit. Further, a parallel 40-bit delay circuit 28 is provided as a delay means, and an AND circuit 29 is provided in place of the AND circuit 4a.
, 32.

FIG. 5 shows the principle of the operation flow of the parallel processing type CRC arithmetic circuit.

After all the flip-flops of the CRC calculation circuit are reset (step a), 8 parallel data is input to the CRC calculation circuit N/L times by L=8 bits (step b). At this time, the CRC calculation circuit has N equal to the code length.
Bit data is input and its internal state is shifted N times. Subsequently, for each clock of input data, the internal state of the CRC calculation circuit is shifted CM-N times with no input (step C). Next, data obtained by delaying received data 1 by N/L clocks is input into the internal state (step d). At this time, the internal state of the CRC calculation circuit is shifted L times. Furthermore, its internal state is shifted (NL) times in the absence of input (step e),
In this internal state, new parallel data is input by L bits (for one crotter) (step f). At this time, the internal state of the CRC calculation circuit is further shifted L times. In the case of this embodiment as well, data is not actually shifted, but equivalently shifted. Therefore, the processing of step f to step f (step g) consists of one clock of parallel data (clock 27
) is carried out every time.

After resetting all the flip-flops in the CRC calculation circuit, input N-bit data and shift the internal state of the CRC calculation circuit by CM-N from that state. The state will be the same as the internal state immediately after reset. If L-bit parallel data obtained by delaying the input data by N/L clocks is input into the internal state, the same L-bit will be input twice in the same internal state. As a result, the influence of the L bit first input to the CRC calculation circuit after reset can be removed from the internal state of the CRC calculation circuit.

Thereafter, the internal state is returned to the same internal state position as when N bits of data were input after reset, and new L bits of parallel data are input to the internal state. As a result, the output of the CRC calculation circuit is N
An operation result for bit data is obtained.

Similarly, CRC calculation results for N-bit input data whose starting point is shifted by L bits are obtained for each clock.

The design of the CRC calculation circuit 31 for realizing the above operation will be explained. In this embodiment, the CRC calculation circuit 31
The generating polynomial of x' is the same as in the conventional example shown in FIG.
+x2+x+l, and the code length N (equal to the length of the header) is 40 bits. It is also assumed that the received data 26 input to the cell synchronization circuit has the same data phase for every 8 bits. Therefore, the CRC
It is assumed that bits are also included in one parallel data.

First, a basic form of an 8-parallel processing type CRC calculation circuit is found. Regarding the circuit configuration for performing CRC calculation by parallel processing, refer to Parallel Scrambling Techniques.
Four Digital Multiplexers J, AT&T
Technical Journal Volume 65, September 10, 1986
Moon (“Parallel scramble1+ng
techniques for digital
l multiplexers, AT&Tte
chnical journal, sep, /act
, 1986. It can be obtained in the same manner as the parallelization method of a self-synchronous scrambler shown in Vol. 65).

According to this document, the circuit configuration when the number of parallel processing is 8 is 7,II from the matrix Ts given by equation (5).
It can be obtained by finding t. T. ．． 8 is shown in equation (6).

The lower right part of the matrix divided into four parts in equation (5) is the C R. The state of each flip-flop in the C arithmetic circuit at the next clock is shown. For example, matrix T. The ninth line of FIG. 2 shows that the next state of the first flip-flop is the exclusive OR of the input data and the contents of the eighth flip-flop.

Also, if input data is represented by D1 to D8, the eighth column is D1
, the seventh column shows D2, and the first column shows D8.

Therefore, if the contents of each flip-flop in the current state are respectively Fl,T''FB,T, then the contents of each flip-flop in the next state are Fl.T.

~F8,T. 1, from equation (6), F1, A-+=F+, r+Ft, r+Fs, A+D8F
2. T. ,=F',,E+F2,T+F7. T+D7(
7) It becomes. Equation (7) is expressed by the CRC calculation circuit 3 shown in FIG.
This corresponds to the 8-parallel CRC basic calculation unit 30 in 1.

By using equations (7), (1), and (2), the calculation formula for performing the process of step g shown in FIG.
It can be determined in the same manner as in the first embodiment. The calculation formula calculates the internal state of each flip-flop from FOI to F when 40 bits of data is input after reset.
'os, the data obtained by delaying the parallel received data by 5 clocks are D1 to D8, the newly input parallel received data is D41 to D48, and the next internal state of each flip-flop is F II to F+8. , FI4 F[+2+ FO3+ FO4+ FO8(8).

The calculation of equation (8) is the addition of the calculations of D1 to D8 to the calculation of equation (7). Therefore, the circuit that realizes equation (8) is the CRC calculation circuit 31 shown in FIG.

〔Effect of the invention〕

As explained above, the cell synchronization circuit of the present invention is provided with a delay means that delays input data by the code length (N bits), and when the period of the CRC calculation circuit is M, each flip-flop of the CRC calculation circuit is After resetting, the input data is input to the CRC calculation circuit for the code length (N bits), and thereafter, for each bit, the internal state of the CRC calculation circuit is shifted [M-NE times] without input. This process is repeated by inputting the output of the delay means to the state, and then inputting the next bit of the input data to the state where there is no input (shifted N-IE times).

With this configuration, the relationship between the code length N and the period M of the CRC calculation circuit can be arbitrarily set within the range where [M-N] is positive or zero.

Therefore, there are no restrictions on the cell structure, and the header, CRC bit, and information string in the cell can be selected as integral multiples of 8 bits, and the receiving device including the cell synchronization circuit can be made into a byte processing type. effective.

Furthermore, since the number of CRC bits can be increased relative to the code length N, there is an effect that the bit error correction ability and the bit error detection ability in the header can be improved. At the same time, since the number of bits of the synchronization pattern for which detection is determined increases, the probability of detecting a pseudo synchronization pattern coincidence at a point that is not a normal synchronization pattern detection position is reduced.

Furthermore, in the present invention, if the cell synchronization establishment state is not reached even after a certain period of time has elapsed from the initial state in which each flip-flop in the CRC calculation circuit was reset, each flip-flop in the CRC calculation circuit can be reset again. Even if a bit error occurs due to noise or other factors in the CRC calculation circuit or delay means when the error occurs,
This has the effect of allowing the cell synchronization circuit to operate normally.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a cell synchronization circuit according to a first embodiment of the present invention. FIG. 2 is a diagram showing the principle of the operation flow of the CRC calculation circuit. FIG. 3 is a diagram showing the overall operation flow of the cell synchronization circuit. FIG. 4 is a block diagram of a cell synchronization circuit according to a second embodiment of the present invention. FIG. 5 is a diagram showing the principle of the operation flow of the CRC calculation circuit. FIG. 6 is a diagram showing an example of a cell configuration. FIG. 7 is a block diagram of a conventional cell synchronization circuit. 3, 21-9 7 register, 4a, 4b, 4c,
24, 29, 32...AND circuit, 5a, 5b...
・AND circuit with inverter, 6, 5a, 5b,
6C... Exclusive OR circuit, 7... Flip-flop, 8, 22, 31-... CRC calculation circuit, 9, 20,
23...OR circuit, 10...frame counter,
13...Delay circuit, 14...Synchronization protection circuit, 15.
... Differentiation circuit, 16 ... Control circuit, 25 ... Counter, 28 ... Delay circuit, 30 ... 8 parallel CRC basic operation section.

Claims (1)

[Scope of Claims] 1. A cell in which a header including a CRC bit is added to a digital information string is input, and a remainder obtained by a generating polynomial equivalent to that used to obtain the CRC bit for the data string constituting this cell. a CRC arithmetic circuit for determining the CRC arithmetic circuit; a means for establishing cell synchronization by detecting from the output of the CRC arithmetic circuit that the input data string is divisible by the generating polynomial; and a means for establishing cell synchronization when the cell synchronization is out of state In the cell synchronization circuit, the header has a code length N set to be shorter than the period M of the generator polynomial, and a delay means for delaying the input data string by N bits;
After the RC arithmetic circuit takes in an N-bit data string after being reset, for each clock of the data string, the delay means shifts the internal state of the CRC arithmetic circuit shifted [MN] times without any new input. The output of the delay means is input to the CRC calculation circuit, and new data is input to the CRC calculation circuit with its internal state shifted [N-1] times without any new input. and means for inputting the new data to the CRC calculation circuit. 2. The resetting means resets the internal state of the CRC arithmetic circuit again if the internal state of the CRC arithmetic circuit does not shift to the cell synchronization state even after a predetermined time has elapsed from the reset initial state. 2. The cell synchronization circuit according to claim 1, further comprising resetting means.