JPH05207003A - Frame synchronizing signal detection circuit - Google Patents

Abstract

PURPOSE:To provide a detection circuit capable of detecting a frame synchronizing signal and a subframe synchronizing signal in parallel with the input of a data signal. CONSTITUTION:The frame synchronizing signal is detected by generating a first signal to take logical '1' only during a period corresponding to the length of a corresponding signal, and generating the logical product of the data signal and the first signal. The subframe synchronizing signal is detected by generating a pulse train whose repeating period is a subframe period to make an isolated pulse signal to be generated at the time of no bit error in a starting subframe a leading pulse, and generating a window pulse by removing the isolated pulse signal from this pulse train, and extracting the subframe synchronizing signal from the data signal by making this window pulse a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to frame synchronous data communication, and more particularly to a synchronous signal error detection circuit.

[0002]

2. Description of the Related Art In frame synchronous data communication, one frame is composed of a plurality of subframes, and a frame synchronous signal indicating the start of one frame of a data signal has a specific pattern in the starting subframe (first subframe). Represented by setting the code. A sub-frame synchronization signal of a predetermined logic level is set to a specific bit of each sub-frame, for example, the k-th bit in order to delimit a part of the frame other than the first sub-frame. The kth bit is usually the first bit.

FIG. 9 shows a frame format of a data signal S3 in a frame synchronous data communication, an enable signal S1 and a clock pulse signal S2. In the figure, one frame consists of a plurality of subframes, each subframe is 8 bits, and each bit is transmitted in synchronization with the clock pulse signal S2. In the following description, each 8-bit subframe is described as an octet. The enable signal S1 has a logic 1 value only during the period in which the data signal is transmitted. The frame sync signal is represented by setting eight "0" s in the start octet. No subframe sync signal or octet sync signal is set in the frame format shown in FIG.

FIG. 10 shows another example of the frame format. The same frame sync signal of logic 0 as in FIG. 9 is set in the first octet, and further the octet sync signal is set. The octet sync signal is assigned to the first bit of each octet and is set to logic one.

FIG. 11 shows a data communication system in which a frame sync signal detection circuit is used. On the transmitting side, the digital data signal sent from the transmitting terminal is converted into an analog data signal by the digital-analog converter 91, and then the analog data signal is received by the receiving antenna 93 via the transmitting antenna 92, and the analog-digital signal is received. It is converted into a digital data signal by the converter 94.
The frame sync signal detection circuit 95 detects the frame sync signal from the digital data signal and determines whether the digital data signal is a transmitted data signal or a data signal representing some other information. And transmits the digital data signal to the receiving terminal. Actually, the frame synchronization signal detection circuit is also provided on the transmission side to inspect the change in the data signal caused by noise.

FIG. 12 is a block diagram of a conventional typical frame sync signal detection circuit. The circuit comprises a serial / parallel converter 10, a memory 12 and a CPU 13. The serial-parallel converter 10 is enabled by the enable signal S1 and the clock pulse signal S
The serial data signal S3 is converted into the parallel data signal S11 in synchronism with 2. The parallel data signal S11 is
It is once stored in the memory 12. After all the data signals transmitted by the data communication are accumulated in the memory 12, the CPU 13 detects the frame synchronization signal by software. If the sub-frame sync signal is set and it is necessary to detect this sub-frame sync signal, this step is performed. Less than,
The frame synchronization signal and the subframe synchronization signal are collectively referred to as a synchronization signal.

[0007]

In the conventional sync signal detection circuit described above, all the serial-to-parallel converted data signals are once stored in the memory, and then the bit assigned to the sync signal is detected. However, there is a problem that it takes a long time to detect the sync signals of all the data signals.

It is a first object of the present invention to provide a frame sync signal detection circuit capable of detecting a frame sync signal in real time in parallel with the reception of a data signal.

A second object of the present invention is to provide a subframe synchronization signal detection circuit capable of detecting the subframe synchronization signal in real time in parallel with the reception of the data signal.

[0010]

In order to achieve the above-mentioned first object, the frame sync signal detection circuit of the present invention has an error in the frame sync signal in which all bits have the same logic level code. Is configured to detect. The frame synchronization signal detection circuit outputs a first signal that takes a logical value of 1 only during a period corresponding to the length of the frame synchronization signal, a data signal transmitted by frame synchronization data communication, and a first circuit. A second circuit having a first gate circuit which inputs a signal and outputs a second signal corresponding to a logical product of the both.

A desirable mode of the first circuit is to delay the enable signal transmitted by frame synchronization data transmission by a period corresponding to the length of the frame synchronization signal and output it as a delay enable signal, and an enable signal. A second gate circuit that outputs an exclusive OR with the delay enable signal as a first signal. A desirable mode of the delay circuit has a shift register having the same number of bits as the number of bits of the frame synchronization signal, and the shift register receives the enable signal and the clock pulse signal transmitted by the frame synchronization data communication, and receives the clock pulse signal. The enable signal is shifted in synchronism with, and its serial output is output as a delay enable signal.

In order to achieve the above-mentioned second object, in the sub-frame synchronization signal detection circuit of the present invention, one frame consists of a plurality of sub-frames, each sub-frame consists of M bits, and the frame synchronization signal starts. The subframe synchronization signal is represented by all bits of the subframe, the subframe synchronization signal is represented by the kth bit of each subframe other than the start subframe, and the kth bit is set to the first logic level. Is configured to detect the error. The subframe synchronization signal detection circuit detects the start subframe, and when it detects that the frame synchronization signal represented in the subframe is error-free, the subframe synchronization signal detection circuit detects the second subframe of the second subframe following the start subframe. Generating the isolated pulse signal of the first logic level in synchronization with the kth bit, and
A start sub-frame detection circuit that delays the input data signal by M clock pulse periods and outputs the start pulse, and the start pulse is generated by delaying the isolated pulse signal by M clock pulse periods, and each subsequent pulse is the immediately preceding pulse. To generate a wind pulse that is a pulse train that is repeatedly generated by delaying the clock signal by M clock pulse periods and that is synchronized with the subframe synchronization signal of each subframe other than the second subframe among the repeatedly generated pulses. And a transmission gate for selecting the k-th bit of a subframe other than the start subframe from the data signal delayed by the start subframe detection circuit under the control of the wind pulse.

A preferred mode of the start subframe detection circuit is a first shift register having a serial input terminal, an M-bit parallel output terminal and a serial output terminal,
The first shift register has an M-input first OR gate connected to the M-bit parallel output of the first shift register, and the first shift register shifts the serially-input data signal in synchronization with the clock pulse signal. The serial output is output as the delayed data signal, and the first OR gate outputs the pulse of the first logic level as the isolated pulse signal only when the start frame has no error.

Another desirable mode of the start subframe detection circuit is a first shift register having a serial input terminal, an M-bit parallel output terminal and a serial output terminal, and an M-bit parallel output of the first shift register. A first OR gate with M inputs connected to
The first shift register has a first delay circuit, the first shift register shifts a serially input data signal in synchronization with a clock pulse signal, and outputs the serial output as a delayed data signal. Outputs the pulse signal of the first logic level only when the start frame has no error, and the first delay circuit delays the output of the first OR gate by k-1 clock pulse period. Output as an isolated pulse signal.

A preferred mode of the window pulse generating circuit has a repeating circuit and an exclusive OR gate, and the repeating circuit has a second delay circuit and a second OR gate, and the second delay circuit is The output of the second OR gate is delayed by M clock pulse periods, the second OR gate generates an OR of the isolated pulse signal and the output of the second delay circuit, and the exclusive OR gate is isolated. The pulse signal and the output of the second OR gate are input to block the output of the isolated pulse signal.

[0016]

1 is a block diagram of a first embodiment of a frame synchronization signal detection circuit of the present invention, and FIG. 2 is a block diagram of an error detection circuit 4 of FIG. FIG. 3 is a timing chart for explaining the operation of each part of the circuits of FIGS. The frame format adopted in this embodiment is the same as that described in FIG. 9, the frame sync signal is set to the start octet (first octet), and all bits are set to logic 0. The data signal of FIG. 3 contains a logic 1 error in the third bit of the frame sync signal.

The frame sync signal detecting circuit comprises a first signal generating circuit 1 and an error detecting circuit 4, and the first signal generating circuit generates a first signal S5 which will be described later. The first signal generation circuit 1 is composed of an 8-bit shift register 2 and an AND gate 3. The shift register 2 inputs the enable signal S1 to the serial input terminal, shifts the enable signal S1 by 8 bits in synchronization with the clock pulse signal S2, and generates a delay enable signal. Therefore, the delay enable signal is a signal whose phase is delayed from the enable signal by 8 clock pulse periods, that is, the length of the frame synchronization signal. The AND gate 3 inputs the enable signal and the inverted delay enable signal S4, and calculates the logical product of them with the first signal S
Output as 5. Therefore, the first signal S5 takes logical 1 only during the period corresponding to the length of the frame synchronization signal (see signal S5 in FIG. 3). When the frame sync signal contains an error, the error detection circuit 4 extracts the error from the frame sync signal. The error detection circuit 4 is an AND gate 5
And a register circuit 6. The AND gate 5 receives the first signal S5 and the data signal S3, and outputs the logical product as the second signal S6. Thereby, the error bit is extracted from the frame synchronization signal (signal S6 in FIG. 3).
The register circuit 6 is composed of AND gates 7 and 8 and a D flip-flop 9. The AND gate 7 inputs the clock pulse signal S2 and the first signal S5, and outputs the active clock pulse train S7 only during the period corresponding to the length of the frame synchronization signal (FIG. 3, signal S7). AND gate 8
Inputs the second signal S6 and the clock pulse train S7, and if the frame synchronization signal has an error bit, outputs one clock pulse S8 synchronized with the bit. The D flip-flop is enabled by the enable signal, the second signal S6 is input to the data input terminal, the clock pulse S8 is input to the clock input terminal, the second signal S6 is latched at the falling edge of the clock pulse S8, and the alarm signal is output. Send S9. In this way, the frame synchronization signal detection circuit can detect the error in real time in parallel with the input of the data signal when the frame synchronization signal has an error. In the present embodiment, the first signal S5 is created by the logical product of the enable signal and the inverted delay enable signal, but the same signal can be obtained by taking the exclusive OR of the enable signal and the delayed enable signal.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a block diagram of a second embodiment of the present invention, FIGS. 5, 6 and 7 are block diagrams of the start octet detection circuit, window pulse generation circuit and data conversion circuit of FIG. 4, respectively, and FIG. 8 is FIG. FIG. 8 is a timing diagram showing the operation of each part of the circuit shown in FIGS. 5, 6 and 7. This embodiment is an example of an octet sync signal detection circuit. The frame format adopted in this embodiment is the same as that shown in FIG.
It shall consist of octets.

As shown in FIG. 4, the octet sync signal detection circuit includes a start octet detection circuit 20, a window pulse generation circuit 21, and a transmission gate 2.
2, an exclusive OR gate 23, and a data conversion circuit 24. The start octet detection circuit 20 comprises an 8-bit shift register 25 and an 8-input NOR gate 26, and the parallel output of the shift register 25 is connected to the input of the NOR gate 26, as shown in FIG. The shift register 25 shifts the data signal S3 in synchronization with the clock pulse signal S2 and outputs a data signal delayed by 8 clock pulse periods from its serial output terminal. Hereinafter, this delayed data signal will be referred to as a delayed data signal S20 (see FIG. 8, signal S20). The NOR gate 26 receives an octet sync of the second octet only when it inputs a logic 0 on all its eight inputs, and thus when the start octet detection circuit 20 does not detect an error in the frame sync signal (start octet). The isolated pulse signal S21 is output in synchronization with the signal (the first bit of the second octet in this embodiment).

The window pulse generation circuit 21 generates a window pulse. The window pulse is a pulse train in which the component pulse is generated in synchronization with the octet synchronization signal (first bit) of the third octet and each octet thereafter, as represented by the signal S22 in FIG. The window pulse generating circuit 21 (see FIG. 6) comprises an 8-bit shift register 28, an OR gate 29 and an exclusive OR gate 30. The OR gate 29 generates a logical sum of the isolated pulse signal S21 and the serial output of the shift register 28, and outputs the output signal S29 from the shift register 28.
Supply to the serial input terminal of. The shift register 28 delays the signal S29 input to its serial input terminal by 8 clock pulse periods and outputs it, and inputs the delayed output (serial output) again via the OR gate 29. Therefore, the shift register 28 and the OR gate 2
Reference numeral 9 constitutes a repetitive circuit. This repetitive circuit generates a pulse train having an isolated pulse signal as a head pulse and an 8-clock pulse cycle as a repetitive cycle. This pulse train is the signal S29. Exclusive-OR gate 30 removes isolated pulse signal S21 from signal S29 and produces window pulse S22 as shown in FIG.

The transmission gate 22 (see FIG. 4) controls the delayed data signal S under the control of the window pulse S22 (using the window pulse S22 as a mask signal).
20 to thereby extract the second octet delayed by 8 clock pulse periods of the octet sync signal and the first bit of the octet thereafter. Hereinafter, the output of the transmission gate 22 will be referred to as a signal S23. The exclusive OR gate 23 is an error detection gate.
This gate receives window pulse 22 and signal 23,
Of the bits set as the octet synchronization signal, the output of the correct bit is blocked, and only the error bit S24 is output (see FIG. 8). The data conversion circuit 24 includes a serial / parallel conversion circuit 33, a D flip-flop 32, A
The ND gate 31 is provided. The serial / parallel converter 33 receives the delayed data signal S20 input serially.
Is converted into a parallel data signal S33 in synchronization with the clock pulse signal S2. The AND gate 31 inputs the error bit S24 and the clock pulse signal S2, and outputs the clock pulse S31 only when the error bit exists. The D flip-flop 32 latches the error bit S24 in synchronization with the clock pulse S31 and resets the reset signal S
32 is output. The reset signal S32 disables the serial / parallel converter 33 and generates an alarm signal.

Next, the operation of this embodiment will be described for the case where the octet synchronization signal of the 10th octet has an error (logic 0). When the start octet detection circuit 20 receives the data signal S3 and the clock pulse signal S2,
The start octet is detected, and if there is no error, the isolated pulse signal S21 is output in synchronization with the first bit of the second octet. When the window pulse generation circuit 21 receives the isolated pulse signal S21, the isolated pulse signal S21 is used as a head pulse and the pulse generation is repeated in synchronization with the first bit of each octet (signal S29). The exclusive OR gate 30 provided in the window pulse generation circuit 21 removes the isolated pulse signal S21 from the signal S29 and generates a window pulse S22. Wind pulse S22
The transmission of the delayed data signal S20 in the transmission gate 22 is controlled to extract the first bit of the second to tenth octet delayed by one octet period (eight clock pulse periods). Exclusive OR gate 23
Is the first output from the transmission gate 22
The output of the correct bit among the bits is blocked, and only the error bit is supplied to the data conversion circuit 24. If no error bit is detected, the data conversion circuit 24 converts the serially input delayed data signal S20 into a parallel data signal S33. When the error bit S24 is detected, the data conversion circuit 24 stops the serial / parallel conversion and issues an alarm signal.

In many cases, the octet sync signal is set to the first bit of each octet. However, the octet sync signal has an arbitrary bit of each octet, for example, the k-th bit.
Bits (k is greater than 1 and less than or equal to 8). In this case, N in the start octet detection circuit 20
The output of the OR gate 26 is delayed by, for example, a k-1 bit shift register by a k-1 clock pulse period, and the delayed output is used as the isolated pulse signal S21, so that the output is not changed. The object of the invention can be achieved.

[0024]

As described above, the frame sync signal detection circuit of the present invention has the following effects.

1. When the data signal is input, the frame synchronization is performed in real time in parallel with the input of the data signal by taking the logical product of the first signal that takes the logical value 1 only for the period corresponding to the length of the frame synchronization signal and the input data signal. A signal error can be detected (Claim 1).

2. Since the first signal can be generated based on the simple principle of generating the exclusive OR of the enable signal and the delay enable signal, various changes can be made as necessary. For example, by setting the delay time to be long or short, it is possible to detect the frame synchronization signal of a length corresponding to the delay time in real time (claim 2).

3. Since the delay circuit for generating the delay enable signal is composed of only one shift register, the circuit is simplified (claim 3).

The subframe synchronization signal detection circuit of the present invention has the following effects.

1. When the start sub-frame of the data signal is input, it is detected, if there is no error bit, an isolated pulse signal is generated, a window pulse is generated based on the isolated pulse signal, and the window pulse is used as a mask signal from the data signal By extracting the frame synchronization signal, the subframe synchronization signal can be detected in real time in parallel with the reception of the data signal (claim 4).

2. An isolated pulse signal which is a source of a control signal used in the present invention, by a simple circuit configuration including a shift register for shifting an input data signal in synchronization with a clock pulse signal and an OR gate for inputting a parallel output of the shift register. Can be generated simultaneously with the end of the input of the start subframe, and the immediacy of the generation of the isolated pulse signal guarantees the real-time detection operation of the subframe synchronization signal detection circuit of the present invention (claim 5).

3. By using the isolated pulse signal as the leading pulse, a pulse train having one subframe cycle as a repeating cycle is generated by the repeating circuit, and the exclusive pulse gate is used to exclude the isolated pulse signal from the pulse train. A window pulse can be generated, whereby the subframe synchronization signal can be extracted from the data signal immediately (claim 7).

4. By delaying the isolated pulse signal and generating a window pulse by the delayed isolated pulse signal, it is possible to detect the subframe synchronization signal even at an arbitrary position of each subframe (claim 6). ).

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of an error detection circuit 4 of FIG.

FIG. 3 is a timing diagram illustrating an operation of each unit of the circuits of FIGS. 1 and 2.

FIG. 4 is a block diagram of a second embodiment of the present invention.

5 is a block diagram of the start octet detection circuit 20 of FIG.

6 is a block diagram of a window pulse generation circuit 21 of FIG.

7 is a block diagram of a data conversion circuit 24 of FIG.

8 is a timing diagram showing the operation of each part of the circuit shown in FIGS. 4 to 7. FIG.

FIG. 9 is a diagram showing an example of a frame format of a data signal in frame synchronous data communication, an enable signal, and a clock pulse signal.

FIG. 10 is a diagram showing an example of a frame format in which a subframe synchronization signal is set.

FIG. 11 is a diagram showing a data communication system including a frame synchronization signal detection circuit.

FIG. 12 is a block diagram of a typical conventional example of a frame synchronization signal detection circuit.

[Explanation of symbols]

1 1st signal generation circuit 2, 25, 28 shift register 3, 5, 7, 8, 31 AND gate 4 error detection circuit 6 register circuit 20 start octet detection circuit 21 window pulse generation circuit 22 transmission gate 23, 30 exclusive logic Sum gate 24 Data conversion circuit 26, 29 OR gate 32 D flip-flop 33 Serial / parallel converter S1 enable signal S2 clock pulse signal S3 data signal S5 first signal S6 second signal S7 clock pulse train S8 clock pulse S9 alarm signal S20 delay Data signal S21 Isolated pulse signal S22 Wind pulse S24 Error bit S29 Pulse train (output of OR gate 29) S30 Parallel data signal S31 Clock pulse S32 Reset pulse

Claims (7)

[Claims] 1. A frame synchronization signal detection circuit in frame synchronization data communication for detecting a frame synchronization signal in which all bits are designated by a code having the same logical value, in a period corresponding to the length of the frame synchronization signal only. A first circuit that outputs a first signal that takes a logic 1 to the second signal; and a second signal that receives the data signal transmitted by the frame synchronization data communication and the first signal and that corresponds to the logical product of the two. Second having a first gate circuit for outputting
A circuit for detecting a frame synchronization signal. 2. A delay circuit, wherein the first circuit delays the enable signal transmitted by frame synchronization data transmission for a period corresponding to the length of the frame synchronization signal and outputs the delayed signal as a delay enable signal; and the enable signal. The frame synchronization signal detection circuit according to claim 1, further comprising: a second gate circuit that outputs an exclusive OR with the delay enable signal as a first signal. 3. The delay circuit has a shift register having the same number of bits as the number of bits of the frame synchronization signal, and the shift register receives the enable signal and the clock pulse signal transmitted by the frame synchronization data communication, and receives the clock signal. The frame synchronization signal detection circuit according to claim 2, wherein the enable signal is shifted in synchronization with a pulse signal, and its serial output is output as a delay enable signal. 4. One frame consists of a plurality of subframes, each subframe consists of M bits, a frame sync signal is represented by all bits of a start subframe, and a subframe sync signal is other than the start subframe. Represented by the kth bit of each subframe, said kth bit being set to a first logic level, for frame synchronous data communication,
In the subframe synchronization signal detection circuit, when the start subframe is detected and it is detected that there is no error in the frame synchronization signal represented in the subframe, the second subframe following the start subframe is detected. A start subframe detection circuit for generating the isolated pulse signal of the first logic level in synchronization with the kth bit and delaying the input data signal by M clock pulse periods before outputting the start pulse. The pulse signal is generated by delaying by M clock pulse periods, each pulse thereafter is repeatedly generated by delaying the immediately preceding pulse by M clock pulse periods, and the pulse among the repeatedly generated pulses is A pulse train composed of pulses that are synchronized with a subframe synchronization signal of each subframe other than two subframes. A window pulse generation circuit for generating a window pulse, and a transmission gate for selecting the k-th bit of a subframe other than the start subframe from the data signal delayed by the start subframe detection circuit under the control of the window pulse. And a subframe synchronization signal detection circuit. 5. The start subframe detection circuit is connected to a first shift register having a serial input terminal, an M-bit parallel output terminal and a serial output terminal, and an M-bit parallel output of the first shift register. M
The first shift register has an input first OR gate, shifts the serially input data signal in synchronization with the clock pulse signal, and outputs the serial output as a delayed data signal. 5. The subframe synchronization signal detection circuit according to claim 4, wherein the OR gate outputs the pulse of the first logic level as the isolated pulse signal only when the start frame has no error. 6. The start subframe detection circuit is connected to a first shift register having a serial input terminal, an M-bit parallel output terminal and a serial output terminal, and an M-bit parallel output of the first shift register. M
A first OR gate of the input and a first delay circuit,
The first shift register shifts the serially input data signal in synchronization with the clock pulse signal, and outputs the serial output as a delayed data signal, and the first OR gate has no error in the start frame. Only when
A pulse signal of a first logic level is output, and the first delay circuit delays the output of the first OR gate by k-1 clock pulse period and outputs it as an isolated pulse signal.
The subframe synchronization signal detection circuit according to claim 4. 7. The window pulse generation circuit has a repeating circuit and an exclusive OR gate, the repeating circuit has a second delay circuit and a second OR gate, and the second delay circuit has a second delay circuit. The output of the second OR gate is delayed by M clock pulse periods, the second OR gate generates the OR of the isolated pulse signal and the output of the second delay circuit, and the exclusive OR gate is 7. The subframe synchronization signal detection circuit according to claim 5, wherein the isolated pulse signal and the output of the second OR gate are input to block the output of the isolated pulse signal.