JP2692481B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit, and more particularly to a frame synchronization circuit which receives an interleaved received signal after error correction coding using a block code and establishes frame synchronization.

[0002]

2. Description of the Related Art In a digital radio communication system for performing error correction coding using a block code, an iterative process may be performed on the transmitting side in order to disperse errors when burst errors occur. When this interleaving is performed, conventionally, a specific bit for frame synchronization has been allocated so that the receiving side can establish interleaving frame synchronization.

[0003]

As described above, in the related art, since a specific bit for frame synchronization is assigned, there is a problem that the signal transmission efficiency is lowered.

An object of the present invention is to provide an interleaved signal after error correction coding using a block code,
An object of the present invention is to provide a frame synchronization circuit that can establish frame synchronization without adding a specific bit.

[0005]

A frame synchronization circuit according to the present invention has a depth N after error correction coding using a block code.
A frame synchronization circuit for receiving a reception signal subjected to interleaving (N is a natural number) and generating a timing signal synchronized with a frame, wherein the reception signal is bit by bit
The exclusive OR of N bits is calculated respectively by extracting N-bit successive-shifted N ways of the phase N of the N ways
An exclusive OR unit for outputting as a column data signal sequence, N word synchronization units for respectively transmitting the word pulse signals when word synchronization is established upon receiving each of the N data signal sequences, and the N word synchronization units. the word word pulse signal from the synchronization portion is configured by a timing signal generator for generating the timing signal.

[0006]

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. The transmitting side includes an encoding circuit 1 and an interleaving circuit 2, and the receiving side includes a frame synchronization circuit 3.
A deinterleave circuit 4 and an error correction circuit 5 are provided.

Here, the coding circuit 1 performs error correction coding on the input signal S1 into a block code. The interleave circuit 2 performs interleave conversion of depth N (N is a natural number) on the block-coded signal from the encoding circuit 1 and sends it to a wireless line via a transmitter (not shown).

The signal transmitted from the transmission side is input to the frame synchronization circuit 3 and the deinterleave circuit 4 as a reception signal S2 via a reception device (not shown).

The frame synchronization circuit 3 includes an exclusive OR unit 3
1 and N word synchronization units 41 to 4N and a timing signal generation unit 51.

The exclusive OR unit 31 takes an exclusive OR of N consecutive bits of the reception signal S2 in accordance with the timing signal Pt from the timing signal generating unit 51. Further, when the interleave frame synchronization is not established, that is, when the timing signal Pt is not supplied, there are N ways to divide consecutive N bits, and therefore, exclusive OR is taken for all the division methods to obtain N columns. Output as a data signal sequence of.

N data signal sequences are input to the word synchronization units 41 to 4N, respectively. When no error occurs on the transmission path, word synchronization is established in any one word synchronization unit. Here, when the word synchronization is established, a word pulse signal indicating the word synchronization timing is transmitted.

The timing signal generator 51 receives a word pulse signal indicating the word synchronization timing from each of the N word synchronizers 41 to 4N, detects a data signal sequence in which word synchronization is established, and interleaves on the transmitting side. The timing signal Pt is generated by detecting the delimiter of the conversion frame. The synchronization of this timing signal is based on N of the cycle of the code word.
Double.

The deinterleave circuit 4 performs an inverse conversion of the conversion in the interleave circuit 2 on the transmission side on the reception signal S2 according to the timing signal Pt from the frame synchronization circuit 3. The error correction circuit 5 corrects the distributed bit error.

By performing the interleaved conversion, when a burst error occurs due to radar interference or the like on the transmission line, the bit error is distributed to each of the N blocks, so that the overall error correction effect is increased. .

Next, the operation of the frame synchronization circuit will be described.

Since the received signal S2 is an interleave-converted signal, word synchronization cannot be established even if it is divided into blocks at any timing. However, the received signal S
If N bits of 2 consecutive exclusive ORs are taken at the correct timing with respect to 2, and the data signal string obtained by the exclusive OR is divided into blocks at the correct timing, the code word becomes a code word, so that word synchronization can be established.

In the exclusive OR unit 31, there are N timings of division for obtaining the exclusive OR of consecutive N bits, but only one is a code word. Now, the case of N = 3 will be described as an example with reference to FIG.

FIG. 2 (1) shows a data signal sequence input to the interleave circuit 2 on the transmission side, that is, a data signal sequence before being interleaved, and (2) is interleaved by the interleave circuit 2. The subsequent data signal sequence is shown. Here, n is a code length, and three bit pattern series (a ₁ , a ₂ , ..., _An ), (b ₁ ,
b ₂ , ..., B _n ) and (c ₁ , c ₂ , ..., C _n ) are code words.

Now, assuming that no error occurs on the transmission path, the method of delimiting continuous 3 bits in the exclusive OR unit 31 is 3 as shown in FIGS. 2 (3A), (3B) and (3C). There is a street. If it is correctly blocked, (3B)
Are three codewords (a ₁ , a ₂ , ..., _An ), (b ₁ ,
_{b 2, ..., b n)} , a code word since those taking the exclusive OR of each bit of the _{(c 1, c 2, ...} , c n). On the other hand, (c ₀ , c ₁ , ... C _n-1 ), (a ₂ , a ₃ ,
Since a _{n + 1} ) is not a code word, the exclusive OR of (3A) and (3C) is not always a code word.

Therefore, since the code word is output only from one column of the N columns (N = 3 in this case) of the exclusive OR unit 31, any one of the N word synchronization units 41 to 4N is output. Word synchronization is established only in the word synchronization section. By detecting the data signal sequence in which this word synchronization is established,
Finally, it is possible to generate the timing signal Pt which serves as a reference for the deinterleave conversion.

FIG. 3 is a block diagram showing a second embodiment of the present invention. The frame synchronization circuit 6 includes a 1 / N frequency divider 61.
, And N word synchronization units 71 to 7N, and a timing signal generation unit 81.

The 1 / N frequency division section 61 frequency-divides the received signal S2 into 1 / N in accordance with the timing signal Pt from the timing signal generation section 81, and outputs it as a data signal sequence of N columns. The data signal train of N columns is composed of N word synchronization units 71.
~ 7N respectively.

The timing signal generator 81 receives the word pulses P1 to PN indicating the timing of word synchronization output from the N word synchronizers 71 to 7N, respectively, and on the transmission side from the phase relationship of the N word pulse signals. Of the timing signal P by detecting the frame delimiter of the interleaved conversion of
generates t. The cycle of this timing signal is N times the synchronization of the code word.

When the 1 / N frequency divider 61 divides the frequency by 1 / N to generate N data signal sequences, if the data signal sequence is divided into blocks at the correct timing, it becomes a code word. Therefore, word synchronization is established in each of the N word synchronization units 71 to 7N.

Further, the 1 / N frequency division unit 61 is in the free-run state until the word synchronization is established and the timing signal Pt is supplied from the timing signal generation unit 81, so that the first bit of the interleaved frame is N. There are N kinds of cases in which it is not uniquely determined where to be input in the data signal row of the row. Therefore, the timing signal generation unit 81 detects the leading bit position of the interleaved frame based on the phase relationship of the word pulse signals P1 to PN output from each of the N word synchronization units 71 to 7N.

FIG. 4 shows an example of the phase relationship of each word pulse signal when the first bit of the interleaved frame is input to the word synchronization section 7i of the i-th (i is an integer, 1≤i≤N) column. FIG. As can be seen from the figure, the word pulse signal Pi in the i-th column to which the leading bit is input is output at a position which is advanced by 1 bit compared with the word pulse signal Pi-1 in the immediately preceding column (i-1) column. To be done. Therefore, since the data signal sequence in which the leading bit is input can be detected from this phase relationship, it is possible to finally generate the timing signal Pt which is the reference of the deinterleave conversion.

[0029]

As described above, the present invention utilizes the word synchronization of the error correction code to establish the interleaved frame synchronization. Therefore, the present invention is not limited to the conventional method for establishing the interleaved frame synchronization. There is an effect that it is not necessary to prepare bits and the transmission efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation of the exclusive OR unit 31 shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram for explaining the operation of the timing signal generator 81 shown in FIG.

[Explanation of symbols]

 1 Encoding circuit 2 Interleave circuit 3 and 6 Frame synchronization circuit 4 Deinterleave circuit 5 Error correction circuit 31 Exclusive OR unit 41 to 4N, 71 to 7N Word synchronization unit 51, 81 Timing signal generation unit 61 1 / N frequency division Part S1 Input signal S2 Received signal Pt Timing signal P1 to PN Word pulse signal

Claims (1)

(57) [Claims] 1. A timing signal synchronized with a frame is generated after receiving a received signal interleaved with a depth N (N is a natural number) after error correction coding using a block code.
A frame synchronizing circuit for forming, 1 from the received signal
Bit by extracting the N-bit successive-shifted N ways of phase calculates the exclusive OR of N bits each of the
An exclusive OR unit for outputting a data signal sequence of the N columns of N kinds, and the N columns of N word synchronization unit for delivering each word pulse signal when the data signal sequence to the receiving word synchronization are established in , the frame synchronization circuit comprising: a timing signal generator for generating the timing signal by a word pulse signal from the N pieces of word synchronization portion.