JPS5837742B2 - Synchronous conversion communication method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generally relates to a communication system for synchronous conversion in a wireless line with poor transmission quality.

Conventionally, when attempting to send and receive daisicle code transmission using a wireless line, synchronization methods suitable for each line (for example, wired line and wireless line) were not adopted as a system system, resulting in problems due to synchronization loss. This method has disadvantages in that code errors occur or the hardware configuration becomes complicated, making it impossible to transmit and receive optimal daisicle code transmission.

The present invention was developed in view of this problem, and it
Even when performing daisicle code transmission between a fixed station and multiple mobile stations or between mobile stations using an F radio line, if a synchronization method suitable for the interface of each line according to the present invention is adopted, it is possible to Even if an error correction method code such as this is adopted, there will be no increase or decrease in the number of codes caused by loss of synchronization, so the feature is that a stable line can always be ensured without code errors.This will be explained in detail below using the drawings. .

First, the main points of the present invention are as follows.

In other words, when transmitting and receiving digital codes using a wireless line, a start-stop synchronization method is used that allows data to be exchanged on the interface and the hardware configuration to be simple between the wired line and the sending and receiving terminal devices. Do it with
In order to improve data quality, a wireless link adds a parity code for error correction when transmitting and receiving data, and the transmitting side converts it to an independent synchronization method that is optimal for the error correction method before transmitting, and the receiving side uses an independent synchronization method. In order to convert the data received using the Asynchronous method again into the asynchronous method and output it, and to save the memory required for adjusting the Quim base, the communication transmission speed of the wireless line is increased by the amount of the parity code added. The reason is that the speed is set to be equal to the wired line speed.

Now, Figure 1 shows an example of the configuration of an HF communication network, where A is a transmitting station and B is a transmitting station.
1! B2+...Bn is a receiving station.

Further, FIG. 2 is a block diagram of an exemplary configuration of the transmitting station A, and FIG. 3 is a block diagram of an exemplary configuration of each of the receiving stations B1 to Bn.

For example, HF, which has worse transmission quality than transmitting station A in Figure 1,
Multiple receiving stations B1, B2, etc. using wireless lines
- Information shall be sent to Bn.

The transmitting station A transmits information using a transmitting device as shown in FIG. 2, where 1 is a terminal device, such as a keyboard of a printing telegraph machine or a tape league.

2 is a synchronous converter that is input to the terminal device 1 via a wired line, and the information of the start-stop serial digital code obtained from this is an error correction code (for example, a known BCH code, etc.) for improving transmission quality. is added to each word and converted into an independent synchronization method that is optimal for transmission over a wireless line.

The output of the synchronous converter 2 (described in detail later with reference to FIG. 4) is converted into a modulated signal for transmission as a wireless signal by a modulator 3.
Sent from

Next, FIG. 3 shows a receiving device installed at each receiving station B, , B2, . . . Bn.

5 in the figure is a receiving antenna and a receiver, and the received signal is sent to a demodulator 6 to be demodulated into a daily signal.

Reference numeral 7 denotes a synchronous converter, which performs error correction word by word on the independent synchronization system daisicle code inputted from the demodulator 6, converts it into an asynchronous system code, and sends it to the terminal device 8 via a wired line. give the output.

For example, a printer or a puncher of a printing telegraph is used as the receiving terminal.

Next, FIG. 4 is a diagram showing a specific circuit configuration example of the transmitting side synchronous converter 2 in FIG. 2, and the synchronous conversion operation on the transmitting side will be explained using this diagram.

Reference numeral 9 in the figure denotes an input interface section, which adjusts the interface to an input signal from the outside.The output is an asynchronous digital code, and FIG. 6 1 is an example of the code structure.

Note that FIG. 6 is a time chart of the daily code in each transmitting and receiving section.

In a start-stop synchronization system, when no signal is input, the stop polarity code is usually continuous, and when words are input continuously, the stop code is usually n times the other bits (n is, for example, 1.5). ).

In the example in Figure 6, each word is ■,, ■2, ■3,..., and each piece of information is made up of 5 pits in one word, with start and stop bits before and after each word. Since data is added, one word consists of 7 bits as shown in the figure.

Note that the start and stop bits have opposite characteristics.

FIG. 6 2 shows enlarged portions 1 and 2 of 1 to aid understanding.

10 in Fig. 4 is a start signal detector, and the input signal changes from stop polarity to start polarity, approximately % of 1 bit length.
If it is determined that the width is continuous and that the polarity is the start polarity, it is determined that the polarity is the start polarity, the gate control circuit 11 is operated, and the input signal passes through the gate control circuit.

That is, as shown in Fig. 6 3, between A, ~B, and A2~B.
The two-way gate control circuit 11 is opened, and the signal passes through this gate and is input to the serial/parallel conversion circuit 12.

Also, when the gate control circuit 11 is opened, the oscillator 1
The gate control circuit 14 for controlling the timing clock from No. 3 is also activated by the start signal shown in FIG. 6, 1.2.
When the gate 14 is opened between A and B1 and between A2 and B2 in FIG. This clock inputs 5-bit information to the serial/parallel conversion circuit 12.

This 5-bit signal is inputted in parallel to the error correction code adding section 16, where, as shown in FIG.
... etc. are added.

Furthermore, start and stop codes are added before and after this one frame, and all words are made into words of equal length bits in order to be transmitted over a wireless line using an independent synchronization method that is optimal for error correction.

Moreover, in order to reduce the memory for time base adjustment between the transmitting and receiving stations and to not reduce the effective transmission speed,
The timing is controlled so that the code lengths of I2 and I2,000P2+ are equal.

That is, since the transmission speed of the radio line is increased by the amount of the parity pit increase and the transmission is performed, the bit error rate on the receiving side is reduced accordingly, but the transmission quality is further improved by the synchronization method and the error correction method.

Now, the output of the error correction code adding section 16 is input to a time interleaving section 17, where a known interleaving is performed.

That is, in order to prevent burst errors (continuous errors) that occur particularly in HF lines, bits are temporally dispersed and transmitted for each frame.

I'l +P'11 1 I'2''P'2 in Fig. 6 6
1 indicates each interleaved word.

Reference numeral 19 in FIG. 4 is a timing sending section, which outputs the clock from the oscillator 13 at equal intervals for each bit as shown in FIG. Send to Department 3.

The above is a description of the transmitter circuit for converting the start-stop synchronization signal into an independent synchronization system optimal for error correction and transmitting it.

Note that a synchronization code, such as a known M-sequence code, for notifying the receiving side of the error correction start position can be controlled by the control unit 20 in FIG. The signal activates the synchronization signal generating section 21 and causes the data output section 18 to send out the synchronization code that is its output.

An example of this synchronization code is shown at 801 in FIG.

Next, the synchronous converter 7 after the demodulator 6 shown in FIG. 3 on the receiving station side will be explained.

FIG. 5 is a diagram showing a specific circuit configuration example of the synchronous converter 7.

Reference numeral 22 in the figure is a synchronization signal detection section, which is always input one bit at a time and is predefined along with the previously input (ml) bits (assuming that the synchronization code is composed of m bits). Check and compare each pit with the m-bit synchronization code that exists, and if a certain number of bits or more match, use this as the synchronization code, and after performing dink leave for each frame in the circuits of 8.9 and 10. Error correction will be explained later.

S in FIG. 6 indicates the position where the synchronization was determined by the above method.

The reception synchronization method uses an independent synchronization reception method, and the bit synchronization and frame synchronization between the transmitting side and the radio line are adjusted as follows.

The Daisicle code after demodulation and detection is differentiated by the conversion point output unit 26, and the conversion points, that is, the points where the Daisicle code goes from O to 1 and from 1 to O, are extracted and sent to the next stage phase lead detection unit 2.
7 and a phase lag detection section 28 detect whether the phase is ahead or behind the reference clock from the reference signal generator 30.

FIG. 7 is an example of a time chart of the received signal, where 1 is the received incoming signal and 2 is the conversion point output differentiated by the conversion point output section 26.

The pulse outputs from both phase detectors 27 and 28 are sent to a frequency divider 29, which divides the output of the reference signal generator 30 and controls the phase of the clock signal to the clock generator 33 which uses it as a clock. do.

As a result, the clock generator 33 outputs a sample pulse SAI that samples the received digital signal bit by bit with the correct phase from the demodulator 6, and the number of pits per frame (including ST/SP signals in the example shown in FIG. 6). The set pulse SE1 is output every time (one frame has 11 bits).

In this way, the sample pulse SA1 is synchronized with the transmitting side.
As explained above, the data is taken into the synchronization detection unit 1 bit by bit to match the frame at the error correction start position, and the set pulse SE1 is output every time 11 sample pulses SA1 are output, and the deinterleaving unit 2
3, the data input from the demodulator 6 is restored to the same code arrangement as that on the transmitting side by a known deinterleaving method as shown in FIG.
send to.

The error correction unit 24 performs error correction of information from the information and parity code for each frame of the input signal.

The code after error correction is output from the data output section 25 to the terminal device 8 as an asynchronous signal as shown in FIG.

The output of the reference signal generator 30 is also input to the frequency divider 31, and the output frequency-divided by Sample pulse SA2 and set pulse SE2 are outputted and sent to the terminal device so that the frame length is equal to the length of one frame of the wireless line, ie, the length of I'l+P'll in FIG. 6.

In other words, if the stop bit of the synchronization code of the asynchronous system is set to 1.5 times that of other bit codes as in this example, the period t2 of the sample pulse SA2 other than the stop code is equal to that of the sample pulse of the independent synchronization system of the wireless line. The relationship between period t and t2 = 1 1/7.5 X t is established.
1, and only when the stop pulse is output, and the start-stop synchronization set pulse SE2 has the same cycle as the independent synchronization set pulse S-E1, but in this cycle, the error correction unit 24 in FIG. 5 outputs one word at a time. Every time the error correction operation is completed, data is outputted to the data output section 25 in an asynchronous code arrangement.

Data synchronously converted on the receiving side in this way can be output to a terminal device, wired line, etc.

As described above, according to the present invention, a stable line with few code errors can be obtained using relatively simple hardware, which has a significant practical effect.

[Brief explanation of the drawing]

Figure 1 is an example of the configuration of a shortwave communication network, Figure 2 is an example of the configuration of transmitting side equipment, Figure 3 is an example of the configuration of receiving side equipment, and Figure 4 is an example of the configuration of the synchronous converter in Figure 2. Figure 5 is an example of the circuit configuration of the synchronous converter in Figure 3, Figure 6 is a time chart of the transmitting and receiving digital signals, and Figure 7 is a time chart of the received signal. be. 1, 8...terminal device, 2.7...synchronous converter, 3...modulator, 4...transmitter and antenna, 5... ...Antenna and receiver, 6...
... Demodulator, 9 ... Input interface section, 10 ... Start signal detection section, 11 ...
... Gate control circuit, 12 ... Serial-to-parallel converter, 13 ... Clock oscillator, 14 ...
Gate control circuit, 15...timing output section,
16...Error correction code addition section, 17...
・Time interleap section, 18... Data output section, 19... Timing sending section, 20...
...control section, 21... synchronization signal generation section, 22
... Synchronization signal detection section, 23 ... Deinterleave section, 24 ... Error correction section, 25 ...
...Data output section, 26...Conversion point output section, 27.28...Phase lead and delay detection sections,
29.31... Frequency divider, 30... Reference signal generator, 32, 33... Clock section.

Claims (1)

[Claims] 1 When transmitting and receiving data using the start-stop synchronization method, the transmitting station and the receiving station in the transmitting and receiving terminal equipment are connected via a wireless line to transmit and receive daisycle codes. A parity code is added to each word, and a synchronization code is added at the start of data transmission to convert it to an independent synchronization method, and the signal transmission speed is increased by the increase in parity bits to increase the transmission time between the input start-stop signal and the transmission word. A synchronous conversion communication system characterized by transmitting data so that the data is the same, and on the receiving side, data received using an independent synchronization method is subjected to error correction using a parity code, and then converted back to the start-stop synchronization method.