JPH02206241A - Frame synchronizing system - Google Patents

Abstract

PURPOSE:To synchronize a local frame in a short time by using consecutive r-bit of the same level as a frame synchronous bit of a received code string and synchronizing the local frame with a signal resulting from ANDing the received code string and a code string shifted by one bit each. CONSTITUTION:A frame synchronous bit of a received code string includes 2 consecutive integral r-bit of the same level or over. N stage (N is positive integer below r-1) of circuits each comprising a branch circuit 4 branching the input code string into two and an AND circuit 8 obtaining AND between a ranched code string and a code string via a delay circuit 5 retarding the code string by one bit is connected are connected in cascade. Then a local frame generating circuit 2 generates a local frame synchronously with a clock signal supplied from 1 clock input terminal 11 via an AND circuit 3. A collation circuit 1 collates a code string from the AND circuit 8 with the local frame, stops an output of the AND circuit 3 by one clock when the frame synchronization bit is dissident and shifts the local frame by one bit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is used in digital communications. In particular, the present invention relates to the generation of a local frame as a timing signal for processing a received code string, and a frame synchronization method for synchronizing this local frame with the received code string.

〔overview〕

In a frame synchronization method that synchronizes a local frame with a received signal string, the present invention uses consecutive r bits of the same polarity as the frame synchronization bits of a received code string, and synchronizes this received code string with a code string that is shifted by 1 bit. The local frame can be synchronized in a short time by synchronizing the local frame with the ANDed signal.

[Conventional technology]

FIG. 4 shows a block diagram of a conventional frame synchronization circuit. Further, FIG. 5(a) shows the 7-frame structure of the received code string, and FIG. 5(a) shows the frame structure of the local frame.

A received code string to be supplied to a subsequent circuit is branched and inputted to a code string input terminal 10, and this code string is supplied to a frame synchronization bit matching circuit 1. A clock signal bit-synchronized with the received code string is input to the clock input terminal 11, and this clock signal is supplied to the local frame generation circuit 2 via the AND circuit 3.

The local frame generation circuit 2 outputs to the frame output terminal 12 a local frame with a frame same Xl as the received code string, and also supplies the same signal to the frame synchronization bit matching circuit 1. The frame synchronization bit matching circuit 1 matches the local frame and the received code string, and if the frame synchronization bits do not match, the output of the AND circuit 3 is stopped for one clock, and the local frame is shifted by one bit.

By repeating this 1-bit shift, the local frame can be synchronized with the received code string. This local frame is used as a timing signal for processing the received code string in a subsequent circuit. Such a frame synchronization method is called a 1-bit shift method.

Here, the synchronization recovery time in the 1-bit shift method is calculated. In this calculation, the frame length is N, as shown in FIG. r bits (in the example in Figure 5, r=
It is assumed that the frame synchronization bits F1 to F4 in 4) are distributed at equal intervals. Also, in this calculation, assuming that the local frame is shifted from the synchronization position, the average time ΔT required for a 1-bit shift is determined.

If the probability that the bit of interest in the code string coincides with the frame synchronization bit by chance despite being shifted from the synchronization position is p, then the probability that a 1-bit shift will occur in the first match is 1-p. Given. The probability that a match occurs in the first match and a 1-bit shift occurs in the second match is p(
1-p). Similarly, the probability that a 1-bit shift occurs for the first time in the (n+1) matching is given by p'' (1-p). If the bit rate of the code string is fh C bits/sec, then the time required for a 1-bit shift is: The time r is τ+=1/fh
C seconds] (1). Also, the time τ2 for which the local frame remains in the same position once is the time interval between the frame synchronization bits, so after the local frame remains in the same position n times,
The time required for a 1-bit shift to occur in the second verification is nτ2+τ1. Therefore, the average time (expected value) ΔTr required for a 1-bit shift is ΔTt"Σp' (1-p) (i τ2 + τ1)++0 = (1-p) τ2 nip" + (1-p) τl Σpi . Here, since , we have .

becomes.

Substituting equations (1) and (2) into equation (3), we get:
(4) It becomes.

N in the worst case. - Since the synchronization position cannot be reached without one shift, the average synchronization return time T in this case is ・ ・ (5). Since the mark rate of the code string is usually 172, p can be set to 1/2 in equation (5), so the following equation is obtained.

[Problem that the invention seeks to solve]

However, in the conventional frame synchronization method, the mark rate is 1/2.
Since the frame synchronization bit is identified from the code string, the time spent in an asynchronous position is long, which has the drawback of increasing the time required to return to synchronization.

An object of the present invention is to solve the above problems and provide a frame synchronization method that can synchronize a local frame with a received code string in a short time.

[Means for solving problems]

In the frame synchronization method of the present invention, the frame synchronization bits of the received code string include successive integer r bits of 2 or more with the same polarity, and the input circuit of the frame phase adjustment means synchronizes the frame phase of the local frame with the received code string. A branch circuit that branches an input code string into two, a delay circuit that delays one code string branched by this branch circuit by 1 bit, and a delay circuit that branches the other code string branched by this branch circuit and the delay circuit. The present invention is characterized in that circuits including an AND circuit that calculates an AND with a passed code string are connected in cascade over N stages of positive integers equal to or less than r-1.

[For production]

If r consecutive bits of the same polarity are used as frame synchronization bits, and this code string is ANDed with a code string obtained by shifting this code string by 1 bit, the mark rate of the frame synchronization bits does not decrease, but The mark rate in other parts decreases. Therefore, the probability that a portion other than the frame synchronization bit coincidentally matches the frame synchronization bit of the local frame is reduced, and the time spent at an asynchronous position can be shortened.

〔Example〕

FIG. 1 shows a block diagram of a frame synchronization circuit according to an embodiment of the present invention, and FIG. 2 shows a frame structure of a received code string.

The circuit shown in FIG. 1 includes a code string input terminal 10 to which a received code string into which frame synchronization bits are inserted periodically
and a local frame generation circuit 2 that generates a local frame with a period equal to the frame period of the received code string inputted to the code string input terminal 10, and a local frame generation circuit 2 that generates a local frame with a cycle equal to the frame period of the received code string input to the code string input terminal 10, and a frame synchronization bit of the local frame and a frame synchronization bit of the received code string. A frame synchronization bit matching circuit 1 and an AND circuit 3 are provided as frame phase adjustment means for adjusting the frame phase of the local frame so that the local frames are synchronized with each other.

Furthermore, this circuit includes a clock input terminal 11 to which a clock signal bit-synchronized with the received signal train is input.

Here, the feature of this embodiment is that the frame synchronization bits of the received code string) are consecutive integers of 2 or more (
In this example, r = 4) bits of the same polarity are included, and between the code string input terminal 10 and the frame synchronization bit matching circuit 1, there is a branching circuit 4 that branches the input code string into two, and this branching circuit 4 A circuit including a delay circuit 5 that delays one of the branched code strings by 1 bit, and an AND circuit 6 that calculates the logical product of the other branched code string and the code string that has passed through the delay circuit 5 is r. This is because they are inserted in series over N stages of positive integers less than or equal to -1.

The local frame generation circuit 2 has a clock input terminal 11
A local frame is generated in synchronization with a clock signal supplied from the AND circuit 3. The frame synchronization bit matching circuit 1 matches the code string inputted via the AND circuit 6 with the local frame, and if the frame synchronization bits do not match, stops the output of the AND circuit 3 for one clock. , shifts the local frame by 1 bit.

FIG. 3 is a time chart showing the operations of the branch circuit 4, the delay circuit 5, and the AND circuit 6;
The code string branched by, et al) is the output of the delay circuit 5, (
C) shows the output of the AND circuit 6, respectively.

Here, the case of positive logic will be explained. In this case, all r frame synchronization bits placed at the beginning of the frame are set to "1".

The first-stage branch circuit 4, delay circuit 5, and AND circuit 6 obtain a code string containing r-1 consecutive "1"s and having the same period as the frame of the received code string. Assuming that the information bits of the received code string are random strings with a mark rate of 1/2, the mark rate of the logical product for parts other than the frame synchronization bits is 1/4. Repeat this process N times (N≦
r-1) When repeated, one frame contains r-N consecutive "1"s, and the mark rate of the other parts is 1/2"
A code string such that is obtained is obtained. These rN consecutive "1"s are regarded as a frame synchronization bit, and the local frame is synchronized with this bit. This allows the local frame to be synchronized with the received code string. This is because the phases of the two code strings match if the delay of the AND circuit 6 is ignored.

The average synchronization recovery time when frame synchronization is achieved using the code string obtained by the above signal processing is calculated. Here, for simplicity, the case where N=r-1 will be explained.

In this case, it is sufficient to set p=1/2 and r=1 for 2 in equation (5). That is,
... ・ (7) becomes.

Next, when comparing the synchronization return time T of the conventional method and the synchronization return time Tf' of the present method, Tt' 1+NO/
(2'''-t)Tr 1+No /r is obtained.

For example, frame length N. = 1000 bits, frame synchronization bit r = 4 bits, then T,' 1
+1000/(256-1)T, 1
+1000/4#0.02, which greatly reduces synchronization recovery time.

In the above embodiments, the case of positive logic has been described, but the present invention can be similarly implemented in the case of negative logic.

〔Effect of the invention〕

As explained above, the frame synchronization method of the present invention uses a frame structure in which frame synchronization bits of the same polarity are arranged in a concentrated manner, and the frame synchronization circuit changes the mark rate of parts other than the frame synchronization bits to determine the synchronization position. Detect. This has the effect of significantly shortening the synchronization recovery time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a frame synchronization circuit according to an embodiment of the present invention. FIG. 2 is a diagram showing the frame structure of a received code string. FIG. 3 is a time chart showing the operations of the branch circuit, delay circuit, and AND circuit. FIG. 4 is a block diagram of a conventional frame synchronization circuit. FIG. 5 is a diagram showing the frame structures of a received code string and a local frame. DESCRIPTION OF SYMBOLS 1... Frame synchronization bit verification circuit, 2... Local frame generation circuit, 3.6... AND circuit, 4...
- Branch circuit, 5... Delay circuit, 10... Code string input terminal, 11... Clock input terminal, 12... Frame output terminal.

Claims (1)

[Claims] 1. A code string input terminal into which a received code string into which frame synchronization bits are periodically inserted is input, and a code string input terminal with a period equal to the frame period of the received code string input to this code string input terminal. A local frame generation circuit that generates a local frame; and a frame phase adjustment means that adjusts the frame phase of the local frame so that the frame synchronization bit of the local frame and the frame synchronization bit of the received code string are synchronized. In the frame synchronization method, the frame synchronization bits of the received code string include bits of the same polarity in consecutive integers of 2 or more, and the input code string is connected between the code string input terminal and the frame phase adjustment means. A branch circuit that branches into two, a delay circuit that delays one code string branched by this branch circuit by one bit, and calculates the AND of the other branched code string and the code string that has passed through the delay circuit. A circuit including an AND circuit with r-
A frame synchronization method characterized in that frames are inserted in series over N stages, a positive integer equal to or less than 1.