JPS62105549A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To perform synchronization by providing a circuit which generates pulses with width prime to a frame period at optional intervals and an AND gate which inhibits the pulses with the output of a synchronism decision circuit, and stopping the timing generation of a frame period temporarily with the output of the AND gate. CONSTITUTION:Pulses with the width T1 prime to the frame period (11 bits) are generated repeatedly with optional width T2 (generation interval) by using repetitive pulses (g) generated by a circuit 7. When a signal (e) except synchronism is '1', a pulse (g) is inputted as an operation stop signal (f) and a circuit 1 stops timing generation operation for a time T1. Therefore, frame synchronizing pulses (b) and a received code sequence (a) vary by the width T1 and at the time of a 11-bit frame period, frame period pulses (b) are put in correct phase by up to 11-time repetition.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization circuit, which is a key technology in digital code transmission.

[Conventional technology]

In digital code transmission, it is generally necessary to include the phase of the timing generation circuit on the transmitting side and the timing circuit on the receiving side, that is, to synchronize the sound, and the regularity of the frame period is required in the tth code string. The frame-sharing method, which transmits data in a single frame, is widely used.

Hereinafter, a specific example will be explained based on a coding system called 10BIC.

A 10BIc code has an 11-bit full frame period and 1
It is a code with an unusual regularity in which adjacent codes are always reversed for each bit.

Conventionally, as a circuit that generates synchronous sound based on this complex code,
A circuit called the 1-bit immediate shift method shown in the third factor,
There is a circuit called the delay concentration shift method shown in FIG.

In FIG. 3, 1 is a timing generation circuit that generates the timing of a functional frame period that temporarily stops operation in response to an external signal, and 2 is a timing generation circuit that generates frames from a received code string based on the signal of this timing generation circuit 1. The pattern detection circuit 3 that detects the regularity of the period is in a synchronized state based on the output of the pattern detection circuit 2. ! - Determined by the synchronization judgment circuit.

The pattern detection circuit 2 includes cascade-connected D
Flip-flop 2-1, 2-2, the Q output of this D flip-flop 2-1, and the D flip-flop 2-2
Excl-7 Poor Gate 2- which uses Q output as human power
3, and the output money input of this exclusive or gate 2-3 is the I/harter 2-4. This inverter 2
-4 and the output of the timing generation circuit 1 as inputs, the AND gate 2-5 is constructed. Reference numeral 4 designates an AND gate which receives all the outputs of the AND gates 2-5 and the output of the synchronization determination circuit 3, and the output of this AND gate 14 is supplied to the timing generation circuit 1.

In FIG. 4, the same parts as in FIG. 3 are given the same reference numerals, and their explanation will be omitted. In this FIG. 4, 5 is an exclusive OR gate 2-3 in the pattern detection circuit 2.
6 is an AND gate 4 connected to the output side of the LC delay circuit.
The Q output of this SR flip-flop 6 is configured to be supplied to the timing generation circuit 1.

The operation of the circuit constructed in this manner and shown in FIGS. 3 and 4 will be explained.

1. The inversion detection signal C becomes "1" when the adjacent 9 codes of the damaged code string a are inverted, and if it is not inverted at the position indicated by the frame period pulse b, it indicates a synchronization pattern error ( ! No. d is output.

Then, the synchronization determination circuit 3 outputs an out-of-synchronization signal et- based on the synchronization pattern error signal d. Further, by setting the operation stop signal fffir IJ, the operation of the timing generation circuit 1 can be stopped and the phases of the received code sequence a and the frame period pulse b can be changed. Up to this point, the operations of the circuits in FIGS. 3 and 4 are the same.

Next, in the case of the circuit shown in FIG. 3, the out-of-synchronization signal e
When is "l", AND gate 4 opens, and at this time, the synchronization pattern! When the IA signal d becomes "1", the timing generation circuit 1 stops operating.

In addition, in the case of the circuit shown in FIG. 4, when the out-of-synchronization signal e is "l", the AND gate 4 opens, and when the synchronization pattern error signal d becomes rlJ, the SR flip-flop 6 is set and the timing When the generation circuit 1μ operation is stopped and the inversion detection signal C becomes rlJ, the SR flip-frog 6
is reset and the timing generation circuit 1 resumes full operation.

[Problem that the invention seeks to solve]

The conventional frame synchronization method described above has the following drawbacks. In other words, there are two main problems with the circuit shown in FIG. 3 and FIG. 4.

First, there is a problem regarding the operation stop signal f.

1. In the case of the circuit shown in Fig. 3, from the frame period nox b, the AND gate 2-5-synchronization pattern error 9 signal d
- AND gate 4 - The delay up to the operation stop signal f needs to be smaller than one bit period, and if the code transmission speed is high, it is difficult to realize the circuit. Next, the circuit shown in FIG.
d gate 2-5 - synchronization pattern error 9 signal d - set signal of SR7 flip-flop 6 in the path of AND gate 4;
It is necessary to make the delay of the reset signal of the SR flip-flop 6 on the path between the inversion detection signal C and the delay circuit 5 the same.
Furthermore, if the transmission speed is high, it is difficult to implement the circuit. Further, this delay requires less than one frame period, which is disadvantageous when the period is short as in the 10 BIc system. However, the dependence of the operation stop signal f on the inverted detection signal C detected from the received code string a also makes it difficult to realize the circuit.

Second, there is a problem with the synchronization determination circuit 3.

In the case of a coding system such as 10BIC, there is a high probability that reversal will be detected at a position other than the position of the reversal rule, so in order to prevent false synchronization, the synchronization judgment circuit 3 monitors the synchronization pattern error signal d at a long cycle. I find it necessary to do so. Such a synchronization determination circuit 3 is based on whether the circuit is simpler in the analog method than the conventionally used t, q7j digital method, or the third factor or the fourth factor.
The circuit shown in the figure has a drawback that the circuit configuration becomes complicated when the signal to be controlled by the AND gate 4 depends on the inversion detection signal C as described above.

To address the above-mentioned problems, a specific example of 10 BIC
This applies not only to this coding method, but also to other coding methods with similar characteristics. Also for other reasons! ：When it is necessary to employ such a coding system, it is desired to have a circuit that can replace the conventional circuit. It has been designed to solve all the problems and eliminate the drawbacks, and includes a pulse generation circuit that generates pulses with widths that are co-prominent to frame synchronization at arbitrary synchronization, and the above-mentioned redundant circuit for gold synchronization. It is a good idea to install an AND gate that inhibits the output of the circuit, and the output of this AND gate temporarily stops the operation sound of the timing generation circuit.

[Function] The pulse generation circuit generates 9 pulses repeatedly with a period of an arbitrary width, and the width is co-prime with the frame period.
When a return pulse is generated and the out-of-synchronization signal is 11'', the above-mentioned repeated pulse is input to the operation stop signal, and the timing generation circuit completely stops operating for a period of time coextensive with the above-mentioned frame period.

Accordingly, the phase of the frame period pulse and the received code string changes by a time period coexistent with the frame period.

[Heavenly Example] Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a frame synchronization circuit according to the present invention, and is an example of a synchronization circuit using the aforementioned l0BIC code. It shows.

In this gc1 diagram, parts with the same symbols as those in Figures 3 and 4 indicate corresponding parts, 7 is a pulse generation circuit that generates a pulse with an @ disjoint to the frame synchronization at an arbitrary period, 8
is an AND gate that inhibits the pulse generated by the pulse generation circuit 7 by the output of the synchronization determination circuit 3. The output of the AND gate 8 causes the operation of the timing generation circuit ffi to be temporarily stopped.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2. FIG. 2 is a waveform diagram showing the waveform of the repetitive pulse output from the pulse generating circuit γ shown in FIG.

As shown in FIG. 2, the repetitive pulse 7 output from the pulse generating circuit 7 in FIG. ).When the out-of-synchronization signal e is 11'', the operation stop signal f receives a repetitive pulse 7, and the timing generation circuit 1 operates only for the time @T+. Therefore, the phase of the frame synchronization pulse b and the received code sequence a changes by the time width TI.Then, the frame synchronization is 1
In the case of 1 bit, it is clear that the frame period pulse b has the correct phase after a maximum of 11@ repetitions.

Note that in FIG. 1, the operations of the corresponding parts indicated by the same reference numerals in FIGS. 3 and 4 are completely unchanged, and therefore their explanations will be omitted here.

〔Effect of the invention〕

As explained above, if the present invention is implemented, the pulse generation circuit that generates a pulse pulse at an arbitrary period having a width coextensive with the frame period is completely independent from other parts, so the tying generation circuit stops. The advantage is that the optimum circuit configuration can be taken, and the pulse generation interval T can be set to any desired value.
This can be calculated as the time from when the phase of the frame synchronization pulse changes until the synchronization determination circuit stabilizes, J.
:9 Since the synchronization determination circuit can be made into a simple configuration with optimal characteristics, the practical effect is extremely significant.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the frame synchronization circuit according to the present invention, Fig. 2 is a waveform diagram showing the waveform of a repetitive pulse used to explain the operation of Fig. 1, and Fig. 3 is a 1-bit immediate shift method. Circuit diagram showing an example of a conventional circuit called
The figure is a circuit diagram showing an example of a conventional circuit called a delay concentration shift method. 1...-timing generation circuit, 2... pattern detection circuit, 3... synchronization determination circuit, γ... pulse generation circuit, 8... AND gate.

Claims (1)

[Claims] A timing generation circuit that generates the timing of the waiting frame period for the function to temporarily stop the operation by an external signal, and a pattern that detects the regularity of the frame period from the received code string based on the signal of this timing generation circuit. In a frame synchronization circuit consisting of a detection circuit and a synchronization determination circuit that determines the state of synchronization based on the output of this pattern detection circuit, a pulse generator that generates a pulse having a width coextensive with the frame period at an arbitrary period. A frame synchronization circuit comprising: a circuit and an AND gate that inhibits the pulse by an output of the synchronization determination circuit, and the output of the AND gate temporarily stops the operation of the timing generation circuit. .