JPH031624A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To reduce a time required for synchronization establishment by applying re-synchronization to frame synchronization by a frame counter and word synchronization by a ring counter respectively independently. CONSTITUTION:The word synchronization by a ring counter 15 is executed in the timing when logical 1 reaches to a bit to which a frame pattern is to be reached independently of the frame synchronization by a frame counter 23. The re-synchronization of the frame synchronization by the frame counter 23 is executed by revising the phase of the frame counter 23 independently with a delay circuit 22 and a gate circuit 20 when dissidence exists in the detection output of a frame coincidence detection circuit 21. Even when the dissidence of a frame pattern is detected in the frame synchronization circuit, the phase of the frame counter 23 is changed without giving effect on the word synchronization at each occasion.

Description

[Detailed description of the invention] [Industrial application field] The present invention is used in digital communications.

INDUSTRIAL APPLICABILITY The present invention is used for frame synchronization of a backbone transmission system, a public communication network, a subscriber system, and other digital transmission systems.

The present invention is utilized for frame synchronization in which a frame pattern is distributed and transmitted in each word within a frame.

[Conventional technology]

When transmitting a series of digital signals using a frame structure, one frame has an m-word structure and one word has an n-bit structure. A method of transmitting a frame pattern having 1 bits distributed in each word, identifying the timing at which the 1 1 arrives as the frame synchronization timing, and synchronizing the frame. FIG. 6 is a block diagram of a conventional circuit for this purpose. When the number of words in one frame is m, this circuit has m-1 "0" and 1 "0" in one frame.
This circuit inputs serial data in which a frame pattern having ``1'' is distributed bit by bit, and synchronizes the frames.

The circuit shown in FIG. 6 includes a shift register 13 that converts serial data input to a terminal 11 into parallel data, and a terminal 12
a ring counter 15 that is driven by the clock of the serial data inputted to the input terminal and generates a word pulse; a latch circuit 14 that latches the contents of the shift register 13 using the word pulse; and a frame counter 23 that generates a frame pattern for each word. and the latch circuit 14
A frame coincidence detection circuit 21 detects a mismatch between the bit in which a frame pattern should arrive in each bit of the frame counter and the output of the frame counter, and resynchronization is performed when this frame coincidence detection circuit 21 sends out a mismatch output. configured to perform an action.

In this resynchronization operation, when an output is sent to the frame coincidence detection circuit 21, a signal is sent from the gate circuit 18 to the delay circuit 17 at the timing of the word pulse. The delay circuit 17 delays the signal by two clocks or more and sends it to the gate circuit 16, so that the counting operation of the ring counter I5 is missed by one clock and the timing of word pulse generation is delayed. This word pulse is given as a count input to the frame counter 23, and its output is sent to the frame coincidence detection circuit 21 at timings at which a preset frame pattern is distributed.

Therefore, when the word pulse generated from the ring counter 15 is generated at the correct timing and word synchronization is established, and the frame counter 23 is generating a frame pattern at the correct timing, a stable synchronization state exists and the frame coincidence is detected. There is no signal at the output of circuit 21.

In a practical circuit, a protection circuit is inserted at the position indicated by the symbol X in FIG. 6, so that even if the frame coincidence detection circuit 21 instructs resynchronization, resynchronization will not be executed unless it occurs a predetermined number of times in succession. It is configured as follows. Here, in order to avoid complicating the explanation, the protection circuit at the position of symbol X will be omitted from the explanation.

[Problem that the invention attempts to solve]

This circuit is an excellent circuit that detects distributed frame patterns and synchronizes frames, but in order to establish synchronization from an asynchronous state, first the ring counter 1
5 is restored, and the frame counter 23 executes a frame synchronization operation. However, if a discrepancy between the frame pattern sent from the frame counter 23 and the bits that should be received by the frame pattern is detected, the ring synchronization is performed each time. A resynchronization operation of the counter 15 is performed.

Therefore, even if the word synchronization is restored every time the frame patterns do not match, the word synchronization operation and the frame synchronization operation are executed by the ring counter 15, which has the disadvantage that the resynchronization operation takes time.

The present invention improves this and aims to shorten the time required for the resynchronization operation.

[Means to solve the problem]

The circuit of the present invention, in addition to the frame coincidence detection circuit (21), is a word asynchronous circuit that detects the arrival of an opposite logic value (logic "1" according to the conventional example described above) at a bit where a frame pattern should arrive. The present invention is characterized in that it includes a detection circuit, and means for temporarily inhibiting the counting operation of the ring counter based on the detection output of the word asynchronization detection circuit to achieve word synchronization independently of frame synchronization.

[Effect]

When a circuit performs a resynchronization operation from an asynchronous state,
Word synchronization by the ring counter (15) is performed independently of frame synchronization by the frame counter (23) at the timing when logic "1" arrives at the bit where the frame pattern should arrive. Frame counter (23
) frame synchronization is performed by a frame coincidence detection circuit (21
), frame synchronization is resynchronized by independently changing the phase of the frame counter (23) using the delay circuit (22) and the gate circuit (20). That is, in the circuit of the present invention, even if a frame pattern mismatch is detected in the frame synchronization circuit, the phase of the frame counter (23) can be changed each time without affecting word synchronization.

This occurs when the word synchronization is correct but the frame synchronization is not, i.e. the frame synchronization circuit is correctly looking at the bits that the frame pattern should arrive at, but
This is extremely effective when the frame pattern arriving at that bit and the frame pattern generated by the frame counter (23) do not match, and a synchronization state is achieved by changing the phase of the frame counter.

In this way, the overall time required to establish synchronization can be shortened.

〔Example〕

FIG. 1 is a block diagram of a circuit according to a first embodiment of the present invention.

This Example 7 circuit has m-1 one logical value (“0” in this example) and one opposite logical value (“l” in this example) in one frame. This is a circuit for synchronizing frames by inputting serial data in which a frame pattern is distributed one bit at a time. Table 1 shows an example of input data.

Input serial data arrives at terminal 11. This embodiment circuit includes a shift register 13 that converts the serial data into parallel data, a ring counter 15 that is driven by the clock of this serial data and generates a word pulse, and latches the contents of the shift register 13 using the word pulse. a latch circuit 14; a frame counter 23 that generates bits of a frame pattern distributed word by word; and a frame counter 23 that detects coincidence or mismatch between the bits of the frame pattern of the latch circuit 14 that should arrive and the output of the frame counter. A coincidence detection circuit 21 is provided.

Here, the feature of the circuit of the present invention is that the frame synchronization by the frame counter 23 and the word synchronization by the ring counter 15 are configured so that resynchronization operations can be executed independently.

That is, a delay circuit 22 and a gate circuit 20 are provided as means for temporarily inhibiting the counting operation of the frame counter 23 and resynchronizing frame synchronization when the frame coincidence detection circuit 21 detects a mismatch. Also,
Separately from this frame coincidence detection circuit 21, a one-word asynchronous detection circuit 18 is provided which detects that a logic value "1" has arrived at the bit (C) where the frame pattern should arrive,
The delay circuit 17 serves as a means for temporarily inhibiting the counting operation of the ring counter 15 based on the detection output of the word asynchronization detection circuit 18 and achieving word synchronization separately from frame synchronization.
and a gate circuit 16.

Further, in this embodiment circuit, a protection circuit 19 enables the word asynchronous detection circuit 18 only when "1" is detected over a plurality of words consecutive to the bit (C) where the frame pattern should arrive (forward protection). Equipped with.

In a practical circuit, it is preferable to insert a protection circuit at the position indicated by symbol X in order to maintain stable frame synchronization, but this will be omitted here because the explanation will be complicated.

FIG. 2 is an operation time chart of this first embodiment circuit. An example of this input data is shown in the table.

Symbols a-k in FIG. 2 indicate waveforms at points with corresponding symbols shown in FIG. As an example to simplify the explanation, 1
Table 1 shows an example of input serial data assuming that each word is 3 bits (n=3) and one frame is 5 words (m=5).

At this time, the frame pattern is F, F, F2, F, and F4 are 10,000 in this order. Further, the number of protection stages l (the number of backward protection stages) of the protection circuit 19 is assumed to be 2 here for the sake of simplicity.

(Hereinafter, this page margin) Table Example of input data F...Frame pulse D...The output of the data frame counter 23 is frame pattern F.
. -F4 appears repeatedly in order. In a state where synchronization is not established, the output d of the protection circuit 19 is "1". At this time, a resynchronization operation is executed and a hunting pulse e is sent out from the AND circuit 18. As a result, the driving pulses g of the ring counter 15 are thinned out, and the phase of the ring counter 15 is shifted. When the frame pulse F appears in the first stage C of the latch circuit 14, the AND circuit 18 becomes inhibited, the hunting pulse e disappears, and the word synchronization returns. When the word synchronization is restored, a frame pulse appears in circulation at the first stage of the latch circuit 14.

When this synchronization return state is repeated multiple times, the protection circuit 19 is reset and the output d becomes "0". As a result, word synchronization is established.

The frame counter 23 is driven by the word pulse b and the frame counter 23 is driven by the word pulse F corresponding to the frame pulse. -F, is sent repeatedly. However, the output of the frame counter 23 is F. If the first stage C of the latch circuit 14 becomes other than Fo when . is fixed. Next, the first stage C of the latch circuit 14 becomes F. Continue until
The frame counter 23 enters the driving state at the next word when the signal C becomes Fo. Frame synchronization is restored in this state.

When frame synchronization is established, the protection circuit 19
continues to be in the reset state and its output d continues to be "0". Therefore, the AND circuit 18 continues to be inhibited and resynchronization operation is prohibited.

With this circuit, there is no need to cause the word synchronization circuit to perform resynchronization each time the frame synchronization circuit performs resynchronization. That is, the word synchronization by the ring counter 15 is in a synchronization recovery state, and the frame pattern appears correctly in the output C of the latch circuit 14, but the frame pattern of this output C and the frame pattern sent out by the frame counter 23 do not match. state, the delay circuit 22 is activated according to the output of the gate circuit 21.
By the operation of the gate circuit 20, the phase of the frame counter 23 can be changed independently of word synchronization. At this time, word synchronization does not perform a resynchronization operation. Therefore, the time required for the entire resynchronization operation is shortened compared to the conventional circuit shown in FIG.

Next, considering the degree of this shortening, when one frame is composed of m words and ■words are composed of n bits, and the probability of detecting a pattern match in an asynchronous state is set to 1/2, as shown in Fig. 1. The maximum time T required for the circuit of the first embodiment to return to synchronization from an asynchronous state is:
It is the sum of the worst average word synchronization recovery time Tw from an asynchronous state to word synchronization recovery and the worst case time Tf from word synchronization recovery to frame synchronization recovery ("worst" means the case where the timing that takes the longest time happens to occur). say). Regarding the above word synchronization return time Tw, since the word synchronization counter corresponds to a 1-bit delay shift, T, = (n+1+n) (n-1)/n
(1) It is a word. This calculation formula is described in detail in Kozuka, "Transmission Characteristics of Staff Synchronization Method," Research and Practical Application Report, Vol. 18, No. 6, Published by Nippon Telegraph and Telephone Public Corporation, June 1969, and other publications, so the explanation will be omitted here. Further, the worst time Tf required for frame synchronization recovery is the case where the word synchronization recovery time exactly hits the counter value F1 of the frame counter 23, and the value of the frame counter 23 is next F. It takes about 1 frame to get F to the input frame pattern. Approximately one additional frame is required for this to appear, so the total time is approximately two frames. Therefore, when m=72 and n=9 as practical values, T
I=T w + T f =17 words+2 frames-2,2 frames. As a comparative example, in the conventional example shown in FIG. 6, resynchronization of word synchronization is executed every time the frame patterns become inconsistent, so the worst time until the entire synchronization is restored is
According to the above document, To = <n+ 1+n
)(mn-1)/mn frames. Substituting the above case of m=72 and n=9 into this, it becomes To"19 frames. In other words, compared to the worst time, the effect of this embodiment is that the time from the asynchronous state to the synchronous state is only 11 This will be shortened to .6%.

By the way, in the circuit shown in FIG. 1, it is possible to shorten the time until synchronization is restored by performing resynchronization in this way, but after synchronization is restored, before the protection circuit 19 is reset, i.e. If, before the word synchronization is established, a "1" of the frame pattern happens to appear in bit C, where the frame pattern should arrive, the word synchronization will perform a resynchronization operation. To avoid this, mn> (n+1+n) (n-1) +in between the number of words of an I frame, m, the number of bits of one word, n1, and the number of backward protection stages, β, of the protection circuit 19.
(3) The following conditions are necessary.

The left side of equation (3) is the time for one frame, the first term on the right side is the word synchronization recovery time expressed in the number of bits given by equation (1), and the second term is the backward protection after word synchronization recovery. This is the time until the protection circuit 19 is reset by the operation.

On the other hand, the number of backward protection stages l of the protection circuit should be determined based on how many times the synchronization state must be detected to establish the synchronization state in order to avoid false synchronization establishment. "Practical Application of Equipment" Research and Practical Application Report published by Nippon Telegraph and Telephone Public Corporation, Vol. 25, No. 1, 19
Using the results of the study in 1997, it is said that ogq is appropriate, where q is the probability of coincidence detection, ρh is the risk of false synchronization, and n is the number of bits in one word. As practical numerical values, if the false synchronization risk rate ρh is 1%, the coincidence detection probability q is 0.5, and for example n=17, the above equation (4) can be obtained. If f=11, then the value of m that satisfies equation (3) will be 44 or more, and it can be seen that frame synchronization cannot be recovered if a frame with a word count less than 44 is used. In other words, in relation to the number l of backward protection stages of the protection circuit 19, the number m of words in the frame and the number n of bits in the hood
There is a constraint between .

A circuit improved from this is a circuit according to a second embodiment of the present invention shown in FIG. In this example, a discrepancy detection circuit is provided to detect that a logic value "1" has arrived twice in a row at the time when the frame pattern should arrive. That is, one of the AND circuits 32 receives the bit C to which the frame pattern should arrive.
The current value of is given to the other side of the AND circuit 32, and the value of the bit where the frame pattern at the time of the previous word synchronization judgment should arrive is held in the flip-flop 31 and given to the other side of the AND circuit 32. The output of the AND circuit 32 is supplied to the gate circuit 18 to temporarily inhibit the counting operation of the ring counter 15, thereby providing word synchronization in addition to frame synchronization. Furthermore, this means for synchronizing words is such that even if a logic value "1" arrives twice in a row at bit C where the frame pattern should arrive, immediately after the detection of the first "1" of the two times. When the bit of is "0" and the second of the two times is the next synchronization judgment timing after temporarily prohibiting the counting operation of the ring counter, execution of the resynchronization operation is prohibited. It is characterized by That is, the size of the latch circuit 14 is increased by one bit so that it can detect the pip (d) immediately after the previous word synchronization detection time, and this is realized by the gate circuit 34, flip-flop 33, and gate circuit 35.

FIG. 4 shows an operation time chart of this second embodiment circuit. FIG. 5 shows an example of the input data of the second embodiment circuit, the word synchronization determination position, and the bits on which the logical product circuit 32 detects the logical product.

In this circuit, the frame pattern should arrive at bit C
When a logic "1" appears twice in a row at the word synchronization determination position, resynchronization is activated, but if there is a frame pattern 1 bit after the first of these two determination positions, resynchronization is activated. Since there is no need to perform a synchronization operation, execution of a resynchronization operation is prohibited in this case. Therefore, even if the frame pattern "1" is detected before the protection circuit 19 starts the protection operation, the resynchronization operation will not be started immediately, and the frame pattern will be There is no longer any conflict between the number of words in the word and the number of bits in the word that would make it impossible to perform a synchronous operation under certain conditions.

The frame pattern explained in the above example has its logical value "1"
The present invention can be implemented in the same manner even if "0" is inverted.

〔Effect of the invention〕

As explained above, according to the present invention, the word synchronization circuit does not perform a resynchronization operation every time a resynchronization operation is performed regarding the frame synchronization circuit, so it takes a long time to return to synchronization from an asynchronous state. This has the effect of significantly shortening the time.

Furthermore, in the invention according to claim 2, in addition to the above-mentioned effect, there is no need to set a specific constraint between the number of words in a frame and the number of bits in a word in relation to the number of backward protection stages of the protection circuit. This has the effect of enabling design with a large degree of freedom.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit according to a first embodiment of the present invention. FIG. 2 is an operation time chart of the circuit of the first embodiment. FIG. 3 is a block diagram of a circuit according to a second embodiment of the present invention. FIG. 4 is an operation time chart of the circuit of the second embodiment. FIG. 5 is a diagram showing an example of input data of the second embodiment circuit. FIG. 6 is a block diagram of a conventional circuit. 1', ++1. −

Claims (1)

[Claims] 1. Input serial data in which a frame pattern having m-1 one logical value and one opposite logical value is distributed in each word, bit by bit, in one frame. A shift register (13) that converts serial data into parallel data, a ring counter (15) that is driven by the clock of the serial data and generates a word pulse, and a latch circuit (15) that latches the contents of the shift register using the word pulse. 14), a frame counter (23) that generates a frame pattern for each word, and a frame coincidence detection circuit (23) that detects a mismatch between the bits to which the frame pattern of the latch circuit (14) should arrive and the output of the frame counter. 21) and means for temporarily inhibiting the counting operation of the frame counter to achieve frame synchronization when the detection circuit detects a mismatch, the frame synchronization circuit comprising: , a word asynchronous detection circuit (18) is provided for detecting that the opposite logic value has arrived at the bit where the frame pattern should arrive, and the counting operation of the ring counter is temporarily inhibited by the detection output of the word asynchronous detection circuit. means for achieving word synchronization separately from frame synchronization, and when in the word synchronization state, the word synchronization is performed unless the opposite logic value arrives multiple times in succession at the timing of the word pulse at the bit where the frame pattern should arrive; A frame synchronization circuit characterized by comprising a protection circuit (19) for inhibiting operation of a means for synchronizing. 2. Input serial data in which a frame pattern having m-1 one logical value and one opposite logical value is distributed in each word, one bit at a time, in one frame, and convert this serial data into parallel data. a shift register (13) for converting; a ring counter (15) driven by the clock of the serial data to generate a word pulse; a latch circuit (14) for latching the contents of the shift register by the word pulse; a frame counter (23) that generates a frame pattern at a time; a frame coincidence detection circuit (21) that detects a mismatch between the bits to which the frame pattern of the latch circuit (14) should arrive and the output of the frame counter; In a frame synchronization circuit comprising means for temporarily inhibiting the counting operation of the frame counter to achieve frame synchronization when the circuit detects a mismatch, the frame synchronization circuit includes a means for synchronizing the frame by temporarily inhibiting counting operation of the frame counter when the circuit detects a mismatch, the frame synchronization circuit having a means for synchronizing the frame by temporarily inhibiting counting operation of the frame counter when the circuit detects a mismatch. If the opposite logical value is 2 for the bit to be
A discrepancy detection circuit (1
8, 31, 32), and means for temporarily inhibiting the counting operation of the ring counter based on the detection output of the mismatch detection circuit to achieve word synchronization in addition to frame synchronization, so that the frame pattern matches the bit to which the frame pattern should arrive. Even if the opposite logical value arrives two times in a row, the bit immediately after the detection point of the opposite logical value on the first of the two times is the one logical value, and two of the two times means (33, 34, 35) for inhibiting the operation of the means for synchronizing the word when the counting operation of the ring counter is temporarily inhibited; In some cases, a protection circuit (19) is provided for prohibiting the operation of the word synchronization means unless the opposite logic value arrives a plurality of times in succession at the timing of the word pulse at the bit where the frame pattern should arrive. A frame synchronization circuit characterized by: