JPH0329435A - Frame synchronization circuit - Google Patents

Abstract

PURPOSE:To attain the synchronization restoration even in a frame pattern with lots of bit numbers in one work in comparison with a word number in one frame by avoiding out of synchronism at the location of a frame pattern representing the head of the frame before a word synchronizing circuit enters the synchronizing establish state. CONSTITUTION:A serial parallel conversion means 3a converts an input data into a (n+1)-bit parallel signal, a latch means 4a latches and outputs the input data converted according to a word pulse. Then a logical arithmetic means 5e uses, e.g. an AND circuit to AND the output of the 1st stage of the latch circuit 4a with an output of the (n+1)-th stage, inputs the result to a synchronization protection means 8 and a discrimination means, from which a hunting pulse is generated. Since the AND logic does not go to logical '1' when outputs of the 1st stage and the (n+1)-th stage of the latch circuit 4a are not both logical '1', the AND logic goes to logical '1' before the word circuit synchronization restores and goes to logical '0' after synchronization restoration. Thus, no hunting pulse is generated, the restoration to the out of synchronism is prevented. Thus, synchronization restoration is surely implemented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is utilized for a frame synchronization circuit used for synchronization control of digital transmission systems such as backbone transmission systems, public networks, and subscriber systems. Within one frame (m-1
A frame synchronization circuit that performs frame synchronization after expanding n-bit parallel time-division multiplexed high-speed signals in word units, in which a frame synchronization pattern having ( ) "0" and one "l" is arranged bit by bit. Regarding.

[Conventional technology]

FIG. 4 is a block diagram showing an example of a conventional frame synchronization circuit of this type. In FIG. 4, 1 is input data, 2 is an input clock synchronized with input data 1, 3 is a shift register that performs serial-to-parallel conversion, 4 is a latch circuit, and 5a
, 5b, 5c and 5d are AND circuits, 5a)
6b and 6C are inverters, 7 is a ring counter, 8
is a word synchronization protection circuit, 9 and 11 are delay circuits, and 10 is a frame counter. It should be noted that a frame synchronization protection circuit is inserted and utilized at the position marked with an x in the lower right corner of FIG. 4, but this is omitted because the explanation would be complicated. Here, circuits 5a, 6a, 7, 8, 5b and 9 constitute a word synchronization circuit, and circuits 5d, 6b. 10, 5c, 6c and l
1 constitutes a frame synchronization circuit.

Next, the operation of this conventional example will be explained.

As an example of input data 1 is shown in Fig. 3, one word is a frame pattern with m-1 degrees of "0" and one "l" (indicating the beginning of the frame) in one frame. This is an information string in which one bit is distributed for each bit. The shift register 3 has stages for one word (n bits), and input data 1 is input to the first stage by an input clock 2 synchronized with the input data 1, and is sequentially sent to the subsequent stage. The latch circuit 4 latches the output of each stage of the shift register 3 using a word pulse a. The ring counter 7 divides the input clock 2 by n and outputs the word pulse a. The word synchronization protection circuit 8 receives the output of the first stage of the latch circuit 4 using the word pulse a.

When a predetermined number of consecutive "1"s are input, the word synchronization protection circuit 8 is set and outputs rlJ to the output C.

On the other hand, when a predetermined number of consecutive "0"s are input, the word synchronization protection circuit 8 is reset and outputs "0" to the output C. The delay circuit 9 delays the hunting pulse d output by the AND circuit 5b by two clocks. The frame counter 10 divides the word pulse a by m (the number of words in one frame) and outputs a frame pulse g. The delay circuit l1 delays the hunting pulse h output from the AND circuit 5C by one word.

In the out-of-synchronization state, the word synchronization protection circuit 8 is in the set state, and its output C is "1". In the synchronization recovery process, the output b of the lth stage of the latch circuit 4 becomes "1".
'', since the output C is ``1'', the hunting panorez d becomes ``IJ'', and the input clock 2 is inhibited by 1 clock in the AND circuit 5a, so the word synchronous circuit does not hunt. , the next word pulse a is delayed by one clock than usual.Latch circuit 4
When the output b of the first stage has the same sign as "0" of the frame pattern, the hunting pulse d becomes "0", and the ring counter 7 continues to count up with the input clock 2. If the output b of the first stage of the latch circuit 4 is "0" of the true frame pattern, the word synchronization circuit returns to synchronization.

Next, the output b of the first stage of the latch circuit 4 becomes "0"
If so, the word synchronization protection circuit 8 is reset,
The output C becomes "0" and the word synchronization establishment state is entered.

After the word synchronization is restored, the frame synchronization process begins. In the frame synchronization circuit, when the frame pulse g is "l" and the output b of the first stage of the latch circuit 4 is "0", the hunting pulse h becomes "lj", and the input pulse J of the frame counter 10 becomes "lj". Since 1 bit is inhibited, the frame synchronization circuit hunts.If the frame pulse g is "1" and the output b of the lth stage of the latch circuit 4 is "1", the hunting pulse h is "0". ”, so
The frame counter IO is directly counted up by the input pulse J, and the frame synchronization circuit 22 returns to synchronization.

Next, the operation of this conventional example will be further explained using FIGS. 3 and 5.

FIG. 4 shows input data 1 when one word and three pits t- (n=3) and one frame are five words (n=5). In this case, the frame pattern is Fo""I F, , F2, F. , F. =0. Here, DI, D2, represent data.

FIG. 5 is a time chart showing the operation when such input data 1 arrives. Note that the symbols D+, D4, F3, F4, shown in FIG.
This corresponds to the same symbol shown in the figure. Frame patterns F0 to F4 repeatedly appear in the frame pulse g output from the frame counter IO.

In the circuit of FIG. 4, in the out-of-synchronization state, the word synchronization protection circuit 8 is in the set state, so its output C is "
It is fixed at 1. Now in an out-of-sync state,
The frame pulse g from the frame counter lO is F. That is, when it is "1", it is assumed that data D1, that is, "1" is output to the first stage output b of the latch circuit 4.

First, the operation of the word synchronization circuit 8 will be explained. in this case,
Hunting pulse d has the same output as word pulse a because word pulse a1 output b and output C are "1".

Therefore, the output e of the delay circuit 9 becomes as shown in the figure, and the count-up clock f of the ring counter 7 is inhibited by one clock. Therefore, the next word pulse a output from the ring counter 7 is 1 word more than 1 word.
After a clock delay, data D, ie, "l" appears at the output b of the first stage of the latch circuit 4. In this case as well, since the hunting pulse d becomes "l", the word pulse a outputted from the next ring counter 7 is delayed by one clock from the l word, and the output b of the lth stage of the latch circuit 4 is a frame. Pattern F3 appears. In this case, the hunting pulse d becomes "0" and the word synchronization circuit returns to synchronization.

A frame pattern F4 appears at the first stage output b of the latch circuit 4 due to the next word pulse a output from the ring counter 7. Assuming that the word synchronization protection circuit 8 has two stages, the word synchronization protection circuit 8 is reset and its output C becomes "0". This causes the word synchronization circuit to enter a synchronization establishment state.

Next, the operation of the frame synchronization circuit will be explained. Since the frame counter 10 is counted up by the word pulse a output from the ring counter 7, the output frame pulse g includes Fo, F+, F2 while the delay pulse l of the hunting pulse h is "0". , F3
, F4 appear in this order. However, when the frame pulse g is F0, that is, "1", the latch circuit 4
When the output b of the second stage is "0", the hunting pulse h becomes "1", so the next input clock J of the frame counter 10 is inhibited, and the frame pulse g output from the frame counter 10 is F. stay in position. In this operation, the output b of the first stage of the latch circuit 4 is F. It continues until The output b of the first stage of the latch circuit 4 is F. When this occurs, the hunting pulse h becomes "0" and the frame synchronization circuit returns to synchronization.

[Problem that the invention seeks to solve]

In the conventional frame synchronization circuit described above, after the word synchronization circuit 2l returns to synchronization and before the word synchronization protection circuit 8 is reset and enters the synchronization establishment state, the frame pattern Fo, that is, "1" is input to the first stage of the latch circuit 4. When it appears at the output b of For example, when the number of stages of the word synchronization protection circuit 8 is five, in FIG.
In other words, the synchronization is lost when "1" appears.

Note that this becomes a problem when the sum of the word synchronization recovery time and the backward protection time of the word synchronization protection circuit 8, that is, the time from word synchronization recovery to establishment of word synchronization, becomes longer than one frame length.

This is frame pattern F. In other words, even if "1" causes an out-of-synchronization state, the F of the next frame pattern
. This is because there is no problem as long as the word synchronization is restored and the word synchronization is established before the arrival of the word synchronization. The word synchronization recovery time and backward protection time become longer as the number of bits n of l word becomes larger. Therefore, a problem with this circuit occurs when the ratio of the word length to the frame length is large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a frame synchronization circuit in which the word synchronization circuit does not return to an out-of-synchronization state after returning to synchronization and before entering a synchronization established state, by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides (m-1) one logical values and one logical value in one frame.
A frame synchronization circuit equipped with means for performing frame synchronization after parallel expansion of input data consisting of a time-division multiplexed high-speed signal in which a frame synchronization pattern having opposite logical values is distributed one bit per word in units of words. a serial-to-parallel converter for converting the input data into an (n+1)-bit parallel signal; a latch for latching the output of the serial-to-parallel converter according to an input word pulse; and an input clock synchronized with the input data. frequency dividing means for dividing the frequency into a word period (1/n) and outputting the word pulse; logical operation means for performing a predetermined logical operation on the output of the first stage and the output of the (n+1)th stage of the latch means; , a determining means for determining whether the output of the logical operation means is the frame synchronization pattern, a synchronization protection means, and the output of the synchronization protection means indicates an out-of-synchronization state, and the determination means detects that it is not the frame synchronization pattern. The present invention is characterized by comprising a delay shift type word synchronization circuit including a delay processing means for delaying the output of the frequency dividing means by one clock of the input clock when

[Effect]

The serial/parallel conversion means converts the input data into an (n+1) bit parallel signal, and the latch means latches and outputs the converted input data according to the word pulse. Then, the logic operation means uses, for example, an AND circuit to logically AND the output of the first stage of the latch circuit and the output of the (n+1)th stage, and inputs the logical product to the synchronization protection means and the determination means to generate a hunting pulse. The logical product is “unless both the outputs of the first stage and the (n+1)th stage of the latch circuit are “L”.
1", so before the word synchronization circuit returns to synchronization, "
1", and becomes "0" after synchronization is restored.

As a result, after the word synchronization circuit returns to synchronization, the frame pattern F is generated before the synchronization protection means is reset and the synchronization establishment state is entered. That is, even if "1" appears at the output of the first stage of the latch means, the logical product is "0",
Since the hunting pulse is not generated, there is no possibility of returning to the out-of-synchronization state.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In this embodiment, there are (m-1) “0” and 1 “0” in one frame.
A frame equipped with a means for performing frame synchronization after parallel expansion of input data l consisting of a time-division multiplexed high-speed signal in which a frame synchronization pattern having "1" is distributed one bit per word in units of words. In the synchronous circuit, there is a shift register 3a as a serial/parallel conversion means for converting input data 1 into an (n+1) bit parallel signal, and a latch as a latch means for latching the output of this shift register 3a according to an input word pulse a. A circuit 4a, a ring counter 7 as a frequency dividing means that divides the input clock 2 synchronized with the input data 1 into a word period (1/n) and outputs a word pulse a, and the first stage output b of the latch circuit 4a. . , the word synchronization protection circuit 8 as a synchronization protection means, and the output C2 of this word synchronization protection circuit 8 indicate an out-of-synchronization state, and when the AND circuit 5b detects that it is not a frame synchronization pattern, the ring counter 7 A delay circuit 9 as a delay processing means for delaying the word pulse a by one clock of the input clock 2, a delay shift type word synchronization circuit including an inverter 6a and an AND circuit 5a, and further includes AND circuits 5C and 5d, Inverter 6b
and 6C% frame counter 10 and delay circuit 1
The frame synchronization circuit includes a frame synchronization circuit including 1.

A frame synchronization protection circuit is inserted and utilized at the position marked x in the lower right corner of FIG. 1, but this is omitted here because the explanation would be complicated.

The feature of the present invention is that in FIG. 1, the shift register 3a
This is because a latch circuit 4a and a word synchronization circuit including an AND circuit 5e are provided.

Next, the operation from the out-of-synchronization state to the recovery of frame synchronization in this embodiment will be explained with reference to FIGS. 2 and 3. Here, FIG. 3 is an explanatory diagram showing input data l, and FIG. 2 is a time chart showing operation waveforms at various points in this embodiment. D1, D3, F, . . . in FIG. 2 correspond to input data with the same symbols in FIG. 3.

Since the synchronization is initially out of synchronization, the word synchronization protection circuit 8
It is assumed that is in the set state and its output c2 is "1". Initially, the first stage of the latch circuit 4a and (n
+1) data D3 to the outputs b1 and b2 of the 1st stage, respectively.
and D1 appear, AND circuit 5e
Since the output c1 of the word synchronization protection circuit 8 is "1" and the output c2 of the word synchronization protection circuit 8 is "1", the hunting pulse d which is the output of the AND circuit 5b becomes the same as the word pulse a. This hunting pulse d is delayed by two periods of the input clock 2 by the delay circuit 9 to become a delayed pulse e, which is applied to the AND circuit 5a via the inverter 6a.

As a result, the next count-up clock f to the ring counter 7 is stopped, so the next word pulse a is 1
It is delayed by one clock from the word.

Due to this word pulse a, data D6 and D4 appear at the outputs b1 and b2 of the latch circuit 4a, respectively.

In this case as well, the output c1 of the AND circuit 5e becomes "l", so the hunting pulse d becomes "1", and therefore the next word pulse a is delayed by l clocks from one word. This word pulse a causes the output b of the latch circuit 4a to
1 and b2 have frame pulses F4 and F, respectively.
3 appears. In this case, the output c1 of the AND circuit 5e becomes "0", so the hunting pulse d becomes "0". At this point, the word synchronization circuit returns to synchronization.

When the hunting pulse d is "0", the next count-up clock f of the ring counter 7 is not stopped, so the next word pulse a is output one word later. Thereafter, the same operation is repeated, and when the outputs b and b2 of the latch circuit 4a become frame pulses F3 and F2, respectively, the word synchronization protection circuit 8 is reset, its output c2 becomes "0", and the word synchronization circuit Enters synchronization establishment state. However, the number of protection stages of the word synchronization protection circuit 8 is set to 3.
It's in stages. As shown in FIG. 2, in this embodiment, after the word synchronization circuit returns to synchronization, F of the frame pattern. That is, since the hunting pulse d becomes "0" at the "l" position, synchronization does not occur. The operation of the frame synchronization circuit is similar to the conventional example shown in FIG.

As described above, in this embodiment, the word synchronization circuit 21
After a returns to synchronization and before the word synchronization circuit enters the synchronization establishment state, F of the frame pattern. In other words, even if "1" arrives, synchronization will not occur.

In this embodiment, the input data l is an information string in which a frame pattern having m-1 "0"s and one "1" in one frame is distributed with one pit per word. However, the present invention can be applied even if the frame pattern has "1" and "0" reversed.

〔Effect of the invention〕

As explained above, in the present invention, before the word synchronization circuit enters the synchronization established state, synchronization does not occur at the position of the frame pattern indicating the beginning of the frame. This has the effect that synchronization can always be recovered even in a frame pattern in which the number of word bits is large.

Note that the present invention is particularly effective in a system in which frame synchronization is achieved by a violation of the mBIC code.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a time chart showing the operation. FIG. 3 is an explanatory diagram showing an example of input data used in the present invention. FIG. 4 is a block diagram showing a conventional example. FIG. 5 is a time chart showing the operation. 1... Input data, 2... Input clock, 3, 3a
...Shift register, 4, 4a...Latch circuit, 5
a to 5e...AND circuit, 6a to 6C...inverter, 7...ring counter, 8...word synchronization protection circuit, 9, l1...delay circuit, 10...frame counter.

Claims (1)

[Claims] 1. Time division multiplexing in which a frame synchronization pattern having (m-1) one logical value and one opposite logical value is distributed in one bit per word in one frame. A frame synchronization circuit equipped with means for performing frame synchronization after parallelizing input data consisting of high-speed signals word by word, comprising: a serial-to-parallel conversion means (3) for converting the input data into an (n+1) bit parallel signal; a latch means (4) for latching the output of the serial-to-parallel converter according to an input word pulse; and a part for dividing an input clock synchronized with the input data into a word period (1/n) and outputting the word pulse. a logic operation means (5e) for performing a predetermined logical operation on the output of the first stage of the latch means and the output of the (n+1)th stage of the latch means; a determining means (5b) for determining whether the frame synchronization pattern is the same, a synchronization protection means (8), and when the output of the synchronization protection means indicates an out-of-synchronization state and the determination means detects that the pattern is not a frame synchronization pattern, the frequency division means A frame synchronization circuit comprising: a delay shift type word synchronization circuit including delay processing means (9, 5a, 6a) for delaying an output by one clock of the input clock.