JPH0329437A - Frame synchronization circuit - Google Patents

Abstract

PURPOSE:To reduce the time from the asynchronizing state till the synchronization restoration by avoiding a word synchronization from executing resynchronization every execution of resynchronization by a frame synchronizing circuit. CONSTITUTION:When the circuit executes the resynchronization from an asynchronous state, the word synchronization by an n-adic counter 27 is executed independently of the frame synchronization by a frame counter 23 in the timing when logical '1$' appears at the output of an exclusive NOR circuit 19. The frame synchronization by the frame counter 23 is executed when dissidence appears at the detection output of a frame coincidence detection circuit 21 and the resynchronization of the frame synchronization is executed by revising the phase of the frame counter 23 independently by means of a delay circuit 22 and a gate circuit 20. That is, even when the dissidence of the frame pattern is detected by the frame synchronization circuit, the phase of the frame counter 23 is changed without giving effect onto the word synchronization. Thus, the time till the synchronization establishment is reduced as a whole.

Description

[Detailed description of the invention] [Industrial application field] INDUSTRIAL APPLICATION This invention is utilized for digital communication.

INDUSTRIAL APPLICABILITY The present invention is used for frame synchronization of a backbone transmission system, a public communication network, a subscriber system, and other digital transmission systems.

The present invention uses m8, which is a transmission line code to avoid consecutive 0s.
It is used for a method of achieving frame synchronization by violation of the 1c code.

[Conventional technology]

When transmitting a series of digital signals using a frame structure, one frame has a structure of m words, and one word consists of n-1 bits of data and a 1-bit C code (complementary code) or the opposite of the complementary code. When the n-bit structure consists of a code, the l bit at a specific position in each word of m-1 words in one frame is the complement code of the bit before or after the bit ( C bit)
The bit at a specific position within the remaining word transmits a data string consisting of the same code as the bit before or after the bit (referred to as C-bit violation code τ). However, a method is known in which frame synchronization is achieved by identifying the timing at which the C-bit violation code arrives as the frame synchronization timing.

FIG. 8 is a block diagram of a conventional circuit for this purpose. When the number of words in one frame is m words, this circuit is a series circuit in which m-1 C bits and 1 C-bit violation code τ are distributed one bit at a time in one frame. This is a circuit that inputs data and performs frame synchronization.

The circuit shown in FIG. 8 includes a shift register 13 that converts serial data input to a terminal 11 into parallel data, and a terminal 12.
a ring counter 15 that is driven by the clock of the serial data inputted to the input terminal and generates a word pulse; a latch circuit 14 that latches the contents of the shift register 13 using the word pulse; An exclusive NOR circuit (EX-NOR circuit) 19 that takes the opposite logic of the exclusive OR of the bit where the C-bit violation code τ bit is to arrive and the bit immediately before that bit. , a frame counter 23 that generates a frame pattern for each word, and the output of the exclusive NOR circuit 19 and the frame counter 23.
Frame coincidence detection circuit 2 detects a mismatch between the output and the output.
1, and is configured to perform a resynchronization operation when this frame coincidence detection circuit 21 sends out a mismatch output.

In this circuit, the C bit is the complementary sign of the bit immediately before it (
opposite sign> and C-bit violation code τ
It is assumed that a bit has the same sign as the bit immediately before it. Therefore, when in the synchronized state, a half-frame pattern appears at the output of the exclusive NOR circuit 19.

In the resynchronization operation, when an output is sent to the frame coincidence detection circuit 21, a signal is sent from the gate circuit 18 to the delay circuit 17 at the timing of the word pulse. The delay circuit 17 delays the signal by a timing of 2 clocks or more and 1 word or less, and sends it to the gate circuit 16, so that the counting operation of the ring counter 15 is missed by 1 clock, and the timing of word pulse generation is delayed. It will be done. This wide pulse is given as a count input to the frame counter 23, and its output is sent to the frame coincidence detection circuit 21 at timings at which preset frame patterns are distributed.

Therefore, when the word pulse generated from the ring counter l5 is generated at the correct timing and word synchronization is established, and the frame counter 23 is generating a frame pattern at the correct timing, a stable synchronization state exists and the frame coincidence detection circuit There is no signal at the output of 21.

In a practical circuit, a frame synchronization protection circuit is inserted at the position indicated by the symbol X in the lower right corner of FIG. It is configured not to perform resynchronization.

Here, in order to avoid complicating the explanation, the frame synchronization protection circuit at the position of symbol X will be omitted from the explanation.

[Problem to be solved by the invention]

This circuit is an excellent circuit that detects distributed frame patterns and achieves frame synchronization, but in order to establish synchronization from an asynchronous state, first the ring counter I
5 is restored, and the frame counter 23 executes the frame synchronization operation. However, when a mismatch between the frame pattern sent from the frame counter 23 and the output of the exclusive NOR circuit 19 is detected, the A resynchronization operation of the ring counter 15 is performed each time. Therefore, even if word synchronization is restored for each mismatch of frame patterns, the word synchronization operation and the frame synchronization operation are executed by the ring counter 15, which has the disadvantage that the resynchronization operation takes time.

Further, in this conventional circuit, a loopback loop exists in the high-speed circuit section 9, and the delay accuracy of the loopback loop must be suppressed to within a half period of the input clock input to the terminal 12. However, since each circuit element generally has delay variations, in order to satisfy the above conditions, the high-speed circuit section 9 cannot be designed to operate at high speed up to the operating limit of each circuit element. Therefore, this conventional circuit has a drawback that it is not suitable for an ultra-high speed frame synchronization circuit.

The present invention aims to improve these drawbacks, and aims to provide a frame synchronization circuit that reduces the time required for resynchronization operations and is suitable for ultra-high-speed frame synchronization circuits.

[Means to solve the problem]

The circuit of the present invention includes an n-ary counter (27) that is driven by the output of the ring counter (15) and outputs the count value as a control signal, and an n-ary counter (27) that is driven by the output of the ring counter (15) and outputs the count value as a control signal;
bit and a bit obtained by delaying the n-th bit of the output of the latch circuit (14) by 1 bit, and according to the control signal from the n-ary counter (27), the C bit or the violation code τ of the C bit is input. an output selection means (30) for selectively outputting the bit at which the bit should arrive and the bit one bit before that bit, and the output selection means (30);
In addition to the exclusive NOR circuit <19> which takes the opposite logic of the exclusive OR between the two bits of the output of 30) and the frame coincidence detection circuit (21>), the exclusive NOR circuit (
A word asynchronous detection circuit (18) is provided to detect that the output of the word asynchronous detection circuit (19) is logic "1", and the detection output of the word asynchronous detection circuit (18) causes the n-ary counter (2
The present invention is characterized in that it includes means for achieving word synchronization independently of frame synchronization by incrementing the count value of 7) by one.

[Effect]

When a circuit performs a resynchronization operation from an asynchronous state,
Word synchronization by the n-ary counter (27) is performed with frame synchronization by the frame counter (23) at the timing when a logic "1" appears at the output of the exclusive NOR circuit (19) which takes the opposite logic of the exclusive OR. are executed independently. Frame synchronization by the frame counter (23) is performed by the frame counter (23) by the delay circuit (22> and gate circuit (20)) when a mismatch appears in the detection output of the frame coincidence detection circuit (21).
) is executed by independently changing the phase of That is, in the circuit of the present invention, even if a frame pattern mismatch is detected in the frame synchronization circuit, the phase of the frame counter (23) can be changed each time without affecting word synchronization.

This occurs when the word synchronization is correct but the frame synchronization is not, i.e. the frame synchronization circuit is correctly looking at the bits where the frame pattern should appear, but
The frame pattern appearing in that bit and the frame pattern generated by the frame counter (23) do not match, and changing the phase of the frame counter is extremely effective when entering a synchronized state.

In this way, the overall time required to establish synchronization can be shortened.

Further, in the circuit of the present invention, the loopback loop related to word synchronization includes the n-ary counter (27) that operates at 1/n of the input clock, the output selection means (30), and the exclusive NOR circuit (19). , and a word asynchronous detection circuit (18), and there is no loopback loop to the serial-to-parallel converter (lO), which operates at high speed, so the serial-to-parallel converter (10) operates to the operating limit of the constituent circuit elements. can be done. That is, in the circuit of the present invention, the frame synchronization circuit is configured completely separate from the serial-to-parallel converter (10) consisting of a high-speed circuit, so it is suitable as a frame synchronization circuit for ultra-high-speed signals.

〔Example〕

FIG. 1 is a block diagram of a circuit according to a first embodiment of the present invention.

In this embodiment circuit, when the number of words in one frame is m words, m-1 C bits and one C bit violation code τ bit are distributed in one bit each. This circuit inputs serial data and synchronizes frames. Here, the C bit is the complementary code of the bit immediately before the C bit, and the violation code τ bit of the C bit is the same code as the bit immediately before the C bit. Table 1 shows an example of input data.

Input serial data arrives at terminal 11. This embodiment circuit includes a shift register 13 that converts the serial data into parallel data, a ring counter 15 that is driven by the clock of this serial data and generates a word pulse, and a latch that latches the contents of the shift register 13 using the word pulse. The circuit 14, the n-ary counter 27 which is driven by the word pulse and outputs the count value as a control signal, and the n-1 bits from the second bit to the nth bit of the output of the latch circuit 14 are each converted into one bit of the word pulse. The delay circuit 28 that delays the clock and the output n of the latch circuit 14
bit and the n-th bit of the output of the delay circuit 28,
A shift matrix 30 for selectively outputting the bit at which the C bit or the violation code T bit of the c bit should arrive and the bit 1 bit before that bit according to the control signal output from the n-ary counter 27, and the shift matrix 30; An exclusive NOR circuit 19 that takes the opposite logic of the exclusive OR between two bits of the output of the matrix 30, and bits of the same series as each bit of the frame pattern to appear in the output of this exclusive NOR circuit 19. a frame counter 23 that generates a frame counter 23, a frame coincidence detection circuit 21 that detects coincidence or mismatch between the output of the exclusive NOR circuit 19 and the output of the frame counter 23, and a latch circuit I.
4 and n-1 bits of the output of the delay circuit 28, and selects and outputs n bits of each word according to the control signal of the output of the n-ary counter 27.

Here, the feature of the circuit of the present invention is that the frame synchronization by the frame counter 23 and the word synchronization by the n-ary counter 27 are configured so that resynchronization operations can be executed independently.

That is, a delay circuit 22 and a gate circuit 20 are provided as means for temporarily inhibiting the counting operation of the frame counter 23 and resynchronizing frame synchronization when the frame coincidence detection circuit 21 detects a mismatch. Also,
Separately from this frame coincidence detection circuit 21, a word asynchronous detection circuit 18 is provided which detects the appearance of the logical value "l" in the output of the exclusive NOR circuit 19. A delay circuit 25 and a gate circuit 26 are provided as means for incrementing the count value of the n-ary counter 27 by one and achieving word synchronization in addition to frame synchronization.

In addition, in this embodiment circuit, in the word synchronization established state, only when the logic value "1" is detected over a plurality of consecutive words at the output of the exclusive NOR circuit 19 (forward protection), the word synchronization is established. enable the asynchronous detection circuit 18;
When word synchronization is not established, the exclusive NOR circuit 19 outputs a logical value "
The word asynchronous detection circuit 18 is provided with a protection circuit 24 that disables the word asynchronization detection circuit 18 only when the word asynchronous detection circuit 18 is detected.

In a practical circuit, it is recommended to insert a protection circuit at the position marked X at the bottom right of Figure 1 in order to maintain stable frame synchronization, but this will be omitted here as the explanation will be complicated. . This also applies to FIGS. 3 to 7, which will be described later.

FIG. 2 is an operation time chart of this first embodiment circuit. Symbols a, bl-g1, h to k, p-s in FIG. 2 indicate waveforms at points with corresponding symbols shown in FIG. As an example to simplify the explanation, one word is 3 bits (n=3
), one frame has 5 words (m=5), and an example of input serial data is shown in Table 1. Table 1 also shows the frame pattern generated by the exclusive NOR circuit 19.

F. F,F. F,F. becomes 1 (1 (100) in order. In addition, the number of backward protection stages of the protection circuit 24 is assumed to be 2 for the purpose of simplifying the explanation. Initially, the control signal k, which is the count value of the n-ary counter 26, is 0. shall be.

(Hereinafter, this page margin) The output l of the frame counter 23 has a frame pattern F.
. -F4 appears repeatedly in order. In a state where synchronization is not established, the output g of the protection circuit 24 is "1". At this time, a resynchronization operation is executed and a count up pulse h is sent out from the gate circuit 18. As a result, the count value of the n-ary counter 27 increases by one. Shift Max} The IJxes 29 and 30 have a shift amount equal to that of the n-ary counter 2.
Since it is determined by the control signal k, which is the output count value of the n-ary counter 27, when the count value of the n-ary counter 27 increases by one, input data shifted by one bit from the previous input data is output. When the frame pulse F2 generated at the output f of the exclusive NOR circuit l9 appears, the gate circuit 18 becomes inhibited, and the count-up pulse h disappears.
The counting operation of the n-ary counter 27 is stopped and word synchronization is restored. When the word synchronization is restored, the recovered frame pulse appears in circulation at the output f1 of the exclusive NOR circuit 19. When this synchronization return state is repeated for the number of backward protection stages (twice in this case), the protection circuit 24 is reset and the output g1 becomes "0". As a result, word synchronization is established.

7 L/-m counter 23 is driven by word pulse a to F corresponding to frame pulse. -F, is repeatedly sent as output p. However, the frame counter 23
The output p is F. When , exclusive NOR circuit 1
The output f1 of 9 is F. otherwise, gate circuit 2
1 indicates a mismatch, and the frame counter 2 starts from the next word.
Since the drive pulse p of 3 is prohibited, the output p of the frame counter 23 is fixed at F0. This is then applied to the output of the exclusive NOR circuit 19. This signal continues until F is generated. The frame counter 23 enters the driving state at the next word. Frame synchronization is restored in this state.

When frame synchronization is established, the protection circuit 24
continues to be in the reset state and its output g continues to be "0". Therefore, the gate circuit 18 continues to be in the prohibited state and resynchronization operation is prohibited.

In this embodiment circuit, there is no need to cause the word synchronization circuit to perform resynchronization each time the frame synchronization circuit performs resynchronization. In other words, the word synchronization by the n-ary counter 27 has returned to synchronization, and the frame pattern appears correctly in the output f1 of the exclusive NOR circuit 19, but the frame pattern of this output and the frame sent by the frame counter 23 are different. When the patterns do not match, the delay circuit 22 and the gate circuit 20 operate in accordance with the output of the gate circuit 21.
The phase of the frame counter 23 can be changed independently of word synchronization. At this time, word synchronization does not perform a resynchronization operation. Therefore, the time required for the entire resynchronization operation is shortened compared to the conventional circuit shown in FIG.

Next, considering the degree of this shortening, when one frame has an m-word configuration and one word has an n-bit configuration, and if the probability of pattern mismatch detection in an asynchronous state is 2, then the The maximum time T required for the example circuit to return to synchronization from an asynchronous state is the worst average word synchronization return time Tw from an asynchronous state to word synchronization return and the worst case time T from word synchronization return to frame synchronization return. , ("worst" means the case where the timing happens to be the most time-consuming).

Regarding rvjTV at the time of word synchronization recovery, the word synchronization counter corresponds to an immediate shift of 1 bit, so T+=(n+n)(n- 1)/n (1
) word. This calculation formula is described in detail in Kozuka, "Transmission Characteristics of Staff Synchronization Method," Research and Practical Application Report, Vol. 18, No. 6, Published by Nippon Telegraph and Telephone Public Corporation, June 1969, and other publications, so the explanation will be omitted here. The worst time Tt required for frame synchronization recovery is the case where the word synchronization recovery point just hits the counter value F1 of the frame counter 23, and it takes about one frame until the next value of the frame counter 23 reaches F0. time, then F to the input frame pattern. Approximately one additional frame is required for this to appear, so the total time is approximately two frames. Therefore, when m=72 and n=9 as practical values, '
L=T. +Tr=16 words+2 frames ζ2.2 frames. As a comparative example, in the conventional example shown in FIG. 8, word synchronization is resynchronized every time the frame patterns become inconsistent, so the worst time until the entire synchronization is restored is T0.
According to the above-mentioned document, To=(n+1 +n)(
mn − 1)/mn (2) frame. Substituting the above case of m=72 and n=9 into this, we get T. =19 frames. That is, compared to the worst case time, the effect of this embodiment is that the time from an asynchronous state to a synchronous state is shortened to only 11.6%.

In this embodiment circuit, the serial/parallel converter 10 and the frame synchronization circuit are completely separated, and the frame synchronization circuit operates with a clock that is 1/n of the input clock input to the terminal 12. Furthermore, since the serial-to-parallel converter lO, which requires high-speed operation, does not have a loopback loop, the serial-to-parallel converter 10
It is possible to operate the circuit element to its operating limit. Therefore, the circuit of this embodiment is suitable for a frame synchronization circuit for ultra-high-speed input signals.

FIG. 3 is a block diagram of a circuit according to a second embodiment of the present invention.

In this embodiment circuit, as in the first embodiment shown in FIG. 1, the word synchronization circuit operates independently of the frame synchronization circuit.
Similar to the first embodiment, the synchronization recovery time is shortened compared to the conventional example.

The feature of this embodiment circuit is that the shift matrix 30 shown in FIG. 1 is removed and the input to the exclusive NOR circuit 19 is taken from the output of the shift matrix 29.

The operation of this embodiment circuit is the same as that shown in FIG. 1, and therefore the operating waveform at each point is also the same as that shown in FIG. 2. For this reason,
Maximum time required to return to synchronization from an asynchronous state r
I! JTI is also the same as in the first embodiment and is shortened.

FIG. 4 is a block diagram of a circuit according to a third embodiment of the present invention.

In this embodiment circuit, as in the first embodiment shown in FIG. 1, the word synchronization circuit operates independently of the frame synchronization circuit.
Similar to the first embodiment, the synchronization recovery time is shortened compared to the conventional example.

The features of this embodiment circuit include a delay circuit 31 whose input bit number is increased by one bit compared to the delay circuit 28 of FIG. 1, and a delay circuit which delays the output of the n-th bit of this delay circuit 31 by one word pulse clock. 32, and instead of the shift matrix 30 in FIG. 1, n bits of the output of the latch circuit 14, n bits of the output of the delay circuit 31, and
According to the control signal of the output of the n-ary counter 27, the bit where the C bit or C bit violation code bit should arrive, the bit immediately before it, and the C bit or A shift matrix that selects and outputs the C bit one word before the bit where the violation code T bit of the C bit should arrive or the bit where the violation code C bit of the C bit should arrive and the bit immediately before that bit. 33, and the exclusive NOR circuit 19 which takes the opposite logic of the exclusive OR of the C bit of the output of this shift matrix 33 or the violation code τ bit of the C bit and the bit immediately before it. An exclusive NOR circuit 34 that takes the opposite logic of the exclusive OR between two bits one word before the two bits input to the exclusive NOR circuit 19 of the output of the shift matrix 33; OR circuit 3 that ORs the outputs of NOR circuits 19 and 34
5.

This corresponds to a so-called multi-point monitoring system, and is in an asynchronous state. Therefore, when the output of the protection circuit 24 is "l", the output of at least one of the exclusive NOR circuits 19 and 34 is "l". Then, since a count-up pulse appears at the output of the gate circuit 18, the resynchronization operation of the word synchronization circuit becomes faster than in the first embodiment. Therefore, the word recovery time of this embodiment circuit is shorter than that of the first embodiment. The time from recovery of word synchronization to recovery of frame synchronization is the same as in the first embodiment.

In this embodiment circuit, the output of the exclusive NOR circuit 19 is given to one input of the gate circuit 21, but the output of the exclusive NOR circuit 34 may be given instead. Further, although the output of the exclusive NOR circuit 19 is given to the input of the protection circuit 24, the output of the exclusive NOR circuit 34 or the output of the OR circuit 35 may be given instead.

FIG. 5 is a block diagram of a circuit according to a fourth embodiment of the present invention.

In this embodiment circuit, as in the first embodiment shown in FIG. 1, the word synchronization circuit operates independently of the frame synchronization circuit.
Similar to the first embodiment, the synchronization recovery time is shortened compared to the conventional example.

The feature of this embodiment circuit is that, compared with the third embodiment shown in FIG. 4, the shift matrix 33 is removed and the shift matrix 29 is replaced with
Using the sum of the bit-th output bit and the output bit of the delay circuit 32 as input, n bits in word units and the bits 1 bit before and 2 bits before the n bits are input according to the control signal of the output of the n-ary counter 27. of bits (n+
2) A shift matrix 36 for selectively outputting bits is provided, and the input signals of the exclusive NOR circuits 19 and 34 are provided from the output of the shift matrix 36.

This embodiment circuit also corresponds to a so-called multi-point monitoring system, and its operation and characteristics are the same as the third embodiment shown in FIG. Therefore, the manner in which input signals are applied to the gate circuit 21 and the protection circuit 24 is also the same.

By the way, in the first to fourth embodiments, although resynchronization is executed in this way and the time until synchronization is restored can be shortened, the protection circuit 24 is still not reset after synchronization is restored. If the frame pattern "1" happens to appear at the output of the exclusive NOR circuit 19 before the word synchronization is established, the word synchronization will execute a resynchronization operation. To avoid this,
The following condition is required between the number of words m in one frame, the number n of bits in one word, and the number l of backward protection stages of the protection circuit 24: mn>(n+n)(n-1)+ln (3).

Equation (3) is the condition for the first and second embodiments.

In the third and fourth embodiments, the word synchronization recovery time is shorter than in the first and second embodiments, so this condition is less strict.

The left side of equation (3) is one frame time, the first term on the right side is the word synchronization recovery time expressed in the number of bits given by equation (1), and the second term is protection by backward protection operation after word synchronization recovery. This is the time until the circuit 24 is reset.

On the other hand, the number of backward protection stages l of the protection circuit should be determined based on how many times the synchronization state must be detected to establish the synchronization state in order to avoid false synchronization establishment.This value is determined by Otake et al. "Practical Application of Equipment" Research and Practical Application Report published by Nippon Telegraph and Telephone Public Corporation, Vol. 25, No. 1, 19
Using the results of the study in 76, it is said that when the probability of matching detection is q, the following is appropriate. As a practical numerical value, if the false synchronization risk rate ρh is 1%, the coincidence detection probability q is 0.5, and n=17 as an example, l≧11 can be found from the above equation (4). If l=11, then the value of m that satisfies equation (3) will be 43 or more, and it can be seen that frame synchronization cannot be recovered if a frame with a word count less than 43 is used. In other words, in relation to the number l of backward protection stages of the protection circuit 24, there is a constraint between the number m of words in one frame and the number n of bits in one word.

A circuit improved from this is a circuit according to a fifth embodiment of the present invention shown in FIG.

The features of this embodiment circuit are as follows in the third embodiment shown in FIG.
The difference is that an AND circuit 37 is used instead of an OR circuit 35. This allows two adjacent words one word apart from each other to
Since the opposite logic of the exclusive OR of the bits is detected by the exclusive NOR circuits 19 and 34, and the logical product thereof is taken by the AND circuit 37, the output of the exclusive NOR circuit 19 contains the frame pattern. Even if “1” is generated, the output of the exclusive NOR circuit 34 is “1” of the frame pattern.
0" is generated, the output of the AND circuit 37 is "0".
Therefore, no count-up pulse is generated at the output of the gate circuit 18.

Therefore, in the circuit of this embodiment, after the word recovery, in a state where the protection circuit 24 has not yet entered the backward protection operation, that is, in a state where its output is "L", the frame pattern is applied to the output of the exclusive NOR circuit 19. Even if "l" is generated, the word synchronization circuit no longer starts resynchronization operation, and in relation to the number of backward protection stages l of the protection circuit 24, the number of words m in one frame and the bits of l words number n
There are no conflicts between the two that would make it impossible to perform synchronous operations under certain conditions.

FIG. 7 is a block diagram of a circuit according to a sixth embodiment of the present invention. This embodiment circuit is another circuit that compensates for the drawbacks of the first to fourth embodiment circuits described above.

The characteristics of this embodiment circuit are as follows in the fourth embodiment shown in FIG.
The difference is that an AND circuit 37 is used instead of an OR circuit 35. This effect is similar to that shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, since the word synchronization circuit does not execute a resynchronization operation every time a resynchronization operation is performed regarding the frame synchronization circuit, it takes a long time to return to synchronization from an asynchronous state. It has the effect of significantly shortening the length.

Furthermore, in the invention according to claims 3 and 4, in addition to the above-mentioned effects, specific constraint conditions are set between the number of words in a frame and the number of bits in a word in relation to the number of backward protection stages of the protection circuit. There is no need to provide this, which has the effect of allowing a greater degree of freedom in design.

Further, according to the present invention, the frame synchronization circuit is separated from the serial-to-parallel converter, which requires high-speed operation, and can be realized with a low-speed circuit.Furthermore, since there is no loopback loop in the serial-to-parallel converter, the operation of the control circuit elements is improved. Since the speed can be increased to the limit, it has the effect of being suitable for frame synchronization circuits for ultra-high-speed input signals. In addition to the method shown in the example, there are various ways to implement the serial-to-parallel converter circuit, such as realizing it in the optical circuit area, so being able to separate the serial-to-parallel converter and the frame synchronization circuit has the effect of increasing the degree of freedom in design. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit according to a first embodiment of the present invention. FIG. 2 is an operation time chart of the circuit of the first embodiment. FIG. 3 is a block diagram of a circuit according to a second embodiment of the present invention. FIG. 4 is a block diagram of a circuit according to a third embodiment of the present invention. FIG. 5 is a block diagram of a circuit according to a fourth embodiment of the present invention. FIG. 6 is a block diagram of a circuit according to a fifth embodiment of the present invention. FIG. 7 is a block diagram of a circuit according to a sixth embodiment of the present invention. FIG. 8 is a block diagram of a conventional circuit. 9... High-speed circuit section, 10... Serial-to-parallel conversion section, 11,
12...terminal, 13...shift register, 14...
・Latch circuit, 15...Ring counter, 16, 18
, 20, 26... gate circuit, 17, 22, 25, 2
8, 31, 32... Delay circuit, 19, 34... Exclusive NOR circuit, 21... Frame coincidence detection circuit,
23... Frame counter, 24... Protection circuit, 2
7...N-ary counter, 29, 30, 33, 36...
Shift matrix, 35... OR circuit, 37...
AND circuit.

Claims (1)

[Claims] 1. The c bit at a specific position in each word of m-1 words in one frame is set to the opposite logical value of the b bit before or after the c bit, and the remaining Serial data (mB1C code data) consisting of m words in one frame in which the c bit at a specific position in one word has the same logical value as the b bit before or after the c bit is 1 word long n In a frame synchronization circuit equipped with a serial-to-parallel conversion means (13, 14, 15) for serial-to-parallel conversion into parallel data of bits, an n-ary counter ( 27); a frame counter (23) that generates a frame pattern driven by the clock of the parallel data; and a frame counter (23) for generating a frame pattern driven by the clock of the parallel data; A first delay means (28) for delaying is inputted with n bits of the parallel data and an n-th bit of the output of the first delay means, and according to a control signal of the output of the n-ary counter, the c First output selection means (30
), and a second input circuit that inputs n bits of the parallel data and n-1 bits of the output of the first delay means, and selects and outputs n bits of each word according to a control signal of the output of the n-ary counter. a second output selection means (29); a first logic circuit (19) that takes the opposite logic of the exclusive OR between the two bits of the output of the first output selection means; a frame coincidence detection circuit (21) for detecting a mismatch between the output and the output of the frame counter;
and means for temporarily inhibiting the counting operation of the frame counter to achieve frame synchronization when the frame coincidence detection circuit detects a mismatch; a word asynchronous detection circuit (18) to detect; a means for incrementing the count value of the n-ary counter by one based on the detection output of the word asynchronous detection circuit to achieve word synchronization in addition to frame synchronization; , a protection circuit (24) that prohibits the operation of the word synchronization means unless the output logic value of the first logic circuit becomes "1" several times in succession;
A frame synchronization circuit characterized by comprising: 2. Set the c bit at a specific position in each word of m-1 words in one frame to the opposite logical value of the b bit before or after the c bit, and set the c bit at a specific position in the remaining one word. Converts serial data (mB1C code data) consisting of m words in one frame into parallel data with a word length of n bits, where the c bit of is the same as the b bit before or after the c bit. A frame synchronization circuit comprising serial-to-parallel conversion means (13, 14, 15) for serial-to-parallel conversion, comprising: an n-ary counter (27) driven by the clock of the parallel data and outputting its count value as a control signal; a frame counter (23) that generates a frame pattern driven by a clock of parallel data; and a first frame counter that delays each bit from the second bit to the nth bit of the parallel data by one clock of the clock of the serial data. inputting n bits of the parallel data and n-1 bits of the output of the first delay means to a delay means (28), and according to a control signal of the output of the n-ary counter,
a second output selection means (29) for selectively outputting n bits in word units; and exclusion of the bit where the c bit should arrive and the bit where the b bit should arrive in the output of the second output selection means. a first logic circuit (19) that takes the opposite logic of the logical OR, and a frame coincidence detection circuit (21) that detects a mismatch between the output of this first logic circuit and the output of the frame counter.
and means for temporarily inhibiting the counting operation of the frame counter to achieve frame synchronization when the frame coincidence detection circuit detects a mismatch; a word asynchronous detection circuit (18) to detect; a means for incrementing the count value of the n-ary counter by one based on the detection output of the word asynchronous detection circuit to achieve word synchronization in addition to frame synchronization; , a protection circuit (24) that prohibits the operation of the word synchronization means unless the output logic value of the first logic circuit becomes "1" several times in succession;
A frame synchronization circuit characterized by comprising: 3. Set the c bit at a specific position in each word of m-1 words in one frame to the opposite logical value of the b bit before or after the c bit, and set the c bit at a specific position in the remaining one word. Converts serial data (mB1C code data) consisting of m words in one frame into parallel data with a word length of n bits, where the c bit of is the same as the b bit before or after the c bit. A frame synchronization circuit comprising serial-to-parallel conversion means (13, 14, 15) for serial-to-parallel conversion, comprising: an n-ary counter (27) driven by the clock of the parallel data and outputting its count value as a control signal; a frame counter (23) that generates a frame pattern driven by a parallel data clock; and a second delay means (31) that delays each of the n bits of the parallel data by one clock of the serial data clock.
), and a third delay means (
32), inputting n bits of the parallel data, n bits of the output of the second delay means, and 1 bit of the output of the third delay means, and according to the control signal of the output of the n-ary counter. , the d bit to which the c bit should arrive, the e bit to which the b bit should arrive, the f bit which is one word away from the d bit and where the c bit should arrive, and the b bit which is one word away from the e bit. a third output selection means (33) for selectively outputting g bits to arrive;
Input n-1 bits from bit to nth bit,
a second output selection means for selectively outputting n bits in a word unit according to a control signal of the output of the n-ary counter;
29), a first logic circuit (19) that takes the opposite logic of the exclusive OR of the d bit and the e bit of the output of the third output selection means; The f bits of the output and the g
a second logic circuit (34) that takes the opposite logic of exclusive OR with the bit; and a frame coincidence detection circuit (34) that detects a mismatch between the outputs of the first and second logic circuits and the output of the frame counter. 21), and when this frame match detection circuit detects a mismatch,
means for temporarily inhibiting the counting operation of the frame counter to achieve frame synchronization; a third logic circuit (35, 37) for calculating the OR or AND of the outputs of the first and second logic circuits; A word asynchronous detection circuit (18) detects that the output logical value of the third logic circuit is "1", and the count value of the n-ary counter is incremented by one based on the detection output of this word asynchronous detection circuit, and a frame is generated. means for achieving word synchronization in addition to synchronization, and when in the word synchronization state, the output logic value of the first logic circuit, the second logic circuit, or the third logic circuit becomes "1" a plurality of times in succession; A frame synchronization circuit characterized in that it is equipped with a protection circuit (24) that prohibits the operation of means for synchronizing words unless the following conditions occur. 4. Set the c bit at a specific position in each word of m-1 words in one frame to the opposite logical value of the b bit before or after the c bit, and set the c bit at a specific position in the remaining one word. Serial data (mB1C code data) consisting of m words in one frame where the c bit of is set to the same logical value as the b bit before or after the c bit is converted into parallel data with a word length of n bits. A frame synchronization circuit equipped with serial-to-parallel conversion means for parallel conversion, comprising: an n-ary counter (27) driven by the clock of the parallel data and outputting its count value as a control signal; a frame counter (23) that generates a frame pattern; and a second delay means (31) that delays each of the n bits of the parallel data by one clock of the serial data clock.
), and a third delay means (
32), inputting n bits of the parallel data, n bits of the output of the second delay means, and 1 bit of the output of the third delay means, and according to the control signal of the output of the n-ary counter,
a fourth output selection means (36) for selectively outputting n bits in word units, a bit 1 bit before the n bits, and a bit 2 bits before the n bits; and the c bit of the output of the fourth output selection means. a first logic circuit (19) that takes the opposite logic of the exclusive OR of the d bit from which the b bit should arrive and the e bit from which the b bit should arrive;
and exclusive logic between the bit where the c bit which is one word away from the d bit of the output of the fourth output selection means should arrive and the bit where the b bit which is one word away from the e bit should arrive. A second logic circuit that takes the opposite logic of sum (
34); a frame coincidence detection circuit (21) that detects a mismatch between the outputs of the first and second logic circuits and the output of the frame counter; means for temporarily inhibiting the counting operation of the counter to achieve frame synchronization; a third logic circuit (35, 37) for calculating the logical sum or logical product of the outputs of the first and second logic circuits; A word asynchronous detection circuit (18) detects that the output logical value of the logic circuit is "1", and the detected output of this word asynchronous detection circuit increments the counted value of the n-ary counter by one to establish frame synchronization. means for separately synchronizing words, and when in the word synchronization state, the output logic value of the first logic circuit, the second logic circuit, or the third logic circuit becomes "1" several times in succession; A frame synchronization circuit characterized in that it comprises a protection circuit (24) for inhibiting the operation of means for synchronizing words unless the synchronization occurs.