JPH0329436A - Frame synchronization circuit - Google Patents

Abstract

PURPOSE:To reduce the time from the asynchronizing state till the synchronization restoration by avoiding a word synchronization from executing resynchronization every execution of resynchronization by a frame synchronizing circuit. CONSTITUTION:When the circuit executes the resynchronization from an asynchronous state, the word synchronization by a ring counter 15 is executed independently of the frame synchronization by a frame counter 23 in the timing when logical 1 appears at the output of an exclusive NOR circuit 19. The frame synchronization by the frame counter 23 is executed when dissidence appears at the detection output of a frame coincidence detection circuit 21 and the resynchronization of the frame synchronization is executed by revising the phase of the frame counter 23 independently. That is, even when the dissidence of the frame pattern is detected by the frame synchronization circuit, the phase of the frame counter 23 is changed without giving effect onto the word synchronization. Thus, the time till the synchronization establishment is reduced as a whole.

Description

[Detailed description of the invention] [Industrial application field] The present invention is used in digital communications.

INDUSTRIAL APPLICABILITY The present invention is used for frame synchronization of a backbone transmission system, a public communication network, a subscriber system, and other digital transmission systems.

The present invention is based on the mB
Used for frame synchronization based on IC code violations.

[Conventional technology]

When transmitting a series of digital signals using a frame structure, one frame has a structure of m words, and one word consists of n-1 bits of data and a 1-bit C code (complementary code) or the opposite of the complementary code. When the n-bit structure consists of a code, one bit at a specific position in each word of m-1 words in one frame is the complementary code (C bit), and the bit at a specific position within the remaining word has the same code as the bit before or after that bit (referred to as C-bit violation code τ). A method is known in which frame synchronization is achieved by transmitting a frame and identifying the timing at which the C-bit violation code arrives as the frame synchronization timing.

FIG. 8 is a block diagram of a conventional circuit for this purpose. When the number of words in one frame is m words, this circuit is a series circuit in which m-1 C bits and 1 C-bit violation code are distributed in one bit each. This is a circuit that inputs data and performs frame synchronization.

The circuit shown in FIG. 8 includes a shift register 13 that converts serial data input to a terminal 11 into parallel data, and a terminal 12.
a ring counter 15 that is driven by the clock of the serial data inputted to the input terminal and generates a word pulse; a latch circuit 14 that latches the contents of the shift register 13 using the word pulse; Exclusive OR circuit (EX-NOR circuit) 19 that takes the opposite logic of the exclusive OR of the bit where the violation code τ bit of C bisoto is to arrive and the bit immediately before that bit, and the word a frame counter 23 that generates a frame pattern every time, and a frame coincidence detection circuit 21 that detects a mismatch between the output of the exclusive NOR circuit 19 and the output of the frame counter 23.
The frame coincidence detection circuit 21 is configured to perform a resynchronization operation when the frame coincidence detection circuit 21 sends out a mismatch output.

In this circuit, the C bit is the complementary sign of the bit immediately before it (
opposite sign), and the C-bit violation code τ
It is assumed that a bit has the same sign as the bit immediately before it. Therefore, when in the synchronized state, a frame pattern appears at the output of the exclusive NOR circuit 19.

In the resynchronization operation, when an output is sent to the frame coincidence detection circuit 21, a signal is sent from the gate circuit 18 to the delay circuit 17 at the timing of the word pulse. The delay circuit 17 delays the signal by a timing of 2 clocks or more and 1 word or less, and sends it to the gate circuit I6, so that the counting operation of the ring counter 15 is missed by 1 clock, and the timing of word pulse generation is delayed. It will be done. This word pulse is given as a count input to the frame counter 23, and its output is sent to the frame coincidence detection circuit 21 at timings at which a preset frame pattern is distributed.

Therefore, when the word pulse generated from the ring counter 15 is generated at the correct timing and word synchronization is achieved, and the frame counter 23 is generating a frame pattern at the correct timing, it is a stable synchronization state and frame coincidence is detected. There is no signal at the output of circuit 21.

In a practical circuit, a frame synchronization protection circuit is inserted at the position indicated by the symbol X in the lower right corner of FIG. It is configured not to perform resynchronization.

Here, in order to avoid complicating the explanation, the frame synchronization protection circuit at the position of symbol X will be omitted from the explanation.

[Problem to be solved by the invention]

This circuit is an excellent circuit that detects a frame pattern arranged in a divided manner and synchronizes the frame, but in order to establish synchronization from an asynchronous state, first the ring counter 1
5 is restored, and the frame counter 23 executes the frame synchronization operation. However, when a mismatch between the frame pattern sent from the frame counter 23 and the output of the exclusive NOR circuit 19 is detected, the A resynchronization operation of the ring counter 15 is performed each time. Therefore, even if word synchronization is restored for each mismatch of frame patterns, the word synchronization operation and the frame synchronization operation are executed by the ring counter 15, which has the disadvantage that the resynchronization operation takes time.

The present invention improves this and aims to shorten the time required for the resynchronization operation.

[Means to solve the problem]

In the circuit of the present invention, in addition to the frame coincidence detection circuit (21), the output of the exclusive NOT logic circuit (19) is set to the opposite logic value (
In accordance with the conventional example described above, a word asynchronous detection circuit (18) is provided to detect the logic "1"), and the detection output of this word asynchronous detection circuit temporarily inhibits the counting operation of the ring counter to synchronize the frame. It is characterized by having means for synchronizing words independently of the .

[Effect]

When a circuit performs a resynchronization operation from an asynchronous state,
Word synchronization by the ring counter (15) is performed independently of frame synchronization by the frame counter (23) at the timing when logic "1" appears at the output of the exclusive NOR circuit (19). Frame counter (23)
Frame synchronization is performed by the frame coincidence detection circuit (21)
When a mismatch appears in the detected output of Even if detected,
The phase of the frame counter (23) can be changed each time without affecting the word synchronization.

This occurs when the word synchronization is correct but the frame synchronization is not, i.e. the frame synchronization circuit is correctly looking at the bits where the frame pattern should appear, but
The frame pattern appearing in the pit and the frame pattern generated by the frame counter (23) are different from each other, and it is extremely effective to enter a synchronized state by changing the phase of the frame counter.

In this way, the overall time required to establish synchronization can be shortened.

〔Example〕

FIG. 1 is a block diagram of a circuit according to a first embodiment of the present invention.

In this example circuit, when the number of words in one frame is m words, m-1 C bits and 1 C bit violation code bit are distributed one bit at a time in one frame. This is a circuit for inputting arranged serial data and synchronizing frames. Here, the C bit is the complementary code of the bit immediately before the bit, and the τ bit is the same code as the bit immediately before that bit. Table 1 shows an example of input data.

Input serial data arrives at terminal 11. This embodiment circuit includes a shift register 13 that converts the serial data into parallel data, a ring counter 15 that is driven by the clock of this serial data and generates a word pulse, and a latch that latches the contents of the shift register 13 using the word pulse. circuit 14; and an exclusive NOR circuit 19 that takes the opposite logic of the exclusive OR of the bit where the C bit or τ bit is to arrive and the bit immediately before that bit among the bits of the latch circuit 14; a frame counter 23 that generates bits of the same series as each bit of the frame pattern that should appear in the output of the exclusive NOR circuit 19;
Output of exclusive NOR circuit 19 and frame counter 2
The frame matching detection circuit 21 detects matching or mismatching with the output of No. 3.

Here, the feature of the circuit of the present invention is that the frame synchronization by the frame counter 23 and the word synchronization by the ring counter 15 are configured so that resynchronization operations can be executed independently.

That is, a delay circuit 22 and a gate circuit 20 are provided as means for temporarily inhibiting the counting operation of the frame counter 23 and resynchronizing frame synchronization when the frame coincidence detection circuit 21 detects a mismatch. Also,
Separately from this frame coincidence detection circuit 21, a gate circuit 18 is provided as a word asynchronous detection circuit for detecting the appearance of a logical value "1" in the output of the exclusive NOR circuit 19. A delay circuit 17 and a gate circuit 16 are provided as a means for temporarily inhibiting the counting operation of the ring counter 15 and achieving word synchronization in addition to frame synchronization based on the output.

In addition, in this embodiment circuit, in the word synchronization established state, the gate circuit operates only when the logic value "1" is detected over a plurality of consecutive words in the output of the exclusive NOR circuit l9. When 18 is enabled and word synchronization is not established, the gate circuit 18 is disabled only when a logic value "0" is detected in the output of the exclusive NOR circuit 19 over a plurality of consecutive words (backward protection). A protection circuit 24 is provided.

In a practical circuit, it is recommended to insert a frame synchronization protection circuit at the position indicated by symbol X in the lower right corner of Figure 1 in order to maintain stable frame synchronization, but this is omitted here as the explanation will be complicated. do. Note that this also applies to FIGS. 3, 4, and 7, which will be described later.

FIG. 2 is an operation time chart of this first embodiment circuit. Symbols in FIG. 2 as bs dl Sd2, e-k,
p and q indicate the waveforms of points with corresponding symbols shown in FIG. As an example to simplify the explanation, 1 word is 3
bits (n=3), ■ frame is 5 words (m=5
), an example of input serial data is shown in Table 1. Also table l
The frame pattern generated by the exclusive NOR circuit 19 is also shown.

Fo FI F2 F3 F4 becomes 10000 in order. Further, the number of backward protection stages of the protection circuit 24 is assumed to be two for the sake of simplicity.

Table 1 D...data, C, ~C,...C bit, co...
・Violation code τ bit of C bit, F...
Frame patterns F0 to F4 repeatedly appear in order at the output j of the frame pulse frame counter 23. In a state where synchronization is not established, the output f of the protection circuit 24 is "
1”. At this time, a resynchronization operation is executed and a hunting pulse g is sent out from the gate circuit 1B. As a result, the drive pulse 1 of the ring counter 15 is thinned out,
The phase of the ring counter 15 shifts. The frame pulse F generated at the output e of the exclusive NOR circuit 19,
When the gate circuit 18 appears, the gate circuit 18 becomes inhibited, the hunting pulse g disappears, and the word synchronization is restored.

When the word synchronization is restored, the generated frame pulse appears in circulation at the output e of the exclusive NOR circuit 19.

When this synchronization return state is repeated for the number of backward protection stages (twice here), the protection circuit 24 is reset and the output f becomes "0". As a result, word synchronization is established.

The frame counter 23 is driven by the word pulse b to the output j and repeatedly sends out F0 to F corresponding to the frame pulse. However, the output J of the frame counter 23
is F. When the output e of the exclusive NOR circuit 19 is other than F0, the frame coincidence detection circuit 2
1 indicates a mismatch, and the frame counter 2 starts from the next word.
Since the drive pulse q of 3 is prohibited, the output j of the frame counter 23 is F. is fixed. This is then F to the output e of the exclusive NOR circuit 19. This continues until F0 is generated, and at the next word when this signal becomes F0, the frame counter 23 enters the driving state. Frame synchronization is restored in this state.

When frame synchronization is established, the protection circuit 24
continues to be in the reset state and its output f continues to be "0". Therefore, the gate circuit 18 continues to be in the prohibited state and resynchronization operation is prohibited.

In this embodiment circuit, there is no need to cause the word synchronization circuit to perform resynchronization each time the frame synchronization circuit performs resynchronization. In other words, the word synchronization by the ring counter 15 has returned to synchronization, and the frame pattern appears correctly in the output e of the exclusive NOR circuit 19, but the frame pattern of this output e and the output sent out by the frame counter 23 When the frame pattern of J does not match, the phase of the frame counter 23 is changed independently of word synchronization by the operation of the delay circuit 22 and gate circuit 20 according to the output k of the frame match detection circuit 21. I can do it.

At this time, word synchronization does not perform a resynchronization operation.

Therefore, the time required for the entire resynchronization operation is shortened compared to the conventional circuit shown in FIG.

Next, consider the degree of this shortening. ■Frame is m
When a word structure is used and one word is composed of n bits, and the probability of pattern mismatch detection in an asynchronous state is 2, the time required for the circuit of the first embodiment shown in Fig. 1 to return to synchronization from an asynchronous state is The maximum required time T1 is the sum of the worst average word synchronization recovery time Tw from an asynchronous state to word synchronization recovery and the worst time Tf from word synchronization recovery to frame synchronization recovery ("worst" coincidentally means the longest time (This refers to the case where such timing occurs.) Regarding the word synchronization return time TW, since the word synchronization counter corresponds to a 1-bit delay shift, T+ = (n+ 1 + n) (n - 1)/n
(1) It is a word. This calculation formula is described in detail in Kozuka's "Transmission Characteristics of Staff Synchronization Method" Research and Practical Application Report, Vol. 18, No. 6, Published by Nippon Telegraph and Telephone Public Corporation, ■June 1969, and other publications, so the explanation will be omitted here. The worst time Tf required for frame synchronization recovery is the case where the word synchronization recovery point just hits the counter value F1 of the frame counter 23, and it takes approximately one frame until the next value of the frame counter 23 reaches F0. time, then F to the input frame pattern.

Approximately one additional frame is required for this to appear, so the total time is approximately two frames. Therefore, in the case of m-72 and n=9 as practical values,
T+=Tw+Tr=17 words+2 frames z2.2 frames. As a comparative example, in the conventional example shown in FIG. 8, word synchronization is resynchronized every time the frame patterns become inconsistent, so the worst case period is T until the overall synchronization is restored.

According to the above-mentioned document, To=(n+ 1 +n)
(mn = 1)/mn (2) frame. Substituting the above case of m=72 and n=9 into this, we get T. =19 frames. That is, compared to the worst case time, the effect of this embodiment is that the time from an asynchronous state to a synchronous state is shortened to only 11.6%.

FIG. 3 is a block diagram of a circuit according to a second embodiment of the present invention.

In this embodiment circuit, the word synchronization circuit operates independently of the frame synchronization circuit as in the first embodiment shown in FIG. The feature of this embodiment circuit is that the number of stages of the shift register 13 and latch circuit 14 is two stages larger than one word (n stages), so that the C bit or the τ bit of the violation code of the C bit is the bit that should arrive. Separately from the first exclusive NOR circuit 19 which takes the opposite logic of the exclusive OR with the previous bit, the C bit or A second exclusive NOR circuit 25 is provided which takes the opposite logic of the exclusive OR between the bit where the τ bit is to arrive and the bit immediately before that bit, and further includes an exclusive NOR circuit l9.
This is because an OR circuit 26 is provided to OR the outputs of and 25.

This corresponds to a so-called multi-point monitoring system, and is in an asynchronous state. Therefore, when the output of the protection circuit 24 is "1", the output of at least one of the exclusive NOR circuits 19 and 25 is "l". In this case, a hunting pulse appears at the output of the gate circuit 18, so that the resynchronization operation of the word synchronization circuit becomes faster than in the first embodiment. Therefore, the word recovery time of this embodiment circuit is shorter than that of the first embodiment.

The time from recovery of word synchronization to recovery of frame synchronization is the same as in the first embodiment.

Note that in this embodiment circuit, the frame coincidence detection circuit 21
Although the output of the exclusive NOR circuit 19 is given to one input of the , the output of the exclusive NOR circuit 25 may also be given. Furthermore, in FIG. 3, the output of the exclusive NOR circuit 19 is given to the input of the protection circuit 24;
This may provide the output of the exclusive NOR circuit 25 or the output of the OR circuit 26.

By the way, in the first embodiment and the second embodiment, it is possible to shorten the time until the resynchronization is executed and the synchronization is restored in this way, but after the synchronization is restored, the protection circuit 24
If the frame pattern "1" happens to appear at the output of the exclusive NOR circuit 19 before the word synchronization is yet reset, that is, before the word synchronization is established, the word synchronization will execute a resynchronization operation. To avoid this, mn>(n+1
+n)(n-1)+Jn (3) The following condition is required. Equation (3) is a condition for the first embodiment. In the second embodiment, the word synchronization recovery time is shorter than in the first embodiment, so this condition is less strict.

The left side of equation (3) is one frame time, the first term on the right side is the word synchronization recovery time expressed in the number of bits given by equation (1), and the second term is protection by backward protection operation after word synchronization recovery. This is the time until the circuit 24 is reset.

On the other hand, the number of backward protection stages l of the protection circuit should be determined based on how many times the synchronization state must be detected to establish the synchronization state in order to avoid false synchronization establishment.This value is determined by Otake et al. "Practical Application of Equipment" Research and Practical Application Report published by Nippon Telegraph and Telephone Public Corporation, Vol. 25, No. 1, 19
Using the results of the study in 76, the probability of matching detection is q. It is considered appropriate to set the false synchronization risk rate to ρ, and the number of bits in one word to n. As practical values, the false synchronization risk rate is 1%, and the coincidence detection probability is q.

Assuming that 0.5 and n=17 as an example, l≧11 can be found from the above equation (4). If l=11, then the value of m that satisfies equation (3) will be 44 or more, and it can be seen that frame synchronization cannot be recovered if a frame with a word count less than 44 is used. In other words, in relation to the number l of backward protection stages of the protection circuit 24, there is a constraint between the number m of words in one frame and the number n of bits in one word.

A circuit improved from this is a circuit according to a third embodiment of the present invention shown in FIG. This embodiment circuit is an exclusive NOR circuit 1
A mismatch detection circuit is provided for detecting that the logic value "1" has arrived twice in a row at the output of the circuit 9. That is, the exclusive NOR circuit 19 is connected to one side of the AND circuit 27.
The current value of the output of the AND circuit 27 is given to the other side of the AND circuit 27.
The value of the output of 9 is held in a flip-flop 28 and provided.

The output of the AND circuit 27 is supplied to the gate circuit 18 to temporarily inhibit the counting operation of the ring counter 15, thereby providing word synchronization in addition to frame synchronization.

Furthermore, this word synchronization means is such that even if the logic value "1" arrives twice in succession at the output of the exclusive NOR circuit 19, the current synchronization determination position temporarily prohibits the counting operation of the ring counter 15. At the next synchronization determination position and at the time of detection of the first "1" of the two times, the C bit of the latch circuit l4 or the violation code C bit of the C bit is from the bit to which it should arrive and that bit. When the output of the exclusive NOR circuit 32 which takes the opposite logic of the exclusive OR with the bit after one bit is a logic value "0", execution of the resynchronization operation is prohibited. shall be.

That is, the sizes of the shift register 13 and latch circuit 14 are increased by 1 bit, and the exclusive NOR circuit 3 is
2, detects the opposite logic of the exclusive OR of two inputs shifted one bit later than the two inputs of the exclusive NOR circuit 32, which takes the opposite logic of the exclusive OR at the time of previous word synchronization detection. This was realized by the gate circuit 30, the flip-flop 29, and the gate circuit 31.

FIG. 5 shows an operation time chart of the circuit of the third embodiment. FIG. 6 shows an example of the input data of the third embodiment circuit, the word synchronization determination position, and the bits on which the AND circuit v427 detects the AND.

In this embodiment circuit, when a logic "1" appears twice in a row at the word synchronization determination position at the output e of the exclusive NOR circuit 19, the resynchronization operation is activated, but the current synchronization determination position is At the next synchronization determination position where the counting operation of the counter 15 is temporarily inhibited, and at the first of these two determination positions, the output e2 of the exclusive NOR circuit 32
In addition, when the frame pattern "0" is generated, there is no need to perform the resynchronization operation, so in this case, the execution of the resynchronization operation is prohibited. Therefore, protection circuit 2
"l" in the frame pattern before 4 starts protection operation.
is detected, the resynchronization operation is no longer started immediately, and the synchronization operation cannot be performed under certain conditions between the number of words in the frame m and the number of backward protection stages l of the protection circuit 24. There will be no contradiction.

FIG. 7 is a block diagram of a circuit according to a fourth embodiment of the present invention. This embodiment circuit is another circuit that compensates for the drawbacks of the first and second embodiments.

The features of this embodiment circuit are as follows in the second embodiment shown in FIG.
The difference is that an AND circuit 33 is used instead of the OR circuit 26. The exclusive NOR circuits 19 and 25 detect the opposite logic of the exclusive OR of two adjacent bits that are one word apart from each other, and the AND circuit 33 calculates the logical product. Even if the frame pattern “1” is generated at the output of the circuit 19, the frame pattern “0” is generated at the output of the exclusive NOR circuit 25, so the output of the AND circuit 33 is “1”. O”,
No hunting pulse is generated at the output of the gate circuit 18.

Therefore, in the circuit of this embodiment, in a state where the protection circuit 24 has not yet entered the backward protection operation after word recovery, that is, in a state where its output is "1", the output of the exclusive NOR circuit 19 is set to frame. Even if the pattern "1" is generated, the word synchronization circuit no longer starts resynchronization operation, and in relation to the number l of backward protection stages of the protection circuit 24, the number m of words in one frame and the number of words in one word are There is no contradiction with the number of bits n that would make it impossible to perform a synchronous operation under specific conditions.

〔Effect of the invention〕

As explained above, according to the present invention, since the word synchronization circuit does not execute a resynchronization operation every time a resynchronization operation is performed regarding the frame synchronization circuit, it takes a long time to return to synchronization from an asynchronous state. It has the effect of significantly shortening the length.

Furthermore, in the invention according to claims 2 and 3, in addition to the above-mentioned effects, a specific constraint condition is set between the number of words in a frame and the number of bits in a word in relation to the number of backward protection stages of the protection circuit. There is no need to provide this, which has the effect of allowing a greater degree of freedom in design.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit according to a first embodiment of the present invention. FIG. 2 is an operation time chart of the circuit of the first embodiment. FIG. 3 is a block diagram of a circuit according to a second embodiment of the present invention. FIG. 4 is a block diagram of a circuit according to a third embodiment of the present invention. FIG. 5 is an operation time chart of the third embodiment circuit. FIG. 6 is an explanatory diagram showing an example of input data of the third embodiment circuit. FIG. 7 is a block diagram of a circuit according to a fourth embodiment of the present invention. FIG. 8 is a block diagram of a conventional circuit. IL 12...Terminal, 13...Shift register, 1
4... Launch circuit, l5... Ring counter, 16
, l8, 20, 30, 31... gate circuit, 17, 2
2... Delay circuit, 19, 25, 32... Exclusive NOR circuit, 21... Frame coincidence detection circuit, 23...
...Frame counter, 24...Protection circuit, 26...
・OR circuit, 27, 33...AND circuit, 28, 2
9...Flip-flop.

Claims (1)

[Claims] 1. The c bit at a specific position in each word of m-1 words in one frame is set to the opposite logical value of the b bit before or after the c bit, and the remaining Input serial data (mB1C code data) consisting of 1 frame m words in which the c bit at a specific position in 1 word has the same logical value as the b bit before or after the c bit,
A shift register (13) that converts this serial data into parallel data, a ring counter (15) that generates a word pulse driven by the clock of the serial data, and a latch that latches the contents of the shift register using this word pulse. a circuit (14); a frame counter (23) for generating a frame pattern word by word; and the opposite of the exclusive OR of the bit where the c bit should arrive and the bit where the b bit of the latch circuit should arrive. A first logic circuit (19) that takes logic; a frame coincidence detection circuit (21) that detects a mismatch between the output of the first logic circuit and the output of the frame counter; and a frame coincidence detection circuit (21) that detects a mismatch. In the frame synchronization circuit, the frame synchronization circuit includes means for temporarily inhibiting the counting operation of the frame counter to achieve frame synchronization when a frame coincidence detection circuit is detected, in which the output logic value of the first logic circuit is a word asynchronization detection circuit (18) for detecting that the word asynchronous detection circuit (18) is "1"; When in the synchronized state, a protection circuit (24
) A frame synchronization circuit characterized by comprising: 2. Set the c bit at a specific position in each word of m-1 words in one frame to the opposite logical value of the b bit before or after the c bit, and set the c bit at a specific position in the remaining one word. Input serial data (mB1C code data) consisting of m words of 1 frame in which the c bit of is the same logical value as the b bit before or after the c bit,
A shift register (13) that converts this serial data into parallel data, a ring counter (15) that generates a word pulse driven by the clock of the serial data, and a latch that latches the contents of the shift register using this word pulse. a circuit (14); a frame counter (23) for generating a frame pattern word by word; and the opposite of the exclusive OR of the bit where the c bit should arrive and the bit where the b bit of the latch circuit should arrive. a first logic circuit (19) that takes logic; a frame coincidence detection circuit (21) that detects a mismatch between the output of the first logic circuit and the output of the frame counter; In the frame synchronization circuit, the frame synchronization circuit includes means for temporarily inhibiting counting operation of the frame counter to achieve frame synchronization, when the c bit of the latch circuit arrives one word away from the bit to which the c bit should arrive. The exponent bit and the b bit are one word away from the bit that should arrive.
a second logic circuit (25) that takes the opposite logic of the exclusive OR of the bit with the bit that should arrive; and, apart from the frame coincidence detection circuit, the first logic circuit and the second logic circuit; A word asynchronous detection circuit (18) is provided to detect that the output logic value of the circuit (26, 32) that takes the logical sum or logical product of is "1", and the detected output of this word asynchronous detection circuit (18) means for temporarily inhibiting the counting operation of the ring counter to achieve word synchronization separately from frame synchronization; and when in the word synchronization state, the first logic circuit, the second logic circuit, or the first logic circuit. and the second logic circuit, the protection circuit (24) prohibits the operation of the word synchronization means unless the output logic value of the circuit that takes the OR or AND of the logic circuit and the second logic circuit becomes "1" several times in succession. A frame synchronization circuit characterized by: 3. Set the c bit at a specific position in each word of m-1 words in one frame to the opposite logical value of the b bit before or after the c bit, and set the c bit at a specific position in the remaining one word. Input serial data (mB1C code data) consisting of m words of 1 frame in which the c bit of is the same logical value as the b bit before or after the c bit,
A shift register (13) that converts this serial data into parallel data, a ring counter (15) that generates a word pulse driven by the clock of the serial data, and a latch that latches the contents of the shift register using this word pulse. a circuit (14); a frame counter (23) that generates a frame pattern for each word; and an opposite logic of exclusive OR of the bit where the c bit should arrive and the bit where the b bit of the latch circuit should arrive. a first logic circuit (19) which detects a mismatch between the output of the first logic circuit and the output of the frame counter; a frame match detection circuit (21) that detects a mismatch between the output of the first logic circuit and the output of the frame counter; In the frame synchronization circuit, the c bit of the latch circuit is configured to synchronize the bit that should arrive and the b bit of the latch circuit to synchronize the frame by temporarily inhibiting the counting operation of the frame counter when A third logic circuit (3
2), separate from the frame coincidence detection circuit, a mismatch detection circuit (18, 27, 28) is provided for detecting that the output logic value of the first logic circuit is "1" twice in a row; Means is provided for temporarily inhibiting the counting operation of the ring counter based on the detection output of the mismatch detection circuit to achieve word synchronization in addition to frame synchronization, and the output logic value of the first logic circuit becomes "1" twice in a row.
Even if the current synchronization determination position is the next synchronization determination position where the counting operation of the ring counter is temporarily prohibited, and the first logical value of "1" among the two times is detected, When the output logic value of the third logic circuit is "0", means for inhibiting the operation of the word synchronization means (2)
9, 30, 31), and further, when in the word synchronization state, the operation of the means for synchronizing the word is prohibited unless the output logic value of the first logic circuit becomes "1" several times in succession. A frame synchronization circuit comprising a protection circuit (24).