JPH0720087B2 - Frame synchronization circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a frame synchronization circuit, and more particularly to a frame synchronization circuit for high-speed digital transmission.

[Prior Art] FIG. 4 shows, for example, the Institute of Electrical Communication, Japan, Vol. 43, No. 12, (Showa 35).
(December) "Synchronization method in time division multiplexing code transmission"
2 is a conventional example of a frame synchronization circuit called 1-bit shift type digital synchronization system shown in FIG. In FIG. 4, a bit synchronization circuit (1) for reproducing a timing signal from an input multiplex code sequence, a logic gate (2) for inhibiting an output clock of the bit synchronization circuit (1), and a logic gate (2) A line separation circuit (3) that counts output clock pulses to generate a pulse necessary for line separation, and a decoder circuit that separates an input multiplex code sequence into each line based on the output pulse of the line separation circuit (3) (4), and the AND gate (5) for generating the synchronization pattern generation clock by taking the frame synchronization line selection pulse which is one output of the line separation circuit (3) and the input clock of the line separation circuit (3). And the other AND gate (6) for ANDing the frame synchronization line selection pulse, the input multiplex code sequence, and the output of the AND gate (5) Sync pattern generator for generating a pattern (7)
And a non-coincidence circuit (8) that detects the non-coincidence by collating the synchronization pattern with the multiple code sequence input at the frame synchronization position, and a delay circuit (9) that appropriately delays the output of the non-coincidence circuit (8). The output of the delay circuit (9) inhibits the clock by 1 bit by the logic gate (2).

Next, the operation will be described. The transmitted multiple code sequence is bit-synchronized by the bit synchronization circuit (1) to generate a clock pulse. The clock pulse advances the line separation circuit composed of the counting circuit to generate a separation pulse for each line or each digit.

Further, the synchronous line selection pulse h0 output from the line separation circuit (3) selects the code at the synchronization point on the receiving side from the multiplex code sequence in the other AND gate (6), and the one AND gate (5) Then, the timing is taken by the clock to operate the synchronous pattern generator (7). The output of the synchronization pattern generator (7) is compared with the output of the other AND gate (6) in the non-coincidence circuit (8), and the two are always coincident with each other during normal synchronization, so that the normal operation is continued. When synchronization is lost due to noise or the like, the other AND gate (6) erroneously selects the code of another line, and the mismatch circuit (8) generates a pulse for each mismatch. This pulse passes through the 1-bit delay circuit (9), and the logic gate (2) inhibits the clock by 1 bit to shift the line separation circuit (3) by 1 bit. This shift process is repeated several times to restore the synchronized state.

[Problems to be Solved by the Invention] Since the conventional frame synchronization circuit has the above-described configuration, the transmission speed becomes high, and it is difficult to adjust the 1-bit delay circuit for transmission of several gigabits / second. Therefore, it is necessary to use a high-speed element when the clock is prohibited by 1 bit, resulting in a problem of increased cost.

The present invention has been made to solve the above problems, and 1-bit shift processing relating to frame synchronization is performed by using clocks of each line rate after demultiplexing, thereby facilitating frame synchronization in high-speed transmission. It is an object of the present invention to obtain a frame synchronization circuit that can be realized at a low cost as a whole.

[Means for Solving the Problems] A frame synchronization circuit according to the present invention is configured to generate a decoder pattern output after demultiplexing and another AND gate for inputting a synchronization line selection pulse, and a synchronization pattern generation having a clock width after demultiplexing. If a mismatch is detected by comparing the output of the synchronization pattern generator with the output of the other Ant gate, the D-flip-flop one stage before the last stage of the counter in the line separation circuit is reset. And a mismatch circuit that shifts the line separation circuit by 1 bit.

[Operation] According to the present invention, since all 1-bit shift processing is processing by a low speed separation line clock after demultiplexing, no delay circuit is required, and even if the transmission speed is high, the frame synchronization is performed. It is possible to easily realize the circuit and configure the circuit with inexpensive elements.

[Embodiment] Next, the present invention will be described in more detail based on an embodiment shown in FIGS. 1 to 3.

In FIG. 1, a bit synchronization circuit (1) for regenerating a clock from a multiple code sequence, a line separation circuit (10) for generating a separation pulse, a low speed line clock, and a synchronization line selection pulse based on this clock, A decoder circuit (4) that separates the multiple code sequence into each line based on the separation pulse from the line separation circuit (10) and a synchronous line selection pulse generated by the line separation circuit (10) as a low-speed line clock. One AND gate (5) that has a retiming function in synchronization with the other AND gate (6) that takes the logical sum of the data of the specific channel and the synchronization line selection pulse after separating the multiple code sequence, and the AND gate By the output of (5),
A synchronization pattern generator (7) for generating a synchronization pattern,
Output of AND gate (6) and sync pattern generator (7)
A non-coincidence circuit (8) that compares the outputs of the above and generates a pulse when they do not coincide. Further, FIG. 2 shows the line separating circuit (10) in detail. In FIG.
(11a), (11b), (11c), and (11d) are D-flip-flops, which are continuously connected by the number of lines to be multiplexed. Of the outputs of this D-flip-flop, the final stage (11d) Of a counter circuit composed of D-flip-flops (11a) to (11d) and a NOR gate (12), and a NOR gate (12) which takes the NOR with all outputs except as input and inputs to the first-stage D-flip-flop (11a) A separation line clock generation circuit (13) for generating a line clock after demultiplexing from the output, and a synchronization line indicating the position of a frame synchronization pulse by frequency division by an appropriate counting circuit from this separation line clock generation circuit (13) And a counter circuit (14) for outputting a selection pulse.

First, in FIG. 1, the multiplex code sequence transmitted as in the conventional example is bit-synchronized to generate a clock pulse. Using this clock pulse as an input, a line demultiplexing circuit (10) generates a pulse for separating a multiple code sequence into each line and a clock associated with the pulse, and a decoder circuit (4) serial-parallel converts the multiple code sequence. To separate the line. Up to this point, the configuration is exactly the same as the conventional method. If the speed of the multiple code sequence increases to several gigabits per second or more, this bit synchronization circuit (1)
Although it is difficult to perform processing such as synchronization verification and hunting with the output clock, the processing is performed here using the data and clock after demultiplexing.

The line separation circuit (10) generates a sync line selection pulse [separated line clock 1-bit width] at the position of the frame sync pulse by counting by the counting circuit in the same manner as in the conventional case, and one AND gate (5) Then, this pulse is synchronized with the separated line clock, and the synchronization pattern generator (7)
To enter. The sync pattern generator generates a predetermined sync pattern based on the output of the one AND gate (5). On the other hand, the other AND gate (6) takes the logical sum of the above-mentioned sync line selection pulse and the data of the specific channel to which the frame sync pulse should be output when the multiplex code sequence is normally separated, and the disagreement circuit ( 8), and the output of the sync pattern generator (7) is compared with the non-coincidence circuit (8). When they do not coincide, a shift pulse having a separated line clock 1 bit width is generated. When the shift pulse is input to the line separation circuit (10), the counter in the line separation circuit (10) shifts by 1 bit, and the phase of the separation pulse input to the decoder circuit (4) shifts, and the decoder The output separation line is shifted to the circuit (4). In this way, the channel position in which the normal frame synchronization is inserted shifts until the channel position becomes correct, and the synchronization is restored.

The 1-bit shift is possible even when the shift pulse has a 1-bit width of the separation line by the configuration of the line separation circuit (10) shown in FIG. The operation of the line separation circuit (10) will be described below.

FIG. 3 shows a simple time chart when the number of multiplexed lines is 4. Since the number of multiplexed lines is 4, the D-flip flop in FIG. 2 [hereinafter referred to as D-FF] (11)
The number of cascaded stages is 4, and the output signal of the NOR gate (12) that receives the D-FF output of the first stage, the second stage, and the third stage is input to the input of the first stage D-FF (11a). The operation of this counter is a conventionally known operation, and usually four D-FFs are used.
Only one of them becomes "1" and this shifts to the right in order. The line is separated in the decoder circuit (4) using this pulse. Here, the separated line clock rises at the rising edge of the first-stage flip-flop output, and falls at the rising edge of the third-stage flip-flop output, and the separated data is the rising-edge trigger of the first-stage flip-flop output. In this case, the sync line selection pulse indicating the position where the frame sync signal should enter is also expected to be output at the frame sync position, and the first stage D-FF (11a)
This is a case where the rising edge of the output is used as a trigger.

In FIG. 3, a sync line selection pulse is generated at the position A, and both AND gates (5), (6) in FIG.
When a mismatch is detected by the mismatch circuit (8) through the sync pattern generator (7), the shift pulse shows "1".
When the shift pulse becomes "1", the third stage D-FF in FIG.
(11c) is reset, the pulse of * part in the time chart of FIG. 3 disappears, all D-FFs become "0", and only the first stage D-FF (11a) is generated at the next clock. "1"
Therefore, the phase of the pulse for the decoder has 1 bit, and the desired 1-bit shift function can be realized. The above operation is possible as long as the delay time α until the shift pulse is generated is within the delay time of 3 bits of the transmission path clock, and the 1-bit shift processing for mismatch detection and hunting is all performed on the high-speed transmission path. It is not necessary to use a clock, and it can be performed only by the processing by the separated line clock, so that a high speed operation can be realized and an element used such as a gate can be constructed at a low cost.

In the above embodiment, the case where the frame synchronization pattern exists in only one line separation channel is shown, but it may exist in a plurality of line separation channels.
At this time, as the other AND gate (6), a plurality of ORs are formed in parallel with a synchronization line selection pulse indicating the position where each frame synchronization pattern should exist for all the channels for which the frame synchronization pattern is expected. Then, the output of the synchronous pattern generator (7) is set to a plurality of parallel outputs, and a plurality of bits may be compared in the mismatch circuit.

Further, in the above-described embodiment, the position where the counter is reset by the shift pulse is realized by resetting the D-FF one stage before the last stage of the cascade-connected D-FF, but shifts in the counter circuit. If it is a method of extinguishing the going pulse with the output of the D-FF one stage before the final stage, another method such as performing a logical operation with this shift pulse and the D-FF output one stage before the final stage It doesn't matter.
If the position of the D-FF to be reset is shiftable (for example, 2 bits or 3 bits) other than 1 bit due to the system configuration, it is possible to reset not only the last stage but the other D-FF. I don't care.

In the embodiment, for convenience of explanation, the separated line clock rises at the rising edge of the D-FF (11a) output in the first stage, and the D-line in the third stage.
-FF (11c) output is set to fall at the rising edge, but it may be in another place.

[Effects of the Invention] As described above, the present invention performs the mismatch detection in frame synchronization by using the data of the demultiplexed channel, processes it by using the clock after the line separation, and sets it as a basic counter of the line separation circuit. -The flip-flops are connected in cascade for the number of multiple lines, and all D-flip-flop outputs except the final stage are input to the first-stage D-flip-flops by the NOR gate, and the counter is conventionally used to provide a 1-bit shift function. Since the D-flip-flop one stage before the final stage is reset by a shift pulse having a 1-bit width of the clock after the line separation by the above-mentioned mismatch detection, the mismatch detection and the 1-bit shift processing are slow clocks after demultiplexing. Therefore, even if the multiplex transmission speed becomes high, synchronization can be realized. Therefore, there is an effect that an inexpensive element having a slow processing speed can be used.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration block diagram of a frame synchronization circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a detailed example of a line separation circuit in FIG. 1, and FIG. FIG. 4 is a timing diagram showing an operation example of the frame synchronization circuit according to the present invention, and FIG. 4 is a block diagram showing a configuration of a conventional frame synchronization circuit. In the figure, (1) is a bit synchronization circuit, (2) is a logic gate, (3) is a line separation circuit, (4) is a decoder circuit,
(5) is one AND gate, (6) is the other AND gate, (7) is a synchronization pattern generator, (8) is a mismatch circuit, (9) is a delay circuit, (10) is a line separation circuit, ( 11)
Is a D-flip flop, (12) is a NOR gate, (13)
Is a separation circuit clock generation circuit, and (14) is a counting circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A clock from a transmission line is input to cascade connection of D-flip-flops by the number of multiplexed lines, and outputs of D-flip-flops other than the final stage are input to the D-flip-flop of the first stage by a NOR gate. A line demultiplexing circuit that outputs a demultiplexing line clock and a synchronous line selection pulse from the output of the counter, and a decoder circuit that inputs the counter output of this line demultiplexing circuit and demultiplexes by deserializing the input multiplex code sequence. One AND gate for inputting the synchronous line selection pulse and the separate line clock of the line separation circuit, and the output of the one AND gate are input to synchronize the frame with the separate line clock at the synchronous line selection pulse position. A synchronization pattern generator for generating a synchronization pattern,
Another AND gate for inputting the synchronous line selection pulse output from the line separation circuit and the decoder circuit output,
By comparing the output of the other AND gate and the output of the synchronization pattern generator, the bits at the position where the synchronization line selection pulse of the channel where the frame synchronization signal is to be inserted among the separated channels are compared, A frame synchronization circuit comprising: a mismatch circuit that outputs a shift pulse with a 1-bit width of the separation line clock to reset the D-flip-flop one stage before the final stage of the counter of the line separation circuit in the case of a mismatch.