JPH044631A - Pn pattern detector - Google Patents

Abstract

PURPOSE:To reduce power consumption more than that of a conventional detector by adopting the constitution of the PN pattern detector such that the detector processes a parallel PN pattern. CONSTITUTION:A PN pattern detector 34 consists of a demultiplex circuit 35, a parallel comparator circuit 34, a test use parallel PN pattern generating circuit 37 and a PN pattern synchronization discrimination circuit 38. The parallel PN pattern generating circuit 37 generates a detection use parallel PN pattern while utilizing the demultiplexed parallel PN pattern and the PN pattern synchronization discrimination circuit 38 discriminates the synchronization between the parallel PN pattern demultiplexed based on the output of the parallel comparator circuit 36 and the detection use parallel PN pattern and gives the result to parallel PN pattern generating circuit 37, the coincidence between the parallel PN pattern demultiplexed in this state and the detection use parallel PN pattern is checked by the parallel comparator circuit 36, which outputs the result of test of a tested object 33 in response to the quantity of dissidence.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a PN pattern detector used for testing system elements (targets under test) such as lines, exchanges, and multiplexing circuits in digital transmission systems, for example. Regarding.

[Prior Art] Conventionally, when testing a line in a digital transmission system, one station inputs a test pattern to the line, and another station receives the test pattern via the line and checks whether it matches the original test pattern. This is done based on whether or not there is. Similarly, multiplexing equipment and switching equipment are tested by inputting a test pattern into the equipment and comparing the pattern output from the equipment with the original pattern.

As a test pattern used in such a test, a PN (pseudo-noise) pattern is used, which is free from the effects of periodicity of the pattern, bias in appearance of logic levels, and the like.

FIG. 2 shows a conventional conceptual test configuration using a PN pattern. 3 and 4 show specific examples of conventional configurations, with FIG. 3 showing a PN pattern generator and FIG. 4 showing a PN pattern detector.

In FIG. 2, a PN pattern generator 1 generates a PN' pattern, and applies the generated PN pattern to an object under test 2 such as a line. The PN pattern via the object under test 2 is provided to a PN pattern detector 3.

The PN pattern detector 3 includes a comparison circuit 4, a detection PNN butter generator 5, and a P, N pattern synchronization determination circuit 6. In the PN pattern detector 3, a detection PNN butter generator 5 generates a detection PN pattern using the received PN pattern, and a PN pattern synchronization determination circuit 6 generates a received PN pattern based on the output from the comparison circuit 5. The synchronization between the received PN pattern and the detection PN pattern is determined, and the result is given to the detection PNN butter generator 5 for synchronization. The test results of the test subject 2 are output.

The test PN pattern generator 1 includes, for example, a 15-stage shift register circuit 10 as shown in FIG. and the first stage register F1
5, and an exclusive OR circuit 11 that applies to

After initializing each stage register F15 to F1 of the shift register circuit 10 to all logic "1" or all logic "0", a PN pattern is generated from the last stage register F1 by shifting with a clock signal (not shown) having a predetermined period. I am trying to output the following. The generating polynomial of the PN pattern generated with the configuration shown in FIG. 3 is x15+x+1, and its period is 2151 children.

PN corresponding to the PN pattern generator 1 shown in FIG.
A specific example of the configuration of the pattern detector 3 is shown in FIG. Fourth
As shown in the figure, a PN pattern generation section 17 consisting of a shift register circuit 15 and an exclusive OR circuit 16 is also provided on the detection side.

The output of the exclusive OR circuit 16 on the detection side is not directly applied to the first stage register F15, but is applied to the first stage register F15 via the selector circuit 18. The selector circuit 18 selects the received PN pattern until the PN pattern from the generator 17 and the received PN pattern match, that is, until synchronization is established, and selects the PN pattern from the generator 17 after synchronization is established. do.

This switching of the selector circuit 18 is controlled by a counter circuit 19 for PN pattern synchronization protection. That is, the counter circuit 19 determines whether synchronization is established. Counter circuit 19
is provided with the output of an exclusive OR register 20 that performs an exclusive OR between the received PN pattern and the PN pattern generated by the generator 17, and this output is used as a logic to indicate that both PN patterns match. When the level continues to be a predetermined number of bits, it is determined that synchronization has been established and the selector circuit 18 is switched to the PN pattern side from the generator 17.

Further, the output of the exclusive OR circuit 20 is given to an error number counter circuit 21. This counter circuit 21 performs a counting operation after entering the synchronous pull-in state. In the synchronous pull-in state, if there is no abnormality in the object under test 2, the received PN pattern and the PN output by the generator 17
It should match the pattern. Therefore, by counting the number of mismatches, it is possible to detect the degree of abnormality of the object under test 2, and output this.

[Problems to be Solved by the Invention] By the way, the transmission speed of digital transmission systems, particularly the transmission speed of high-order signals, has become extremely high (for example, 400 Mbps). Therefore, it is necessary to process a high-speed PN pattern with a short bit period. high speed P
A PN pattern generator that generates N patterns and a PN pattern detector that performs a detection operation are actually constructed using integrated circuits, but as the speed of integrated circuits increases, power consumption increases exponentially. The same thing can be said about circuit elements other than integrated circuits, although they are not integrated circuits. Furthermore, the higher the speed, the greater the restrictions on what can be used as lead wires and other circuit elements.

The present invention has been made in consideration of the above points, and provides a PN that can establish synchronization of PN patterns by processing a high-speed PN pattern as a low-speed PN pattern.
It is intended to provide a pattern detector.

[Means for Solving the Problem] In order to solve the problem, in the present invention, a PN pattern detector is configured with the following elements.

In other words, serial/parallel expansion of input signals
A parallel conversion circuit, a PN pattern generation circuit that generates a PN pattern based on a divided clock signal obtained by dividing a clock signal by the number of parallel expansions of the input signal, and a PN pattern generated from this PN pattern generation circuit in parallel. A first pattern conversion circuit that converts into a parallel PN pattern, and a coincidence detection circuit that detects coincidence between a parallel signal for an input signal and a parallel PN pattern from the first pattern conversion circuit are provided. Further, a synchronization establishment determination circuit that determines the establishment of synchronization of the PN pattern based on the result of the coincidence detection circuit, and a second pattern conversion circuit that performs the inverse conversion of the conversion performed by the first pattern conversion circuit are provided.

Then, when the synchronization establishment determination circuit determines that synchronization is out of synchronization and enters the PN pattern synchronization pull-in state, the second pattern conversion circuit converts the input signal and converts the obtained PN pattern to the PN pattern generation circuit. It was decided to load the data into the PN pattern and establish synchronization of the PN pattern.

[Operation] The present invention attempts to construct a PN pattern detector using low-speed operating elements.

A serial/parallel converter circuit expands the input signal into parallel parallels and provides it to a coincidence detection circuit. Further, the PN pattern generation circuit generates a PN pattern based on a clock signal having a clock rate that is 1/the number of parallel expansions of the rate of the input signal, and the first pattern conversion circuit generates a PN pattern from this PN pattern generation circuit. The resulting PN pattern is converted into a parallel PN pattern and provided to a coincidence detection circuit. The coincidence detection circuit receives a parallel signal parallel to the input signal,
A synchronization establishment determination circuit detects coincidence with the parallel PN pattern from the first pattern conversion circuit, and determines synchronization establishment of the PN pattern based on the result of this coincidence detection circuit.

Here, when the synchronization establishment determination circuit determines that synchronization has been lost and it becomes necessary to perform the synchronization pull-in operation of the PN pattern again,
The second pattern conversion circuit converts the input signal and loads the PN pattern obtained into the PN pattern generation circuit to establish synchronization of the PN pattern.

[Example] Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

Here, FIG. 5 is a block diagram of the conceptual configuration of a test device to which this embodiment is applied, FIG. 6 is a block diagram showing a specific configuration example of the PN pattern generator, and FIG. 7 is a block diagram of the logic circuit section. FIG. 1 is a block diagram showing a specific example of the configuration of a PN pattern detector in the conceptual configuration of the test apparatus.

concept old fashioned First, the conceptual configuration of the test device will be explained using FIG. 5.

The PN pattern generator 30 of this embodiment is not composed of a single PN pattern generator (corresponding to a conventional generator) but is composed of a parallel PN pattern generation circuit 31 and a bit multiplexing circuit 32. The parallel type PN pattern generation circuit 31 simultaneously generates a plurality of synchronized PN patterns in parallel, and provides the generated parallel PN patterns to the bit multiplexing circuit 32. The bit multiplexing circuit 32 bit-multiplexes the applied parallel PN pattern, converts it into a serial PN pattern, and outputs it to an object under test 33 such as a line.

Here, the speed of the series PN pattern is determined by the object under test 33, and the speed of one P in the parallel PN pattern is
The speed of the N pattern is 1/the number of parallel PN patterns. That is, the processing speed of the parallel PNN pattern generator path 1 is considerably slower than the speed required for the object under test 33.

Of course, the speed of the series PN pattern is
3 is equal, it is equal to the speed of the PN pattern generated by the conventional PN pattern generator 1.

The serial PN pattern via the object under test 33 is provided to a PN pattern detector 34 . The PN pattern detector 34 includes a separation circuit 35, a parallel comparison circuit 36, and a parallel type P for testing.
It consists of an N pattern generator 37 and a PN pattern synchronization determination circuit 38.

The separation circuit 35 performs inverse processing of the bit multiplexing circuit 32, and converts the received serial PN pattern into a parallel PN pattern by separating it and provides it to the parallel comparison circuit 36 and the parallel PNN pattern generator path 7. It is something.

Hereinafter, test operations are performed based on the parallel PN pattern. That is, the parallel PNN pattern generator path 7 generates a parallel PN pattern for detection while using the separated parallel PN pattern.
Generate a pattern and determine PN pattern synchronization F! ! 13
8 determines the synchronization between the separated parallel PN pattern and the parallel PN pattern for detection based on the output from the parallel comparison circuit 36, and sends the result to the parallel PNN pattern generator circuit 7.
In this state, the parallel comparison circuit 36 captures any coincidence or mismatch between the separated parallel PN pattern and the detection parallel PN pattern, and outputs the test result for the object under test 33 according to the amount of mismatch. I have to.

The speed of each PN pattern (each PN pattern among the parallel PN patterns) processed by each element 36 to 38 of this PN pattern detector 34 except for the separation circuit 35 is also 1/the speed of the serial PN pattern by the number of parallels. It has become. In other words, it has a low-speed processing configuration.

PN pattern l'30 Next, a specific example of the configuration of the PN pattern generator 30 will be described with reference to FIGS. 6 and 7.

This generator, for example, takes an exclusive OR of the output logic levels of a shift register circuit 40 having a 15-stage configuration, a register F1 at the last stage of this shift register circuit 40, and a register F2 at the immediately preceding stage, and then calculates the exclusive OR of the output logic level of the register F1 at the last stage of this shift register circuit 40 and the register F2 at the immediately preceding stage. F1
5, and a logic circuit section 42 which inputs the output logic levels of the registers F1 to F15 at each stage of the shift register circuit 40 and performs the processing shown in FIG. The shift register circuit 40, exclusive OR circuit Tr441, and logic circuit section 42 constitute a parallel PNN pattern generator circuit 1.

After initializing each stage of registers F15 to F1 of the shift register circuit 40 and setting them all to logic "1", serial P is shifted by a clock signal (not shown) having a predetermined period.
Output N patterns.

Note that the generating polynomial of the PN pattern generated by the shift register circuit 40 and the exclusive OR circuit 41 is x15+x+1 as in the conventional case, and its period is 2.
It is 151 digits.

The logic circuit section 42 generates eight PN patterns 5EQI to 5EQ8 that differ by 212 digits from the 15 PN patterns (outputs of registers F1 to F15 at each stage) that differ in phase by l clock cycles generated in this manner. It is something to do.

A code surrounded by parentheses indicates that an exclusive OR is taken, and a code consisting of the alphabet "F" and a number such as F3 and F4 indicates the register of the stage of the shift register circuit 40 represented by that code. Indicates output logic level.

Therefore, the logic circuit section 42 converts the output of the register F3 of the shift register circuit 40 into the output PN pattern 5E of the first series.
QI, and the register F of the shift register circuit 40
4, the exclusive OR output of the outputs of F5, F7 and Fil□□□ is used as the output PN pattern 5EQ2 of the second series, and the PN patterns of other series are also formed by logical operations as shown in Fig. 6. ing.

Here, the reason why the output of the register F3 of the shift register circuit 40 is used as it is for the PN pattern 5EQI of the first series, which is the reference, is that
This is because the configuration of the logic circuit section 42 is the simplest configuration.

The PN patterns 5EQI to 5EQ8 of each series are provided to a parallel/serial conversion circuit 43 as a bit multiplexing circuit. This parallel/serial conversion circuit 43 converts the PN pattern 5EQ of each series through parallel/serial conversion.
I~5EQ8 are multiplexed to form a serial PN pattern and applied to the object under test 33.

It is also conceivable to provide eight individual PN pattern generation configurations each consisting of a shift register circuit and an exclusive OR circuit to generate each series of PN patterns 5EQ1 to 5EQ8. Using this will simplify the overall configuration.

PN Pattern v134 - Next, a specific example of the configuration of the PN pattern detector 34 corresponding to the configuration of the PN pattern generator shown in FIG. 6 will be described with reference to FIG.

The serial PN pattern received via the object under test 33 is provided to a serial/parallel conversion circuit 44 as a separation circuit. The serial/parallel conversion circuit 44 performs serial/parallel conversion on this serial PN pattern, converts it into eight series of parallel PN patterns, and supplies the parallel PN patterns to the following detection components.

As shown in FIG. 1, a parallel PN pattern generation section consisting of a shift register circuit 45, an exclusive OR circuit 46, and a logic circuit section 47 is also provided on the detection configuration side.

A selector circuit 48 is inserted between registers F3 and F2 of the shift register circuit 45. The selector circuit i ¥448 is connected to the parallel PN patterns 5EQ11 to 5EQ81 from the logic circuit section 47 and the serial/parallel conversion port i.
Parallel PN pattern 5EQ12~5EQ starting from ¥1344
82, the first series of PN patterns 5EQ12 from the serial/parallel conversion circuit 44 is selected, and when the synchronization is established, the output of the register F3 is selected and applied to the register F2.

This switching of the selector circuit 48 is controlled by a counter circuit 49 for PN pattern synchronization protection. That is, the counter circuit 49 determines the synchronization pull-in state. The counter circuit 49 has a parallel PN pattern 5 from the logic circuit section 47.
EQII~5EQ81 and serial/parallel conversion circuit 4
Eight outputs of an exclusive OR circuit group 50 which performs an exclusive OR between corresponding patterns of the parallel PN patterns 5EQ12 to 5EQ82 from 4 are provided.

When this output continues to have a logic level indicating that both PN patterns match for a predetermined number of bits, it is determined that synchronization has been established and the selector circuit 48 is switched to the register F3 side of the shift register circuit 45.

Further, eight outputs of the exclusive OR circuit group 50 are applied to an adder circuit 51 for calculating the number of errors.

This adder circuit 51 operates to count the number of bits indicating a mismatch state that occurs after the synchronization pull-in state is reached, regardless of which output it takes.

In the synchronous pull-in state, if an abnormality occurs in the object under test 33, the parallel PN pattern 5EQII~ from the logic circuit section 47
5EQ81 and the parallel PN patterns 5EQ12 to 5EQ82 from the serial/parallel conversion circuit 44 should match. Therefore, by counting the number of discrepancies, it is possible to detect the degree of abnormality of the test object 33,
Output this.

In addition, in the above configuration, the reason why one output 5EQ12 is selected from among the eight outputs from the serial/parallel conversion port #144 is because one PN pattern is formed from the eight outputs, and the function are equivalent, and PN
This means that the load pattern for the shift register circuit 45 constituting the pattern generation section is determined.

Therefore, according to the above embodiment, the PN pattern generator 3
Since both the 0 and PN pattern detectors 34 process a plurality of PN patterns that are slower than the PN patterns that pass through the object under test 33, power consumption can be reduced compared to the prior art. In addition, the actual constraints on each component from the transmission speed are weaker than in the past.

Furthermore, since a plurality of PN patterns are formed from one PN pattern using the logic circuit sections 42 and 47, the configuration is simplified.

That is, the configuration is simpler than when a plurality of components forming one PN pattern are provided in parallel.

In the embodiment described above, the PN pattern generator and the PN
Although the pattern detectors are shown both processing parallel PN patterns, only the PN pattern detector, which has more components than the PN pattern generator, may process parallel PN patterns.

The generating polynomial of the PN pattern, the number of parallel PN patterns, etc. are not limited to those of the above-mentioned embodiments.

[Effects of the Invention] As described above, according to the present invention, the PN pattern detector is configured to process parallel PN patterns, so there is no need to configure the circuit with high-speed operation elements, and the power consumption is reduced compared to the conventional one. can be kept small compared to .

[Brief explanation of drawings]

FIG. 1 is a conceptual block diagram of an embodiment of a PN pattern detector according to the present invention, FIG. 2 is a conceptual block diagram of a conventional test device, and FIG. 3 is a block diagram showing a specific configuration of a conventional PN pattern generator. 4 is a block diagram showing the specific configuration of a conventional PN pattern detector, FIG. 5 is a block diagram showing a test device using the PN pattern detector according to the present invention, and FIG. 6 is a block diagram showing the test device using the PN pattern detector according to the present invention. FIG. 7 is a block diagram showing a specific configuration of the PN pattern generator, and is a chart for explaining the processing of the logic circuit section. 44... Serial/parallel conversion circuit, 45... Shift register circuit, 46.50... Exclusive OR circuit, 47... Logic circuit section, 48... Selector circuit, 49... Counter Circuit, 51...adder circuit. Patent Applicant Oki Electric Industry Co., Ltd. (Procedural Amendment (Salmon) September 12, 1990,

Claims (1)

[Claims] A serial/parallel conversion circuit that parallelizes an input signal; and a PN pattern generation circuit that generates a PN pattern based on a clock signal having a clock rate that is 1/the number of parallel expansions of the rate of the input signal. and a first pattern conversion circuit that converts the PN pattern generated from this PN pattern generation circuit into a parallel parallel PN pattern; A coincidence detection circuit that detects coincidence with the PN pattern, a synchronization establishment determination circuit that determines the establishment of synchronization of the PN pattern based on the result of this coincidence detection circuit, and performs the inverse conversion of the conversion by the first pattern conversion circuit. and a second pattern conversion circuit, wherein when the synchronization establishment determination circuit determines that the synchronization is out of synchronization and the PN pattern is in a synchronization pull-in state, the second pattern conversion circuit performs conversion processing on the input signal. A PN pattern detector characterized in that the PN pattern obtained by the PN pattern is loaded into the PN pattern generation circuit to establish synchronization of the PN pattern.