JPH011342A - Frame synchronization method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a frame synchronization system for a PCM multiplex conversion device,
That is, the present invention relates to a frame synchronization method that multiplexes and demultiplexes high-order group signals into low-order group signals and performs frame synchronization and channel assignment.

[Conventional technology]

Frame synchronization of a PCM multiplex converter is to synchronize the timing of the receiver with respect to an incoming PCM multiplex signal frame synchronization pulse in order to determine the starting point of one frame in the receiver of the multiplex converter. This frame synchronization pulse is inserted when a low-order group input signal is synchronized and multiplexed into a high-order group signal to form one multiplexed frame in the transmitter. On the receiving side, the specific pattern given as the frame synchronization pulse is detected to find the starting point of the multiplexed frame. Typical methods for searching for frame synchronization patterns include a 1-bit immediate shift method and a delayed shift method.

The former method searches for a frame synchronization pattern by immediately shifting the timing pulse by one bit when the frame synchronization pattern does not exist at the desired position. This method has the advantage of short synchronization pull-in time, but as higher-order group signals become faster, it is difficult to reduce the loop delay time of the 1-bit instant shift control loop to one time slot or less due to the operating speed limit of the logic circuit used. It's getting difficult. Alternatively, a large number of expensive high-speed logic elements must be used.

On the other hand, in the latter delay shift method, although there is no restriction on the loop delay time as described above, there is a drawback that the synchronization recovery time is long.

As a method to solve these problems, a parallel frame synchronization method has been proposed in which the multiplexed high-order group signals are not synchronized, but are demultiplexed into low-order group signals, and frame synchronization is performed on the low-order group side. Ta. Figure 4 shows the special public service issued in 1977-2857.
9 is a circuit configuration diagram of a parallel frame synchronization method disclosed in Publication No. 9. FIG. In the figure, 1 is a four-stage shift register into which the high-order group signal P9 is input in series by the high-order group clock CLK, 2a to 2d and 21a to 21c are 1-bit memories for serial-to-parallel conversion, and 4a to 4d are for frame synchronization pattern detection. AND gate, 5 sets the high order group clock CLKM to 4
A 4-frequency divider circuit that divides the frequency to obtain a low-order group clock CLKL for serial-to-parallel conversion, and 6 is a 1-by-4 frequency divider circuit that divides the frequency to obtain a low-order group clock CLKL for serial-parallel conversion.
A frame counter that counts the frame length; 7 a synchronization protection circuit that determines frame synchronization establishment and protection period; 9;
゜24 is an AND gate, 13.14 and 27 to 32 are inversion gates, 16.25.26 are inhibit gates, 22 is a channel switching circuit for switching channels after establishing frame synchronization, and 23 detects a frame synchronization pattern. This is a pattern identification circuit that inputs the outputs of each of the anime games 4a to 4d and identifies patterns. In addition, P and l are higher-order group signals,
CHI to CH4 are channels of demultiplexed low-order group signals, CLK is a high-order group clock, CLKL is a low-order group clock, and Patl to Pat4 are frame synchronization detection outputs shown in FIGS. 5(a) to (d). ing.

Next, the operation will be explained. a high-order group signal pulse train P that is multiplexed with 4 channels of low-order group signals and a frame synchronization pulse;
Consider l. The pulse train P of this high-order group signal is transferred to the 4-stage shift register 1 by the high-order group clock pulse CLKH.
will be written to. Immediately before the 5th bit is written to the shift register 1, serial-to-parallel conversion is performed using the low-order group clock CLKL, which is obtained by dividing the high-order group clock CLKH by 4 using the 4-frequency divider circuit 5, and the 1-bit memories 2a to 2d and 21a to 21c are
Transfer to. 1-bit memories 2a-2d and 21a-
21c, there are a total of four combinations as shown in FIGS. 5(a) to 5(d). In Fig. 5, the frame synchronization pattern has a 4-bit configuration, and F+, Fz
, F3, and Fa, and symbols other than the frame synchronization pulse are represented by x. A parallel frame synchronization pattern detection circuit consisting of AND gates 4a to 4d in FIG. 4 detects which of these four combinations has appeared, or whether all the combinations have not appeared. Frame synchronization pattern 110
0, ie F+ =1. Fz=1. F3=O.

If F4=0, if the same pattern as the frame synchronization pattern exists, P a t in P a t
LPat3. Only one of Pat4 becomes "1" and the others become "0".The pattern identification circuit 23 continuously identifies the presence or absence of these outputs and the type of pattern, and when any pattern is identified, it becomes "1". is sent to the inhibition gate 25. On the other hand, when the frame counter 6 counts one frame length using the low-order group clock CLKL, it sends out "1".

If this output and the output of the pattern identification circuit 23 match, the output of the inhibition gate 25 becomes "O", and the synchronization protection circuit 7
It is determined that synchronization has been established, and the number of consecutive matches is counted, and when the number of consecutive matches exceeds a predetermined value, synchronization is determined to have been established. In addition, if the output of the frame counter 6 is "1" and there is no match, the prohibition gate 2
5 becomes "1", and the low-order group clock CLKL to the frame counter 6 is inhibited by 1 bit. By performing this continuously, frame synchronization can be achieved in low-order groups.

When frame synchronization is performed as described above, CHI~
Since the low-order group signal corresponding to CH4 is not necessarily demultiplexed and output, channel switching is required.

Since the frame synchronization pattern of the high-order group multiplexed frame is Fl+Ft, Fs, Fa in the order of the low-order group channels, if the pattern at the time of synchronization recovery is as shown in FIG.
Corresponding low-order group signals are obtained from HI to CH4. In the case of the pattern shown in FIG. 2(b), the channel order of the shift register 1 is CH2, CH3, CH4, CHI, so the input of the high-order group clock CLK to the divide-by-4 circuit 5 is inhibited by the channel switching circuit 22. If 3 bits are inhibited by controlling 16, low-order group signals corresponding to CHI to CH4 can be obtained. In the same way, the same figure ((In case of J, 2 bits same figure (
In the case of dl, it is sufficient to disable 1 bit.

In this way, by providing the channel switching circuit 22 with the function of controlling the number of prohibited bits corresponding to the frame synchronization detection pattern, it becomes possible to switch to a predetermined channel after synchronization is established.

[Problem that the invention seeks to solve]

Conventional parallel frame synchronization methods demultiplex low-order group signals at arbitrary phases as described above, and then switch to a predetermined channel after synchronization is established, resulting in a complex circuit configuration and large scale. . Furthermore, since there are multiple types of combinations of frame synchronization patterns, there is a problem in that erroneous synchronization is likely to occur because any combination will be judged as having a frame synchronization pulse.

This invention was made to solve the above-mentioned problems, and it is possible to reduce the circuit size with a simple configuration without using a large number of expensive high-speed logic elements or increasing the synchronization recovery time. The objective is to obtain a frame synchronization method that can prevent erroneous synchronization.

[Means for solving problems]

The frame synchronization method according to the present invention includes a frame synchronization pattern detection circuit, a high-order group frame synchronization pattern detection circuit that detects a frame synchronization pattern from a high-order group signal, and a frame synchronization pattern detection circuit that detects a frame synchronization pattern from demultiplexed parallel low-order group signals. and a next group frame synchronization pattern detection circuit, and also includes means for sending the detection output of the higher order group frame synchronization pattern detection circuit to the lower order group frame synchronization pattern detection circuit in the frame synchronization pattern search process, and is configured to establish and protect frame synchronization. During the period, the frame synchronization pattern is detected by the low-order group frame synchronization detection circuit, and when the frame synchronization pattern is no longer detected at the frame synchronization position, the frame synchronization protection circuit prohibits frequency division from the high-order group clock to the low-order group clock. Based on this (in the frame synchronization pattern search process, the high-order group frame synchronization detection circuit detects the frame synchronization pattern, and the detection output is sent to the low-order group frame synchronization detection circuit, and the low-order group clock is detected from the high-order group clock). The prohibition of frequency division to the clock is canceled after a predetermined delay.

[Effect]

In the two frame synchronization pattern detection circuits in this invention, the frame synchronization pattern detection circuit corresponding to the low-order group signal operates during the WAR rising and protection periods, detects a mismatch in the frame synchronization pattern, and switches the high-order group clock to the low-order group clock. It operates until frequency division is prohibited. When frequency division is prohibited and frame synchronization pattern search begins, the frame synchronization pattern detection circuit corresponding to the high-order group signal operates, and when a frame synchronization pattern is detected from the high-order group signal pulse train,
The detection output is sent to a frame synchronization pattern detection circuit corresponding to the low-order group signal to operate the circuit, and the inhibition of frequency division from the high-order group clock to the low-order group clock is canceled with a predetermined delay.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit configuration diagram according to an embodiment, and in the figure,
1 is a 4-stage shift register, 2a to 2d are 1-pinto memories for serial-to-parallel conversion, 3 and 4 are AND gates, AND gate 3 corresponds to a high-order group frame synchronization pattern detection circuit in this application, and AND gate 4 corresponds to a low-order group frame synchronization pattern detection circuit. Corresponds to the next group frame synchronization pattern detection circuit. 5 is a 4 frequency divider circuit, 6 is a frame counter, 7 is a frame synchronization protection circuit, 8 to 10
is an AND gate, and the AND gate 10 is provided as a means for sending the detection output of the high-order group frame synchronization pattern detection circuit to the low-order group frame synchronization pattern detection circuit in the frame synchronization pattern search process, and the AND gate 3 and The respective outputs of frame 1, counter 6 and frame synchronization protection circuit 7 are inputted, and their AND outputs are inputted to the set terminals of 1-bit memories 2a and 2b for serial-parallel conversion and the clear terminals of 1-bit memories 2c and 2d. It has become. On the other hand, 11 to 15 are inversion gates, 1
6 is an inhibition gate, and 17 is a delay circuit having a predetermined delay it. Further, PH represents a high-order group signal, CHI to CH4 are channels of demultiplexed low-order group signals, CLK represents a high-order group clock, and CLKL represents a low-order group clock.

Next, the operation will be explained. In addition, in the following explanation, as mentioned earlier, the frame synchronization pattern is 1100.
It is assumed that the high-order group signal PM is composed of a frame in which the four channels of the low-order group signals shown in FIGS. 2(b) to 2(e) are multiplexed as shown in FIG. 2(a).

During the synchronization establishment and protection period, the high-order group signal PI (is sequentially transferred by the 4-stage shift register 1, and Ai, Bi, C
When t and Di are filled in this order, the 4-frequency divider circuit 5 divides the high-order group clock CLK by 4 to generate the low-order group clock CLKL.
The data is transferred to the 1-bit memories 2a to 2d. This results in
In a synchronized state, low-order group signals corresponding to CHI-CH4 are demultiplexed. The AND gate 4 continuously determines whether or not the low-order group signal demultiplexed as described above matches the frame synchronization pattern, and outputs "1" only when the pattern matches. On the other hand, the frame counter 6 counts the low-order group clock CLKH and sends out "1" when the frame synchronization position on the receiving side is reached. When a frame synchronization pattern is detected when the frame counter 6 is "L", the output of the AND gate 4 is 11"2 inversion gate 15
The output of is “O”, and the output of AND gate 8 is “O”
Therefore, it is considered that the synchronization is established. On the other hand, if the frame synchronization pattern is not detected, the output of the AND gate 4 becomes "0", so the inverting gate 15 sends out a "1" and the output of the AND gate 8 becomes "BITONATSU". The "1" sent at this time is delayed by t by the delay circuit 17 and sent to the synchronization protection circuit 7, where the number of mismatches is counted.

When the number of mismatches occurs a predetermined number of times in succession, the synchronization protection circuit 7 sends out "1", and when a mismatch is detected successively, the output of the AND gate 9 becomes "1'" and the prohibition gate 16 disables the high-order group clock CLKH. Then, the frequency divider circuit 5 stops, and the output of the frame counter 6 remains at "1", and a search for a frame synchronization pattern, that is, a hunting process begins. At this time, since the low-order group clock CLKL is stopped, conversion from a serial signal to a parallel signal is not performed.

On the other hand, the AND gate 3 outputs "work" when the contents of the four-stage shift register 1 that transfers the high-order group signal P□ matches the frame synchronization pattern, and when they do not match, the output is "
Therefore, when the same pattern as the frame synchronization pattern first appears in the shift register 1 after entering the hunting process, the output of the AND gate 3 becomes "1" and the output of the AND gate 10 becomes "1". , the contents of the 1-bit memories 2a to 2d are set to a frame synchronization pattern using the set and clear terminals. That is, the contents of the 1-bit memories 2a and 2b are '1'.

The contents of the 1-bit memories 2C and 2d become "0". As a result, the output of the AND gate 4 becomes "1" because the input matches the frame synchronization pattern, and the output of the AND gate 9 becomes 0'' and the clock inhibition is canceled.The clock inhibition is canceled. At the time when the low-order group clock CLKL rises for the first time, the contents of the shift register 1 are changed to a 4-bit signal (for example, AM and BN in FIG. 2) following the frame synchronization pattern of the high-order group signal P9.

By adjusting the delay time by the delay circuit 7, the low-order group signals can be demultiplexed into the corresponding channels CHI to CH4. At this time, the control delay time of the loop due to the delay of the logic element used may be equal to or less than four time slots of the high-order group clock CL K N.

As described above, frame synchronization pattern detection is performed for each of the high-order group signal and the low-order group signal obtained by converting it in parallel, and frame synchronization pattern detection for the former is performed only in the hunting process, so the operation on the low-order group is frame synchronization. It occupies most of the operations for establishment, there is no need to use a large number of expensive high-speed logic elements, and there is no need for a long synchronization recovery time. In addition, when performing serial-to-parallel conversion, it is possible to convert at a predetermined phase by simply adjusting the delay amount of the delay circuit, so it is possible to assign low-order group signals to corresponding channels without adding a pattern recognition function or channel switching function. It has a simple configuration and a small circuit scale.

Furthermore, since there is no need to perform channel switching using only one frame synchronization pattern, it is possible to prevent erroneous synchronization caused by this.

In the above embodiment, the high-order group clock CLKN was prohibited by the prohibition gate 16, but as shown in FIG. 3, the 4-frequency divider circuit 5 is replaced by a flip-flop 1B.

L9 is configured to omit the inhibit gate 16, and the output of the flip-flop 18 is held at "1" and the output of the flip-flop 19 is held at "0" by the inhibit pulse that is the output of the AND gate 9, and the clock inhibition is released. By adjusting the delay amount of the delay circuit 17 so that the low-order group clock rises with the rise of the first high-order group clock CLKM, the same effect as described above can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, a frame synchronization pattern detection circuit is combined with a high-order group frame synchronization pattern detection circuit that detects a frame synchronization pattern from a high-order group signal, and a frame synchronization pattern detection circuit that detects a frame synchronization pattern from demultiplexed parallel low-order group signals. and a low-order group frame synchronization pattern detection circuit for detecting a frame synchronization pattern, and a means for sending the detection output of the high-order group frame synchronization pattern detection circuit to the low-order group frame synchronization pattern detection circuit in the frame synchronization pattern search process, During the protection period, the frame synchronization pattern is detected by the low-order group frame synchronization detection circuit, and when the frame synchronization pattern is no longer detected at the frame synchronization position, the frame synchronization protection circuit prohibits frequency division from the high-order group clock to the low-order group clock. death,
In the frame synchronization pattern search process based on this, the high-order group frame synchronization detection circuit detects the frame synchronization pattern, and sends the detection output to the low-order group frame synchronization detection circuit, which divides the high-order group clock into the low-order group clock. Since the inhibition of synchronization is canceled after a predetermined delay, the circuit scale can be reduced with a simple configuration without using many expensive high-speed logic elements or increasing the synchronization recovery time. This has the effect of being able to prevent this.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram for realizing a frame synchronization method according to an embodiment of the present invention, FIG. 2 is a diagram showing the frame structure of a high-order group signal and the corresponding low-order group signal, and FIG. It is a figure which shows the detection output of the period pattern of other Examples. In the figure, 1 is a 4-stage shift register, 2a to 2d are 1
Bit memory (memory for serial/parallel conversion), 3 is an AND gate (high order group frame synchronization pattern detection circuit), 4 is an AND gate (low order group frame synchronization pattern detection circuit),
5 is a 4 frequency divider circuit, 6 is a frame counter, 7 is a frame synchronization protection circuit, 8 to 10 are AND gates, 11 to 15 are inversion gates, 16 is an inhibition gate, 17 is a delay circuit, P,
is a high-order group signal, CHI to CH4 are channels, CLK is a high-order group clock, and CLKL is a low-order group clock. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa (and 2 others) 4th Diagram 5

Claims (2)

[Claims] (1) A shift register into which a high-order group signal, in which multiple low-order group signals are multiplexed together with a frame synchronization pattern to form one multiplexed frame, is input in series by a high-order group clock; a memory for serial-to-parallel conversion to obtain a low-order group signal by performing serial-to-parallel conversion using a low-order group clock obtained by dividing a clock by the number of low-order group signals; a frame counter that counts one frame length using the low-order group clock; It is equipped with a frame synchronization pattern detection circuit that detects a synchronization pattern, and a frame synchronization protection circuit that determines the establishment of frame synchronization and the protection period based on the output of this detection circuit and the output of a frame counter, and converts a high-order group signal into a low-order group signal. In a frame synchronization method that performs frame synchronization by demultiplexing and searching for frame synchronization patterns and allocating channels for low-order group signals, the frame synchronization pattern detection circuit is replaced with a high-order group frame synchronization pattern detection circuit that detects frame synchronization patterns from high-order group signals. , a low-order group frame synchronization pattern detection circuit that detects a frame synchronization pattern from demultiplexed parallel low-order group signals, and a low-order group frame synchronization pattern detection circuit that detects a frame synchronization pattern from the demultiplexed parallel low-order group signals. The frame synchronization pattern is detected by the low-order group frame synchronization detection circuit during frame synchronization establishment and protection period, and frame synchronization is performed when the frame synchronization pattern is no longer detected at the frame synchronization position. The protection circuit prohibits frequency division from the high-order group clock to the low-order group clock, and in the frame synchronization pattern search process based on this, the high-order group frame synchronization detection circuit detects the frame synchronization pattern, and the detection output is used as the low-order group frame. A frame synchronization method characterized in that the prohibition of frequency division from the high-order group clock to the low-order group clock is canceled with a predetermined delay by sending the signal to a synchronization detection circuit. (2) The means for sending the detection output of the high-order group frame synchronization pattern detection circuit to the low-order group frame synchronization pattern detection circuit inputs each output of the high-order group frame synchronization pattern detection circuit, the frame counter, and the frame synchronization protection circuit, and Consists of an AND gate that sets and clears a predetermined bit in the serial-to-parallel conversion memory with an AND output, and sets the contents of the serial-to-parallel conversion memory to a frame synchronization pattern by the detection output of the higher-order frame synchronization pattern detection circuit in the process of searching for a frame synchronization pattern. A frame synchronization method according to claim 1, characterized in that the frame synchronization method is configured to: