JPH0117621B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronous circuit, and more particularly to a synchronous circuit that generates a signal indicating timing for separating time-division multiplexed signals.

In a communication system that transmits a signal obtained by time-division multiplexing multiple digital signals and adding a predetermined synchronization pattern signal as a basic signal group, the receiving side receives A synchronization circuit is required to generate a timing signal to separate each basic signal group from the signal.

FIGS. 1a and 1b are a block diagram showing a conventional synchronous circuit and a time chart illustrating its operation, respectively. In the basic signal group, like the signal f (or g), a 1-bit signal is added to the n-bit (n is a predetermined positive integer) information signal A1 to An (or B1 to Bn), which is obtained by time-division multiplexing multiple digital signals. A synchronizing signal S _A (or S _B ) is added to constitute one frame, and a plurality of frames that appear one after another constitute one multi-frame. The sequence of synchronization signals S _A (or S _B ) within each multi-frame has a predetermined synchronization pattern. The received signal is a bit-by-bit multiplex of each frame of the two basic signal groups, and is sent from the input terminal 10 to the receiving circuit 1, where it undergoes bipolar/unipolar conversion and becomes signal a, which is sent to the separation circuit 2 and synchronization circuit 3. It will be done. Further, a signal b, which is a clock signal regenerated from the received signal in the receiving circuit 1, is sent to the separating circuit 2 and the synchronizing circuit 3. A synchronization circuit 3 that generates timing signals for separating each basic signal group includes a synchronization detection circuit 31 and a synchronization protection circuit 3.
2, frame synchronization is achieved by detecting the synchronization pattern included in signal a,
A signal e, which is the timing signal, is generated and sent to the separation circuit 2 and the output terminal 13. In the separation circuit 2, a shift register 21 receives signals a and b.
is a signal d that has the same timing as signal a, and a signal c that is obtained by shifting signal a by one period of the pulse of signal b.
and are sent to flip-flops (FF) 22 and 23, respectively. FFs 22 and 23 read signals c and d at the rising edge of the pulse of signal e, respectively, and send signals f and g, which are held until the rising edge of the next pulse of signal e, to output terminals 11 and 12, respectively. Output terminals 11 (or 12) and 13 are connected to a next-stage separation device equipped with a separation circuit and a synchronization circuit, and output a signal f (or g), which is a separated basic signal group, and a signal e, which is a timing signal. In the subsequent separation device, the basic signal group is separated into its constituent digital signals.

The conventional synchronous circuit 3 described above is a multi-channel
As the bit length of the frame increases, the number of components increases, resulting in an increase in the external dimensions of the circuit and power consumption. In particular, in order to detect the synchronization pattern, the synchronization detection circuit 31 must be equipped with a storage circuit having a storage capacity equal to the number of bits of the two multi-frames included in the signal a, and the number of bits of the multi-frames must be As the size increases, it is inevitable that the size will increase.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a compact synchronous circuit using fewer parts.

The circuit of the present invention generates a first pulse indicating the timing of each bit in a signal obtained by further time-division multiplexing the first and second time-division multiplexed signals each consisting of a frame with a predetermined bit length for each bit of the frame. frequency dividing means for receiving a signal and frequency dividing the first pulse signal to generate a second pulse signal indicating timing for separating the first and second time division multiplexed signals from each other; a third pulse signal indicating the presence or absence of a frame synchronization shift in the first time division multiplexed signal; and fourth and fifth pulse signals indicating the timing of predetermined bits in each frame of the first and second time division multiplexed signals, respectively. and when the timings indicated by the fourth and fifth pulse signals are shifted from each other for the first time within a period in which the third pulse signal indicates that there is no frame synchronization shift, and phase control means for changing the phase of the second pulse signal by a predetermined period of time.

Next, the present invention will be explained in detail with reference to the drawings.

2 and 3 are a block diagram showing one embodiment of the present invention and a time chart illustrating its operation, respectively. The synchronizing circuit 4 receives a signal b, which is a clock signal, from the receiving circuit 1, and further indicates the timing of the first bit of the information signal of each frame from the next-stage separation device connected to output terminals 11 and 12, respectively. Receives the signals h and i and a signal j indicating the presence or absence of frame synchronization from the next stage separation device connected to the output terminal 11,
Signal e indicating the timing to separate each basic signal group
is generated and transmitted to the separation circuit 2 and the output terminal 13. Signals h and i received from inputs 14 and 15, respectively, are transmitted to outputs 11 and 1, respectively.
This is a signal sent from the frame counter of the synchronization detection circuit in the next stage separation device connected to 2.
In each frame, the information signal A1~An or B1~ following the 1-bit synchronization signal S _A or S _B
It becomes high level (H) at the time indicating the first bit of Bn. Further, the signal j received from the input terminal 16 is a signal sent from the synchronization protection circuit in the next-stage separation device connected to the output terminal 11, and becomes high level (H) if there is a frame synchronization shift. If there is none, it will be low level (L). Signals h and i are applied to an exclusive OR (EX-OR) gate 41, and signal j is applied to an inhibit gate 42 as an inhibit input and to a flip-flop (FF) 43 as a reset input. EX-OR gate 41
The signal k sent out by the inhibit gate 42 is sent to the input terminal of the inhibit gate 42, and the output signal of the inhibit gate 42 is applied to the FF 43 as a set input. The signal l sent out by the FF 43 is sent to the leading edge detection circuit 44. The leading edge detection circuit 44 receives the signals l and b, and becomes H when a rising edge of the pulse does not appear in the signal l;
When a rising pulse appears on the signal l, the signal m falls and becomes L at the rising edge of the signal b immediately after that, and rises again at the rising edge of the next signal b and becomes H again.
Send out. The counter 45 is a frequency dividing counter, which receives signals b and m, and when signal m is H, counts the pulses of signal b and generates a pulse signal by dividing the frequency of signal b by 2, and when signal m is L, it counts the pulses of signal b and generates a pulse signal by dividing the frequency of signal b by 2. Stop counting the pulses of signal b. The signal e containing this frequency-divided pulse signal is sent to the separation circuit 2, which separates the signal a into two signals f and g, and is sent from the output terminal 13 to the next-stage separation device.

In a normal state, that is, the synchronization signal S _A (or S _B ) and the information signals A1 to An (or B1 to Bn) appear in the signal f (or g), and the next stage receiving the signal f When there is no frame synchronization shift in the separation device, the signals k and j
Since both are L, no rising pulse appears in the signal l sent out by the FF 43, and therefore no falling pulse appears in the signal m. In this case, the synchronization circuit 4 generates a signal e having a constant phase by dividing the frequency of the signal b by 2 to maintain a normal state. When the signal f is received and a frame synchronization error occurs in the next-stage separation device, the signal j becomes H and prohibits the set input to the FF 43. When the frame synchronization is restored, the signal j becomes L and the input to the FF 43 is disabled. Cancels the prohibition of set input. At this time, if a frame synchronization error occurs in the next-stage separation device that receives signal g, the timings at which signals h and i, which indicate the first bit of the information signal, become H are different from each other, causing signal k to become H. Along with this, a pulse rises in the signal l, causing the signal m to become L, so that the phase of the signal e shifts by half a cycle, and H and L are inverted. Along with this, the contents of the signals f and g sent out at the rising edge of the pulse of the signal e are exchanged, and the next-stage separation device receiving the signal f receives a signal that is out of frame synchronization. Sent to be replaced.
When the frame synchronization is recovered, the signal j becomes L.
However, as shown in Fig. 3, when the contents of signals f and g are swapped with those in the normal case, the timing at which signals h and i become H is shifted, so a rising edge of a pulse appears in signal l, and the signal By shifting the phase of e by half a period and inverting H and L,
The contents of signals f and g are exchanged with each other to return to the normal state. By repeating the operations described above a finite number of times, if a frame synchronization error occurs in either of the next-stage separation devices that receive the signal f or g, the two next-stage separation devices will be A normal state can be restored by receiving a signal indicating the presence or absence of frame synchronization from only one side.

Compared to the conventional synchronous circuit 3 shown in FIG. 1a, the synchronous circuit 4 shown in FIG. 2 does not require a memory circuit with a capacity proportional to the length of the multi-frame, and can be made smaller because it uses fewer parts. . Note that the synchronous circuit 4 in Fig. 2
The configuration of is just an example, and can be changed depending on how the logical values are taken as positive or negative, and the configuration of signals h and i
It is clear that a similar effect can be obtained by using another circuit that inverts the height of the pulse of the signal e when the timing of the pulse appearing in the signal e is shifted.

As explained above, the present invention has the effect of realizing a compact synchronous circuit using a small number of parts.

[Brief explanation of drawings]

FIGS. 1a and 1b are a block diagram and a time chart showing a conventional synchronous circuit, respectively, and FIGS. 2 and 3 are a block diagram and a time chart showing an embodiment of the present invention, respectively. 10, 14-16...Input end, 1...Receiving circuit, 2...Separation circuit, 3, 4...Synchronization circuit, 41
...Exclusive OR (EX-OR) gate, 42...
...Inhibition gate, 43...Flip-flop (FF), 44...Leading edge detection circuit, 45...Counter, 11-13...Output terminal.

Claims (1)

[Scope of Claims] 1. A first signal indicating the timing of each bit in a signal obtained by further time-division multiplexing the first and second time-division multiplexed signals, each consisting of a frame with a predetermined bit length, for each bit of the frame. Frequency dividing means that receives a pulse signal and generates a second pulse signal indicating timing for separating the first and second time division multiplexed signals by frequency dividing the first pulse signal; a third pulse signal indicating whether there is a frame synchronization shift in the first time division multiplexed signal; and fourth and fourth pulse signals indicating the timing of a predetermined bit in each frame of the first and second time division multiplexed signals, respectively. During the period in which the third pulse signal indicates that there is a frame synchronization shift, the second pulse signal
without changing the phase of the pulse signal, and without changing the phase of the third pulse signal.
During a period in which the pulse signal indicates that there is no frame synchronization shift, when a timing shift occurs between the fourth and fifth pulse signals, the phase of the second pulse signal is adjusted to eliminate the timing shift. A synchronous circuit characterized by comprising phase control means for changing the phase.