JPS6320932A - Parity counter - Google Patents

Abstract

PURPOSE:To improve high-speed operation by employing a synchronizing system so as not to clear a JK flip-flop in a parity counter to prolong the holding time of a count value for the count result of data of a fraction of one multi-frame. CONSTITUTION:A reset pulse 5 is extracted from timing signals P-1-P-3 in an AND circuit 12' and fed to an OR circuit 14'. Furthermore, an AND circuit 13' with an inverting input uses the signal P-3 to extract only a data part 7 from an input signal as shown in waveform 6 and gives it to an OR circuit 14' and a terminal K of a JK FF 15'. Then the OR circuit 14' inserts a reset pulse (* mark in waveform 8) to a position of a bit M just before the start of parity count in the data part and gives the result to a terminal J, then a level 1 is fed respectively to the terminals J, K in case of the dotted lines (a). An inverter output 1 at the rising of the next clock is outputted as an odd number parity 9 and an even number parity 10 from a terminal Q, the output 0 inverted further in case of the dotted lines (b), the output 1 in case of the dotted lines (c) because of 1, 0 of reset levels, and the output 0 inverted further in case of the dotted lines (d) are outputted from the terminal Q in the respective cases as the odd and even number parities, thereby making the data holding time longer as from the leading of the clock to the rising of the next clock.

Description

[Detailed Description of the Invention] [Summary] By operating the parity counter in a synchronous manner without clearing the JK-flip-flop, ■ the holding time of the count value obtained by counting one multi-frame data can be extended. This improves the possibility of high-speed operation.

[Industrial application field]

The present invention relates to improvements in parity counters.

Parity counters are widely used to detect whether or not an error has occurred in a signal transmitted when transmitting a digital signal, and the case where it is used in a multiplexing/demultiplexing conversion device will be described below.

Figure 4 is an example of a block diagram of a multiplexing/demultiplexing conversion device.
El) is an example of a multiplex conversion device block diagram, and FIG. 4(b) is 3
An example of the frame format of the next group signal, FIG. 4 (C1 shows an example of a block diagram of the separation/conversion device).

In FIG. 4 (al), for example, 7 CH of secondary group signals of 6.312 Mb/s are multiplexed by the multiplexer 1, and additional bits such as the multi-frame first bit parity bit are inserted, and the signal is converted into 44.736 Mb. It is converted into a cubic group signal, and a part of it is added to the parity counter 3. Here, the number of 1's in the data part in the cubic group signal is counted for each multiframe, and the result is converted into a secondary group signal. The pulse generator 2 is inserted at a predetermined position in the signal.The pulse generator 2 is a part that supplies a necessary timing signal to the parity counter.

Also, as shown in Fig. 4(b), one multiframe is made up of, for example, seven frames, one frame is eight blocks, and one block is the data from the additional bits l-(M, G) to one bit before the next additional bit. Each frame is composed of 85 bits, and a multiframe head bit M is inserted at the head of one multiframe.

Next, as shown in FIG.
The count value counted by the parity counter 7 in increments of 1 multiframe 1 and the parity bit inserted into this signal are detected by the parity bit detection device 5, and the parity error detection device 6 compares the count value with the above count value. Although it monitors whether an error has occurred in the transmission path, the parity counter needs to operate normally at the highest possible speed.

[Conventional technology]

FIG. 5 is a circuit diagram of a conventional example, and FIG. 6 is a time chart of FIG. 5. The numbers on the left side of FIG. 6 indicate the waveforms of the portions with the same numbers in FIG. The operation shown in FIG. 5 will be explained below with reference to FIG.

First, the parity counter 10 shown in FIG. 5 is composed of a D-type flip-flop (hereinafter abbreviated as D-FF), and the parity counter 10 shown in FIG. Timing signal P- when input
Since 1, P-2, and P-3 are all set to 1, the parity counter 10 is cleared at this time by the output from the NAND circuit 9 (see FIG. 6--).

Furthermore, as shown in FIG. 6-■, the timing signal P-3 becomes 1 at the positions of the additional bits M and G, and becomes 0 at other positions, so the output of the NAND circuit 8 with a partial inversion input becomes P-. 3 is 1
．． Or, when the data in the input signal is O, it is 1, and the data is 1.
When , an inverted clock is output (see Figure 6-■).

Therefore, the parity counter 1 forming the divide-by-2 circuit
0, as shown in Figure 6-■, sends out an output whose state changes according to the rising edge of the input clock, that is, the number of 1s, from the terminal Q, for example, but as shown above, at the first bit h of the multiframe. Since the parity counter 6 is cleared and becomes O, the state of the previous bit (the part marked with a mark in Figure 6--) becomes the parity count value in one multiframe.

However, since this value must be inserted into the data or compared with extracted parity as described above, it must be latched by the latch circuit 11.

[Problem that the invention seeks to solve]

Here, the count value that the parity counter 10 counts the last 1 of one multiframe must be latched at the rising edge of the latch timer before this counter is cleared as described above, but the holding time of this count value is is the 6th
As shown in Figure 2, since the period from the falling edge of the lock to the rising edge of the next clock is short, there is a high possibility that latching will not be possible during high-speed operation, and there is a low possibility that normal operation will occur up to high speed.

[Means for solving problems]

As shown in FIG. 1, the above problem is solved by a reset pulse generating means 12 that uses a timing signal to generate a reset pulse that matches the bit immediately before the start of parity count in the input signal, and data extraction means 13 for extracting a data portion included in a signal; reset pulse insertion means I4 for inserting the output of the reset pulse generation means into the output of the data extraction means; the reset pulse insertion means and the data extraction means. This problem is solved by the parity counter of the present invention, which is initialized at the bit position immediately before the start of parity counting using the output of be done.

[Effect]

The present invention uses an input timing signal to insert a reset pulse generated by a reset pulse generating means 12 into a data portion extracted from an input signal by a data extracting means 13 using a reset pulse inserting means 14, and then the reset pulse is inserted. The data portion that has been inserted and the data portion that will not be inserted are added to the parity counting means 15, and each time the data portion becomes 1, it is counted up at the next clock, so that when a reset pulse is input, the initial value is set at the next clock. By doing so, the reset pulse is handled as data and clearing is not used, so the holding time of the parity count value is longer than the rising interval of the clock, increasing the possibility of normal operation up to high speeds.

〔Example〕

FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a time chart of FIG. 2. The numbers on the left side of FIG. 3 indicate the waveforms of the portions with the same numbers in FIG. Throughout the plan, the same symbols refer to the same objects, and the AND circuit 12°, the AND circuit 13' with a partially inverted input, the OR circuit 14', and the JK-flip-flop (hereinafter abbreviated as JK-FF) 159 are each reset. Pulse generation means 12, data extraction means 1
3. Components of reset pulse insertion means 14 and parity counting means 15 are shown.

The operation shown in FIG. 2 will be explained below with reference to FIG.

First, the input timing at AND circuit 12° (ε No. P
Reset pulses are taken out from -1, P-2, and P-3 and applied to the OR circuit 14' (see Figure 3-0 to 3).

Also, an AND circuit 13' with a partial inversion input extracts only the data part from the input signal as shown in Figure 3-■ using the timing signal P-3, and connects it to the OR circuit 14'' and the JK-FF.
15'' (see Figure 3-■), and then the OR circuit 14° applies a reset pulse (Figure 3-■) to the bit H position immediately before the start of parity counting in the data portion.
Since the part marked * in the middle is inserted and applied to the terminal J of the JK-FF 15', an output as shown in Figure 3-■ can be obtained from the terminal Q (see Figure 3-■). That is, when dotted line a, 1.1 is added to the J terminal, but at the rise of the 9th clock, the output l which is inverted from the previous state, and when dotted line A, the output l is further inverted and O is added to the dotted line. At C (reset), it is 1°0, so 1 is output, and at dotted line d, it is inverted and O is output from terminal Q (see Figure 3--■, ■).

Here, since the dotted line C is the beginning of one multiframe, the part marked by the three dotted lines becomes the parity count value of the previous multiframe, and this can be latched by a latch circuit (not shown) as in the conventional example, but data retention Since the time from the rising edge of the clock to the rising edge of the next clock is longer than in the conventional case, the possibility of normal operation up to high speed increases.

〔Effect of the invention〕

As described above in detail, the present invention has the effect of increasing the possibility of normal operation up to high speeds.

[Brief explanation of drawings]

Figure 1 is a Brodder diagram of the principle of the present invention. FIG. 2 is a circuit diagram of an embodiment of the present invention, Figure 5 is a circuit diagram of a conventional example. FIG. 6 shows a time chart for the fifth tooth. In the figure, 12 is a reset pulse generating means; 13 is a data extraction means; 14 is a reset pulse insertion means; 15 indicates parity counting means. Koguchiro's Principles 2nd Ward Kaya 1 diagram A small invention of real filter 4 ° J eyes y mouth Hand 2 flash Ushio ↑ 4 bound 11 Tomo Naka Hiragimaki l professional 77 Batomachi Kaya 4 ward

Claims (1)

[Scope of Claims] Reset pulse generating means (12) that uses a timing signal to generate a reset pulse that matches a bit immediately before the start of parity counting in an input signal; a data extracting means (13) for extracting a data portion that is generated; a reset pulse inserting means (14) for inserting the output of the reset pulse generating means into the output of the data extracting means; the reset pulse inserting means and the data extracting means parity counting means (15) that is initialized at the bit position immediately before the parity counting starts using the output of the input signal, and that counts only 1 data in the input signal. parity counter.