JPH0630480B2 - Speed conversion circuit - Google Patents

Description

The present invention relates to a speed conversion circuit in a receiver of a PCM multiplex transmission system.

[Conventional technology]

In PCM transmission, as in digital radio lines,
It can be classified into a dependent synchronization system and an independent synchronization system.
As for the data of the subordinate synchronization system, a plurality of data strings are synchronously sent from the transmitting side. A multiplexed signal is inserted into this data at regular intervals. The data of the independent synchronization system is sent from the transmission side in synchronization (stuff synchronization) by inserting a stuff pulse into a plurality of asynchronous data strings.

On the receiving side, a speed conversion circuit for separating and removing the multiplexed signal and the stuff pulse is provided, but conventionally, the speed conversion circuit is provided separately for the independent synchronization system and for the slave synchronization system.

[Problems to be solved by the invention]

Originally, the basic components of the speed conversion circuit, that is, the elastic memory for writing and reading data at different clock rates, the phase locked loop, etc. are the same for both independent and dependent synchronous systems. Nevertheless, providing a speed conversion circuit separately for both systems as in the prior art increases the system cost accordingly and is extremely unsuitable.

An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a speed conversion circuit on the receiving side of a PCM multiplex transmission system capable of selectively realizing any function for signals of both systems by one circuit.

[Means for solving problems]

In the present invention, on the receiving side of the PCM multiplex transmission system that transmits signals of both independent and dependent synchronization systems, the received data is written in the elastic memory by the clock extracted from the received signal, and the phase synchronized with the clock is written. A speed conversion circuit that is shared by both synchronous systems and is read by the clock of the synchronous oscillator is provided. This speed conversion circuit is a means for periodically generating a clock stop signal for prohibiting the input of the write clock and a means for reading the stuff information and whether or not the clock stop signal is generated at a specific timing depending on the output status. And a means for squeezing, and both of the means can be selected according to the signals of the slave synchronization system and the independent synchronization system.

[Action]

Although the basic operation of the speed conversion circuit according to the present invention is the same as that of the conventional speed conversion circuit, a multiplexed signal is periodically inserted in the signal of the slave synchronization system as an input signal. , A stuff pulse is inserted at a specific timing. In the circuit of the present invention,
By independent selection, it is possible to change the generation method of the clock stop signal for prohibiting the writing clock of the elastic memory.

As a result, it is possible to separate and remove the multiplexed signal in the slave synchronous system and the stuff pulse in the independent synchronous system to perform the speed conversion.

〔Example〕

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit block diagram and FIG. 2 is a time chart. In this embodiment, the data is in one column for convenience. It goes without saying that it is also applicable to a plurality of columns.

In FIG. 1, the elastic memory 106 includes a frequency divider 101 to which the first clock (clock extracted from the received signal) 11 and a second clock (frequency clock of the phase-locked oscillator 110 of the phase-locked loop) 20 are input. The input divider 10 controls writing of the input data 10 and reading of the output data 50. First clock 11 and second
A phase comparison circuit 103 performs phase comparison with the clock 20, and a loop filter 109 and a phase-locked oscillator 110 are used.
Are synchronized by a phase locked loop consisting of The first clock 11 is blocked at the gate 100 when there is a clock stop signal 43.

In the previous stage of this circuit, the first clock 11
And the frame sync pulse 30 are extracted. The frame sync pulse 30 is input to the frame timing generation circuit 104, and the multiplexed signal timing pulse 40 and the stuff timing pulse 41 are generated from the clock of the first clock 11. The stuff pulse is periodically put in a fixed position indicated by the stuff timing pulse 41. Whether the stuff pulse is actually inserted or not is determined by the input data 10
It is transmitted as stuff information in. The stuff information reading circuit 105 makes the judgment and outputs a judgment signal 42 indicating whether or not the stuff pulse is actually inserted. In this embodiment, the discrimination signal 42 becomes low level when the stuff pulse is inserted.

The subordinate / synchronous system is selected by the selection switch 107, and the control circuit 108 controls the frame timing generation circuit 10.
The multiplexed signal timing pulse 40, which is the output from
The stack timing pulse 41 is input and the clock stop signal 43 is output.

The circuit operation of the present invention will be described below. As shown in FIG. 2, it is assumed that the input data 10 has a multiplexed signal inserted every N bits in one frame. First, the case where a signal of the slave synchronization system is input will be described. The selection switch 107 is tilted to the ground (E) side. Since the ground signal is input to the control circuit 108, the control circuit 108 periodically outputs the clock stop signal (negative signal) 43 according to the multiplexed signal timing pulse 40 regardless of the stack timing pulse 41. To do. As a result, the gate 100 periodically prohibits clock input.
The multiplexed signal is not written to the elastic memory 106. Therefore, if the elastic memory 106 is sequentially read out, the output data 50 are arranged by N-1 bits, and the speed conversion on the receiving side is performed. In this way, the speed conversion circuit for the slave synchronization system is realized.

Next, the case of the signal of the independent synchronization system will be described. In this case, a signal obtained by inserting a stuff pulse and performing stuff synchronization is input. The selection switch 107 is tilted to the T side, and the discrimination signal 42 which is the output of the stack information reading circuit 105 is input to the control circuit 108. At the timing of the stuff timing pulse 41, the discrimination signal 4
The speed conversion circuit for the independent synchronization system is realized because it is determined whether or not the clock stop is performed based on the result of 2.

〔The invention's effect〕

As described above in detail, the circuit of the present invention is a speed conversion circuit commonly used for the slave synchronization system and the independent synchronization system, and can be arbitrarily changed by the switch switching setting. Therefore, compared with the case where two types of circuits are designed and manufactured for use, the system cost related to design and production can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and FIG.
The figure is a time chart showing waveforms at various portions of the circuit of the present invention. 10 ... Input data, 11 ... First clock, 20 ...
2nd clock, 30 ... Frame sync pulse, 40 ...
Multiplexed signal timing pulse, 41 ... Staff timing pulse, 42 ... Discrimination signal, 43 ... Clock stop signal, 50 ... Output data (speed conversion data), 100
...... Gate, 101, 102 ...... divider, 103 …… phase comparison circuit, 104 …… frame timing generation circuit, 105 …… staff information reading circuit, 106 …… elastic memory, 107 …… selection switch, 108 ... Control circuit, 109 ... Loop filter, 110 ... Phase-locked oscillator.

Claims (1)

[Claims] 1. A receiving side of a PCM multiplex transmission system for transmitting a signal of a slave synchronization system / independent synchronization system, stores received data in response to a write clock, and responds to a read clock in phase synchronization with the write clock. An elastic memory for reading the stored data, a frame timing generation circuit for generating a multiplexed signal timing pulse and a stuff timing pulse in response to a clock pulse and a frame synchronization pulse extracted from the received signal, and a stuff information in the received data A determination circuit for determining and generating a determination signal indicating whether or not the stuff pulse is actually inserted, and a clock stop signal in response to the multiplexed signal timing pulse when designated as the slave synchronization system. Designated as the independent synchronization system Control means for generating a clock stop signal in response to the stuff timing pulse, the discrimination signal and the multiplexed signal timing pulse, and prohibiting the output of the clock pulse when the clock stop signal is generated. Gate means for permitting output of the clock pulse when the clock stop signal is not generated, and means for generating the write clock in response to the pulse output from the gate means,
A speed conversion circuit comprising means for generating the read clock.