JPH0783331B2 - Large-scale integrated circuit sharing method for demultiplexing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a time division multiplex communication device conforming to the CEPT digital hierarchy according to the CCITT recommendation, and more particularly to an internal demultiplexing circuit of the device (hereinafter, DMUX Abbreviated)).

[Prior Art] Conventionally, this type of large-scale integrated circuit (hereinafter abbreviated as LSI)
Is an LSI that separates from 8.448MHz to 2.048MHz, and 34.368MHz
From 8.48MHz to 8448MHz, designed separately and independently,
It was developed and commercialized.

Here, 8.448MHz, 2.048MHz, and 34.368MHz are 8M, 2M, and 34M, or 8Mb / s, 2Mb / s for simplicity, respectively.
s and 34 Mb / s.

One set of 8 Mb / s signals according to the CCITT recommendation mentioned above contains 4 sets of 2 Mb / s signals, and each set contains 2 sets.
It consists of 12 bits. Further, of the 4 sets of signals, a 10-bit frame signal (frame palace) is arranged in the head set, and 4 bits are placed in the head of each of the remaining sets.
A bit justification control signal is arranged.

On the other hand, one set of 34 Mb / s signals contains 4 sets of 8 Mb / s signals, and each set consists of 384 bits. A 10-bit frame signal (frame palace) is arranged in the head of the four sets, and a 4-bit justification control signal is arranged in the head of each of the remaining sets.

Thus, according to the present invention, the two signals to be demultiplexed have different frame configurations in the number of bits and frame length in each set, but the number of frame pallets and the number of sets of signals to be separated. Are the same. In consideration of this, first, the 8M / 2M DMUX and 34M / 8M DMUX which have been conventionally used will be described below.

FIG. 5 shows a conventional technology of 8M / 2M DMUX.

In the conventional technique, the 8 Mb / s signal 5 ₁ is _first decoded (5 ₃₎ by the decoding circuit 5 ₂ . It performs synchronization determination in the synchronization detection circuit 5 _4, using the result 5 ₅ to control the operation of 8M counter 5 _6. Its output 5 ₁₀ of the counter is given to the DMUX circuit 5 _11, in DMUX circuit 5 ₁₁ separates the output 5 ₃ of the decoding circuit.
Thereafter the buffer memory 1 _12, is changed to four respective unique frequency 5 _{13-5 16} output.

FIG. 6 shows the prior art of 34M / 8M DMUX. Exactly the same as Figure 5, are different only 34M counter 6 ₇ parts.

[Problems to be Solved by the Invention] As described above, in the conventional LSI described above, the 8M / 2M DMU is used.
Since the LSI for X and the LSI for 34M / 8M DMUX were made independently, the development cost was enormous, and the number of types of parts also increased, which was a drawback of having manufacturing complexity. There is.

Therefore, the technical problem of the present invention is 8M / 2M in view of the above-mentioned drawbacks.
It is to provide a large-scale integrated circuit sharing system for demultiplexing that allows two types of functions of a DMUX LSI and a 34M / 8M DMUX LSI to be performed by one type of LSI.

[Means for Solving the Problems] According to the present invention, a frame formed by a plurality of sets of low-order group signals is received, and one high-order group signal that has undergone predetermined coding is received, and the plurality of sets A large-scale integrated circuit for demultiplexing that separates signals of a low-order group is provided, and a high-order group signal of a first kind and a second kind having a different number of bits and bit rates and having frame pulses at the same position is provided. In the method for sharing the large-scale integrated circuit for demultiplexing, by decoding the one high-order group signal and detecting the frame pulse,
A detecting means for detecting synchronization with respect to a high-order group signal of a book, and a number of bits of the first-type high-order group signal of the one high-order group signal, which is connected to the detecting means, is counted according to its bit rate, A first counter means for outputting a first timing signal corresponding to a frame of a first-order high-order group signal and a low-order group signal set; and a high-order group signal connected to the detection means and of the one high-order group signal, Second counter means for counting the number of bits of the second-type high-order group signal according to the bit rate and outputting a second timing signal corresponding to the frame of the second-type high-order group signal and the low-order group signal set; Selecting means for receiving one of the first and second timing signals and externally controlling one of the first and second timing signals, and transmitting the selected one as an output timing signal. Separation means for receiving the decoded one high-order group signal and the output timing signal, and separating the decoded one high-order group signal into a plurality of low-order group signals according to the output timing signal; And a means for receiving the plurality of low-order group signals and the output timing signal and outputting the separated plurality of low-order group signals at a predetermined bit rate. A large scale integrated circuit sharing system can be obtained.

Further, according to the present invention, the first and second counter means are constituted by one (2M / 8M) / (8M / 34M) shared counter, and a large-scale integrated circuit for demultiplexing is provided. A shared system can be obtained.

That is, according to the present invention, DMUX from 8.448MHz to 2.048MHz
Dedicated LSI (abbreviation for Demultiplex; same below) and D (34.368MHz to 8.448MHz) with LSI (abbreviation for large-scale integrated circuit;
In the LSI for MUX, only the means for recognizing and DMUXing the bit string according to the 8.448MHz frame structure and the means for recognizing and DMUXing the bit string according to the 34.368MHz frame structure, respectively, or A common counter for recognizing and DMUXing bit strings according to the two different frame configurations is independently present, and means for switching them by external control is provided, and the other DMCODER section, synchronization detection section, and memory section are Demultiplexing ((Demultiplex) (8M / 2M DMUX, 34M / 8M DMUX) is configured so that one LSI can use both 8M / 2M DMUX and 34M / 8M DMUX.
A large scale integrated circuit sharing system for x) can be obtained.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

-First Embodiment- Fig. 1 shows a first embodiment of the present invention.

First, the high-order group input signal shown by 1 ₁ (when using 8M / 2M DMUX
8.448Mb / s, 34.368Mb / s when using 34M / 8M DMUX) HDB 3
It is decoded by the decoding circuit 1 ₂ . Signal 1 ₃ decoded is synchronized by the synchronization detecting circuit 1 _4, by providing the synchronization signal 1 ₅ into two counter 1 _6, 1 _7, only during synchronization, control such counter operates To be done.

On the other hand, these two types of counters are composed of a counter ₁₆ for counting the frame structure of 8M and a counter ₁₇ for counting the frame structure of 34M, and a first external control signal 1 for switching between them. Based on ₉ , selector 1 ₈ outputs those
It is selected 1 _10.

The extraction the low-order group signal circuit 4 the signal 1 ₃ DMUX circuit 1 ₁₁ which is decoded and separated, then the buffer memory 1 _12, the output after four each converted to a unique frequency 1 ₁₃ to 1 ₁₆

As is clear from the above description, the output timing signal from the counter 1 ₆ or 1 ₇ is output to the selector 1 ₈ without changing the configurations of the DECODER 1 ₂ , the sync detection 1 ₄ , the DMUX 1 ₁₁ , and the buffer memory 1 _12. 2 by switching with
One of one of the higher order group signal 1 ₁ having a different bit rate can be a plurality of low-order group signal set separation.

-Second Embodiment-Fig. 2 shows a second embodiment in which the first embodiment is further improved. The improvement is that two types of counters ₁₆ and ₁₇ are used separately, and instead of counting the frame configuration of 8M and 34M, it is replaced with one (2M / 8M) (8M / 34M) shared counter (26). By controlling the second external control signal 2 _9, it is characterized in that to fulfill their respective functions. An example of how this 8M / 34M shared counter _{26 is} implemented is shown in FIG.

Note that the 8M counter ₁₆ and the 34M counter ₁₇ require a 4 × 53 × 4 counter and a 4 × 96 × 4 counter, respectively, according to the CCITT recommendation, and the example shown here is 53/96. It is an example of a common counter.

-Third Embodiment- Furthermore, the counter shown in FIG. 4 is an improved example of the second embodiment. This is a block in which the selector section and the flip-flop in FIG. 3 are formed in the same block. As a result, the number of LSI design gates can be reduced and the signal delay time can be shortened.

[Effects of the Invention] As described above, the present invention is very similar to the separation method.
In the separation circuit of 8M / 2M DMUX, 34M / 8M DMUX, the common circuit components use the same circuit, and only the 8M counter and 34M counter circuit parts which must be different circuits must be independent, or one Independently configured as a counter and provided with a function to switch it by external control
LSI used for 8M / 2M DMUX, 34M / 8M DMUX devices
Is being shared.

As a result, according to the present invention, since only two types of LSIs need to be developed, which is conventionally required to develop two types of LSIs for 8M / 2M DMUX and 34M DMUX, a large reduction in development cost can be achieved.
In addition, the manufacturing cost can be reduced by reducing and unifying the component parts, and at the same time, the mass production effect of the LSI can be expected, so that the unit price of the LSI itself can be reduced.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention, FIG. 2 is a second embodiment which is an improved example of FIG. 1, FIG. 3 is a concrete example of the common counter of FIG. 2, and FIG. 4 is FIG. Third embodiment, which is an improvement example of
FIG. 6 shows a conventional example of 2M / 8M DMUX, and FIG. 6 shows a conventional example of 8M / 34M DMUX. 1 ₁ …… High-order group input signal (when using 8M / 2M DMUX; 8,448Mb / s, 3
When using 4M / 8M DMUX; 34,368Mb / s, 1 ₂ ...... HDB 3 decoding circuit, 1 ₃ ...... High-order group input decoded signal, 1 ₄ ...... Sync detection circuit, 1 ₅ ...... Sync detection signal , 1 ₆ …… Counter for 8M / 2M DMUX (when using 8M / 2M DMUX), 1 ₇ …… Counter for 34M / 8M DMUX (when using 34M / 2M DMUX), 1 ₈ …… Counter output selection circuit (selector) , 1 ₉ …… Selector control signal, 1 ₁₀ Selected counter output signal, 1 ₁₁ …… DMUX circuit, 1 ₁₂ ……
Buffer memory, 1 ₁₃ to 1 ₁₆ ... Low-order group output (8M / 2M DMUX
When using; 2.048Hb / s, when using 34M / 8M DMUX; 8.448Mb / s), 2 ₁
...... High-order group input signal (8.448Mb / s; when using 8M / 2M DMUX, 34,
368Mb / s; 34M / 2M DMUX used), 2 ₂ ...... HDB 3 decoding circuit, 2 ₃ ...... High-order group input decoded signal, 2 ₄ ...... Sync detection circuit, 2 ₅ ...... Sync detection signal , 2 ₆ …… (2M / 8M) (8M /
34M) Shared counter, 2 ₉ ...... Selector control signal, 2 ₁₀ Selected counter output signal, 2 ₁₁ …… DMUX circuit, 2 ₁₂ …… Buffer memory, 2 ₁₃ 〜 2 ₁₆ …… Low-order group output signal (2.048 Mb /
s; 8M / 2M DMUX used, 8.448Mb / s; 34M / 2M DMUX used),
5 ₁ …… 8.448 Mb / s input signal, 5 ₂ …… HDB 3 decoding circuit, 5 ₃
…… HDB 3 Decoded 8.448Mb / s signal, 5 ₄ …… Synchronous detection circuit, 5 ₅ …… Synchronous detection signal, 5 ₆ …… 8M / 2M DMUX counter, 5 ₁₀ …… Counter output signal, 5 ₁₁ …… DMUX circuit, 5 ₁₂
...... Buffer memory, 5 _{13 to} 5 ₁₆ ...... 2.048 Mb / s output signal, 6 ₁ ...... 34.368 Mb / s input signal, 6 ₂ ...... HDB 3 decoding circuit, 6 ₃ ...... HDB 3 decoded 34.368Mb / s, 6 ₄ …… Synchronous detection circuit, 6 ₅ …… Synchronous detection signal, 6 ₇ …… 34M / 2M DMUX counter, 6 ₁₀ …… Counter output signal, 6 ₁₁ …… DMUX circuit, 6 ₁₂ … … Buffer memory, 6 _{13 to} 6 ₁₆ …… 8.448 Mb / s output signal.

Claims (2)

[Claims] 1. A demultiplexer having a frame formed by a plurality of sets of low-order group signals, receiving one high-order group signal which has been subjected to predetermined coding, and separating the plurality of sets of low-order group signals. A large-scale integrated circuit for demultiplexing, which is provided with a large-scale integrated circuit for plex, has a different number of bits and a different bit rate, and has high-order group signals of the first and second types having frame pulses at the same position. In the method of sharing the above, the one high-order group signal is decoded,
Detecting means for detecting synchronization with the one high-order group signal by detecting the frame pulse; and a bit of a first-type high-order group signal of the one high-order group signal connected to the detecting means. A first counter means for counting the number according to the bit rate and outputting a first timing signal corresponding to the frame of the first-order high-order group signal and the low-order group signal set, and connected to the detection means. At the same time, of the one high-order group signal, the number of bits of the second-type high-order group signal is counted according to its bit rate, and the second type corresponding to the frame of the second-type high-order group signal and the low-order group signal set. Second counter means for outputting a timing signal, receiving the first and second timing signals, and selecting one of the first and second timing signals by external control Selecting means for transmitting as an output timing signal, one decoded high order group signal and the output timing signal, and receiving the decoded one high order group signal according to the output timing signal. Means for receiving a separating means for separating into the next group signal, the plurality of separated low order group signals and the output timing signal, and outputting the separated plurality of low order group signals at a predetermined bit rate. A large-scale integrated circuit sharing system for demultiplexing characterized by having. 2. A demultiplexer having a frame formed by a plurality of sets of low-order group signals, receiving one high-order group signal having undergone predetermined coding, and separating the plurality of sets of low-order group signals. A large-scale integrated circuit for demultiplexing, which is provided with a large-scale integrated circuit for plex, has a different number of bits and a different bit rate, and has high-order group signals of the first and second types having frame pulses at the same position. In the method of sharing the above, the one high-order group signal is decoded,
Detecting means for detecting synchronization with the one higher-order group signal by detecting the frame pulse; and connecting to the detecting means, and performing an operation according to a higher-order group signal designated by external control. The bit string of the high-order group signal is selectively counted at the bit rate corresponding to the specified high-order group signal, and the frame of the high-order group signal specified by external control and the timing signal corresponding to each low-order group signal set are generated. A counter means for outputting, a separating means for receiving the decoded one high-order group signal and the timing signal, and separating the decoded one high-order group signal into a plurality of low-order group signals according to the timing signal. And a plurality of separated low-order group signals and a timing signal, and the separated plurality of low-order group signals are subjected to a predetermined bit rate. Large scale integrated circuits sharing scheme for demultiplexed, characterized in that it comprises a means for outputting.