JP2507678B2 - Time division demultiplexer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a time division demultiplexer, and particularly to a high-order group frame when demultiplexing diversified information and when multiplex relay is required. The present invention relates to a time division demultiplexing device capable of extracting information of a low-order group frame multiplexed into a high-order group frame by using a high-order group clock for. Further, even when the frame structure has a variable position with respect to the high-order group frame in which the head of the information of the low-order group frame is variable, the high-order group clock for the high-order group frame is used to The present invention relates to a time division demultiplexer capable of extracting information of a next group frame.

[Conventional technology]

Conventionally, as this type of apparatus, there has been a time division demultiplexer shown in FIG. This figure is shown in a conventional example of Japanese Patent Laid-Open No. 63-10833, and in the figure, (1) and (2) are time division demultiplexers (hereinafter abbreviated as TDM),
(3) and (4) are data line terminators (hereinafter
DCE), (5a) to (5d) are buffers, (6) and (7) are shift registers (S).
R) and (8) are synchronization signal generating circuits (SYN), (9) is a control unit, and (10) and (11) are shift registers (S).
R), (12a) to (12d) are AND circuits, (13a)
(13d) is a buffer, (14) is a synchronization signal check circuit (DET), and (15) is a control unit.

 Next, the operation will be described.

As an example of conventional general TDM, as shown in FIGS. 2 (a) and 2 (b), a case will be considered here in which frame synchronization pulses are multiplexed by 1 bit for every 4 bits, for example, by 4-bit multiplexing. The transmission signal is input to the TDM (1) on the transmission side at a speed that is 5 times slower than the multiple acceleration, and in the TDM (1), the synchronization signal F, channel A, channel B, channel C, and channel D are switched by the switch mechanism. Second
Arrange as shown in Figure (b) and send in serial format,
The TDM (2) on the receiving side converts each channel data into a parallel signal and outputs it by a similar switch mechanism.

An example of a conventional TDM circuit configuration is shown in FIG. 2 (c).
As shown in (4), on the transmitting side, the data of the respective channels A to D are input to the buffers (5a) to (5d), respectively, and further input to the shift registers (6) (a) to (d) in parallel.

The shift register (6) is an output clock of the control unit (9)
The signal is launched in the order of channel A → channel D by CLK, and the signal launched in the shift register (7) is added with the synchronizing signal F output from the synchronizing signal creating circuit (8) and sent to the line.

On the receiving side, the received serial format signal is input to the shift register (10) and sequentially shifted (d) → (a) by the output clock of the control unit (15), and the data of each channel is regular. When shifted to the position, AND circuits (12a) to (12d) open and the buffer (13
a) to (13d).

The received signal is sent to the sync signal check circuit (14) via the shift register (11), where the sync signal F
Is detected and a clock CLK synchronized with the synchronizing signal F is output from the control section (15).

Next, a configuration in which the conventional general TDM shown in FIG. 2 is further multiplexed will be described with reference to FIGS. 3 and 4.

In FIG. 3, the multiplexing circuits 300a, 300b, 300c, 300d, 30
0e corresponds to the TDM (1) shown in FIG. 2 (a), and the demultiplexing circuits 500a, 500b, 500c, 500d, 500e correspond to the TDM (2) shown in FIG. 2 (a). . Also, A, B, C, ..., R
Is a channel. # 1, # 2, # 3, and # 4 are multiplexed channel numbers.

As described above, the multiplexing circuit 300a includes channels A,
Channel B, channel C, and channel D are arranged. The multiplexing circuit 300b has channels G to J, the multiplexing circuit 300c has channels K to N, and the multiplexing circuit 300d.
, Channels O to R are arranged respectively. In addition, the multiplexed outputs from the multiplexing circuits 300a to 300d are
It becomes an input to the multiplexing circuit 300e.

 FIG. 4 is a diagram showing an example of a frame structure.

Arrangement 100-110 of channel # 1 shown in FIG.
Is the same as the arrangement shown in FIG. 2 (b), and as described above, is sequentially output in the serial format. Where the fourth
The frame shown in FIG. 7A is called a low-order group frame LF. Similarly, the output from the multiplexing circuit 300b is the arrangement 120 to 130 of the channel # 2, the output from the multiplexing circuit 300c is the arrangement 140 to 150 of the channel # 3, and the output from the multiplexing circuit 300d is the channel # 2. 4 arrangement 160-170. These channels # 1 to # 4 are further multiplexed by the multiplexing circuit 300e in the same operation as that described above, and the fourth
The arrangement is such that 25 bits shown in FIG. 7B are set as one frame. Here, the frame shown in FIG. 4 (b) is referred to as a high-order group frame HF. The high-order group frame is a low-order group frame multiplexed for each bit or for each plurality of bits. In the high-order group frame shown in FIG. 4 (b), the low-order group frame shown in FIG. 4 (a) is multiplexed bit by bit, and the frame bit F is inserted every 5 bits.
It shows the case where 1 frame = 25 bits. In the high-order group frame shown in FIG. 4B, the frame bits F # 1, F # 2, F # 3, F # 4 of the low-order group are arranged in one frame first. Next, the first bit A1 of channel # 1, the first bit G1 of channel # 2, the first bit of channel # 3
K1, the first bit O1 of channel # 4 is arranged, the second bit B1 of channel # 1 and the second bit H of channel # 2
Place 1, ... And finally # 1 to # 4 of each channel
The fourth bit D1, J1, N1, R1 of the above is arranged, and this frame is terminated at the fifth bit R1 of channel # 4. The second and subsequent frames also follow this arrangement. That is, F # 1, F # 2, F # 3,
F # 4, A2, G2, K2, O2, B2, H2, ..., N2, R2.

In this way, in order to perform multiplexing in two steps,
As shown in FIG. 3, the multiplexing circuit and the demultiplexing circuit also have 2
Stage required. Further, each of the multiplexing process and the demultiplexing process has two stages. At this time, the multiplexing circuits 300a to 300d and the demultiplexing circuits 500a to 500d are connected to the low-order group circuit and the multiplexing circuit 30a.
The 0e and the demultiplexing circuit 500e are called high-order group circuits. Further, the clock speed is different between the frames before and after the multiplexing, and the operating clock speed is also different between the low-order group circuit and the high-order group circuit. That is, the low-order group circuit operates with a low-speed low-order group clock. The high-order group circuit operates with a high-speed high-order group clock.

Also, FIG. 4 (c) shows a multiplexed high-order group frame.
This is a type of HF, and when the beginning of the information of the low-order group frame is a variable position, a pointer PT indicating the variable position.
An example of a higher order group frame HFP with 1 to PT4 is shown. In the high-order group frame HFP shown in FIG. 4 (c), PT1 to PT
Reference numeral 4 is a pointer for channels # 1 to # 4. For example, PT1 indicates B1, indicating that the beginning of the information of channel # 1 is B1.

Information processing when a conventional time division demultiplexer is used will be described below.

When processing the desired information, it is necessary to take out the desired information from the multiplexed frame. Therefore, the high-order group frame is once received by the demultiplexing circuit 500e, demultiplexed into low-order group frames, and further, any desired information is demultiplexed from the low-order group frame by any of the demultiplexing circuits 500a, 500b, 500c, 500d. I had to do it. Therefore, in order to extract the desired information, it is necessary to perform a two-step process of separating the multiplexed data by the high-order group circuit and further extracting it by the low-order group circuit. In addition, when the relay device extracts additional information for transmission line maintenance, etc. as desired data and then multiplexes and transmits the updated additional information for transmission line maintenance, etc., the low-order group circuit is used. It was necessary to multiplex the data and further to multiplex the data by the high-order group circuit. Thus, in order to extract the desired information from the multiplexed data, multi-step separation is required. When relaying multiplexed data, for example, like a relay device, processing is performed on additional information included in the multiplexed data for transmission path maintenance and the like. In case,
In addition to separating multiplexed data in multiple stages,
I had to multiplex and relay again.

[Problems to be Solved by the Invention]

Since the conventional time division demultiplexing processing system is configured as described above, it is necessary to perform multistage demultiplexing processing in order to obtain desired information from the higher-order group frame. Further, in the case of multiplexing and relaying a high-order group frame as in a relay device, in order to obtain desired information from the high-order group frame, it is necessary to perform the multiplexing again using the multiplexing circuit shown in the conventional example. There was a problem of causing an increase in Furthermore, CCITT Recommendation G707, as shown in FIG. 4 (c),
As in the case of processing NNI (Network Node Interface) standard frames shown in 708 and 709, the beginning of the information of the low-order group frame that contains the desired information is a variable position with respect to the multiplexed high-order group frame. In that case, the conventional method has a problem that the circuit is increased and becomes complicated.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a time division demultiplexer capable of reducing the circuit scale when not only demultiplexing but also multiplexing relay is required. To do. It is another object of the present invention to provide a time division demultiplexer capable of reducing the circuit scale even when the information head can take a variable position with respect to a higher-order group frame.

[Means for solving the problem]

This invention inputs a count value of a high-order group frame counter that counts data of a high-order group frame, and a count value of the high-order group frame counter,
A high-order group decoder that outputs a signal indicating the beginning of the data of the low-order group frame in the high-order group frame and a signal indicating the validity of the data, and a signal indicating the beginning of the data and a signal indicating the validity of the data are input. Input the count value of the low order group address counter and the low order group address counter that counts the data of the low order group frame,
Detect the desired data position based on the count value,
A low-order group decoder that outputs an output enable signal indicating a detected data position, the high-order group frame, and an output enable signal of the low-order group decoder are input, and desired data is output from the high-order group frame by the output enable signal. And a processing circuit for acquiring.

The low order group address counter, the low order group decoder and the processing circuit operate at the same clock speed as the high order group frame counter and the high order group decoder.

Further, the high-order group frame has a pointer indicating the head of the data in the low-order group frame, and the high-order group decoder outputs a signal indicating the head of the data based on the value of the pointer.

[Action]

In the present invention, for each channel, a low-order group address counter having a count enable terminal for inputting a signal indicating the validity of data and a count reset terminal for inputting a signal indicating the beginning of data and a desired data A low-order group decoder that outputs an output enable signal indicating a position is provided, and the processing circuit directly processes the information of each channel from the high-order group frame without converting it into the low-order group frame. The low-order group address counter and the low-order group decoder operate on the high-order group clock, the low-order group address counter performs counting when valid data arrives for each channel, and the low-order group decoder outputs when desired data arrives. Enable the enable signal.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. In this embodiment, it is assumed that the time division demultiplexing device is a relay device that relays the multiplexed information, and the desired information processed by this relay device is the transmission line maintenance information added to each channel. As described below. The transmission line maintenance information is also called additional information. The frame structure processed in this embodiment is the low order group frame LF and the high order group frame HF or HFP shown in FIG.
The configuration is as follows. Therefore, the multiplexed channel number is # 1.
Exists up to # 4 (n = 4).

FIG. 1 is a block diagram of a time division demultiplexer according to the present embodiment. In the figure, (21) is a high-order group frame HF or
Higher-order group frame counter (hereinafter referred to as frame counter) that counts the number of bits in the HFP frame, (22)
Is a high-order group decoder (hereinafter referred to as a decoder) that decodes the count value of the frame counter (21), (23) is a pointer processing circuit used for pointer processing of a high-order group frame HFP having pointers, (24a), (24b) are selection switches , (25) is a low-order group address counter that counts the number of bits in the low-order group frame, a low-order group address counter provided with a reset terminal and a count enable terminal, and (26) is this low-order group address. A low-order group decoder (hereinafter referred to as a decoder) that decodes the count value of the counter (25), (27a), (27b), ...
(27n) is an additional information terminating / generating circuit for processing the transmission line maintenance information defined for each of the n channels by the output enable signal from the decoder (26) of each channel,
(28a), (28b), ..., (28n) are buffer circuits for performing conversion from a high-order group frame to a low-order group frame and changing to a low-order group clock. Frame counter (21), decoder (22), pointer processing circuit (23), low-order group address counter (25), low-order group decoder (26),
Additional information termination / generation circuit (27a), (27b), ...
(27n) operates by a high-order group clock (not shown).

 Next, the operation will be described.

Higher-order group frame HF or shown in FIG. 4 (b) or (c)
HFP is a synchronization signal check circuit (14) as a reception signal.
Where the sync signal is detected by methods known in the art. By synchronizing with this synchronizing signal, the frame counter (21) synchronizes with the received signal and counts the number of bits of the higher-order frame. Decoder (22)
Decodes the count value of the frame counter (21) to generate a frame synchronization position verification pulse and sends it to the synchronization signal check circuit (14) to maintain frame synchronization. The decoder (22) also includes a low-order group address counter (25) and a decoder (2) according to the data position of each channel.
A reset pulse R for controlling 6) and a count enable pulse E are generated. Further, when the head of the information of the low-order group frame can take a variable position with respect to the high-order group frame by a pointer or the like like the high-order group frame HFP, the decoder (22) determines the position of the pointer indicating this variable position. A pulse for notification is generated and passed to the pointer processing circuit (23).

For the selection switches (24a) and (24b), the beginning of the information of the low-order group frame that contains the desired information is fixed in the case where it is a high-order group frame HFP that can take a variable position with respect to the high-order group frame. This is a selection switch provided to switch and process the HF case of the higher-order group frame, and when the head of the lower-order group frame can take a variable position with respect to the higher-order group frame by a pointer, like the high-order group frame HFP. Selects the control of the low-order group address counter (25) and the decoder (26) by the reset pulse R and the count enable pulse E output from the pointer processing circuit (23), and the low-order group like the high-order group frame HF is selected. If the beginning of the frame is fixed, select to select control by the reset pulse R and count enable pulse E output from the decoder (22) It is a switch.

A plurality of low-order group address counters (25) are provided corresponding to the multiplexed channels # 1 to # 4. Also, a plurality of decoders (26) are provided corresponding to the multiplexed channels # 1 to # 4. The reset pulse R and the count enable pulse E described above are separately output from the decoder (22) or the pointer processing circuit (23) to each of the low-order group address counters # 1 to # 4. Low order group address counters # 1 to # 4 (# 2, # 3 and # 4 are not shown)
Is a reset pulse R and a count enable pulse E
The number of bits of the low-order group frame of each channel is counted in accordance with the multiplexed channels # 1, # 2, # 3, # 4, .... For example, the decoder (22) outputs the reset pulse R at the time of the synchronizing signals F (200) and (225) for each frame in FIG. 4 (b), and F # 1 (201), A1 (206), B1
At the time of (211), C1 (216), and D1, the count enable pulse E indicating that the data of the channel # 1 is valid is output. The low-order group address counter # 1 uses the channel #
The counter is advanced by the count enable pulse E indicating that the data of 1 is valid. The low-order group address counter # 1 resets the count by the reset pulse R indicating the leading position of the data of the channel # 1. The count enable pulse E and the reset pulse R are output from the decoder (22) in the case of the high-order group frame HF. Alternatively, in the case of the high-order group frame HFP, it is output from the pointer processing circuit (23). The count enable pulse E and the reset pulse R are input to the count enable terminal and the reset terminal of the low-order group address counter (25),
Controls counting operation. As described above, the low-order group address counter (25) and the decoder (26) are separately provided for each multiplexed channel. Each low-order group address counter (25) and decoder (26) operate separately in synchronization with the head position of the data of each multiplexed channel. The count value of the low-order group address counter (25) is input to the decoder with output enable terminal (26). The decoder (26) stores in advance which data of the low-order group frame LF is the desired data, and the output enable for terminating and generating the transmission path maintenance information provided for each multiplexed channel. Generate a pulse. Output enable pulse is added information termination / generation circuit (27a), (27b) ,.
.., (27n) will be sent. For example, when the channel A of the multiplexed channel # 1 is the channel of the transmission path maintenance information, the decoder (26) sends the output enable pulse to A1 (206), A2 (231), A3, Output at A4 ...

The additional information terminating / generating circuit (27a) processes the maintenance information corresponding to channel # 1 in the higher-order group frame input as the received signal based on the output enable pulse of the decoder (26). The additional information termination / generation circuit (27b)
Of the output data (higher-order group frame) of the additional information termination / generation circuit (27a), the maintenance information corresponding to the channel # 2 is stored in the lower-order group address counter # 2 (not shown in FIG. 1) and the decoder # 2 (first order). Processing is performed based on the output enable pulse (not shown in the figure). Hereinafter, similarly, processing is performed up to the nth channel. Since the circuit of this embodiment operates with the high-order group clock, the additional information termination / generation circuit (27
When the data in which the additional information of all the channels has been processed by a), (27b), ..., (27n) is to be multiplexed and relayed, it is output from the multiplexed relay output X. That is, the high order group frame is directly output from the multiplexed relay output X without demultiplexing again after demultiplexing the high order group frame as in the conventional case. When demultiplexing output is required, buffer (28
Separated by a), (28b), ..., (28n). The higher-order group frame HF or HFP has buffers (28a), (28
b), ..., (28n), and separated for each channel by an output enable pulse from a decoder (26) indicating a valid data position for each channel. The buffer performs processing such as speed conversion to the low-order group frame and transfer to the low-order group clock, and outputs the data of the low-order group frame to channels # 1, # 2, ..., #n. .

In this embodiment, a low-order group address counter (25) with a count enable terminal and a reset terminal and a decoder (26) for outputting an output enable pulse are used for each multiplexed channel. This low-order group address counter (25) operates with the high-order group clock as in the other circuits of this embodiment, and advances the count of bits in the low-order group frame when valid data for each channel arrives, and the decoder (26 ) Is the decoder at the bit position of the desired data (26)
Since the output enable pulse from the is enabled, the additional information termination / generation circuit can process the transmission path maintenance information inserted in each channel without converting it to the low-order group frame. .

In the above embodiment, the additional information termination / generation circuit (27
Although a), (27b), ..., (27n) are connected in cascade,
You may connect in parallel. In this case, the multiplexed relay output X
Is one of the additional information termination / generation circuits (28a), (28
b), ..., (28n) may be selected and output from the selected additional information termination / generation circuit.

〔The invention's effect〕

As described above, according to the present invention, there is an effect that the circuit scale can be reduced even when desired information is extracted from a higher-order group frame, and when multiplex relay of information is required. Further, there is an effect that the circuit scale can be reduced even when the head of the low-order group frame including the desired information can take a variable position with respect to the high-order group frame.

[Brief description of drawings]

FIG. 1 is a block diagram of a demultiplexing processing system showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional demultiplexing processing system, and FIG. 3 is a structure showing a conventional demultiplexing processing system. FIG. 4 is a diagram showing the structure of a frame. In the figure, (21) is a high-order group frame counter, (22)
Is a high-order group decoder that decodes the output of the high-order group frame counter (21), (23) is a pointer processing circuit, and (24)
a) and (24b) are selection switches, (25) is a low-order group address counter, (26) is a low-order group decoder, (27a), (27
b), ..., (27n) are additional information termination / generation circuits, (2n)
8) is a buffer circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

Front page continuation (72) Inventor, Satoshi Matsushita 5-1-1, Ofuna, Kamakura-shi, Kanagawa Sanryo Electric Co., Ltd., Communication Systems Laboratory (56) Reference JP-A-62-146041 (JP, A)

Claims (3)

(57) [Claims] 1. A high-order group frame counter for counting the data of a high-order group frame, and a count value of the high-order group frame counter are input to check the validity of the signal and the data indicating the beginning of the data of the low-order group frame in the high-order group frame. A high-order group decoder that outputs a signal indicating the above, a low-order group frame counter that inputs a signal indicating the beginning of the above data and a signal indicating the validity of the above data, and counts the data of the low-order group frame, and the above low-order group address A low-order group decoder that inputs a count value of a counter, detects a desired data position based on the count value, and outputs an output enable signal indicating the detected data position, the high-order group frame, and the low-order group decoder Output enable signal from the high-order group frame is input by the output enable signal. A time-division demultiplexing device, which is provided with a processing circuit for acquiring data. 2. The time division demultiplexing according to claim 1, wherein the low order group address counter, the low order group decoder and the processing circuit operate at the same clock speed as the high order group frame counter and the high order group decoder. apparatus. 3. The high-order group frame has a pointer indicating the beginning of data in the low-order group frame, and the high-order group decoder outputs a signal indicating the beginning of the data based on the value of the pointer. The time division demultiplexing device according to claim 1 or 2.