JPH02177634A - F/s bit synchronization establishing system - Google Patents

Abstract

PURPOSE:To reduce burden to synchronization establishment by reading in synchronism for the unit of information concerning an F/S bit, which is stored to each buffer means, and multiplexing the F/S bit to a second time division multiplexing signal. CONSTITUTION:Concerning respective F/S bits (14-1)-(14-N) temporarily stored to respective buffer means (16-1)-(16-N), an F/S bit multiplexing means 17 reads the F/S bits with making the partition of the information unit (multi-frame unit) mutually coincident. Then, the F/S bit is multiplexed to a second time division multiplexing signal 13. Thus, when a termination device, etc., to receive the second time division multiplexing signal executes the synchronization establishment of respective first time division multiplexing signals (12-1)-(12-N) and the synchronization is established only concerning anyone of F/S bit relating to the first time division multiplexing signal, the synchronization can be established concerning all the first time division multiplexing signals (12-1)-(12-N).

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a signal transmission method in which time division multiplexed signals transmitted via a plurality of digital lines are concentrated and transmitted as a new time division multiplexed signal. relates to a method for establishing synchronization of the F/S bits when multiplexing the F/S bits on each time division multiplexed signal into a new time division multiplexed signal. The aim is to realize an F/S bit synchronization establishment method that does not need to be performed for each multiplexed signal and can reduce the burden on establishing synchronization. an F/S bit extracting means provided for each of the first time division multiplexed signals for extracting an F/S bit that is inserted into each first time division multiplexed signal and constitutes one information unit with a predetermined plurality of bits; buffer means provided for each of the first time division multiplexed signals that temporarily stores the /S bit and can independently control writing and reading; and the information for the F/S bit stored in each buffer means. F/S bit multiplexing means for synchronizing the reading in units and multiplexing it into the second time division multiplexed signal.

[Industrial application field]

The present invention relates to a signal transmission method for concentrating and multiplexing time division multiplexed signals transmitted via a plurality of digital lines and transmitting them as new time division multiplexed signals. The present invention relates to a method for establishing synchronization of F/S bits when multiplexing the above F/S bits into a new time division multiplexed signal.

[Conventional technology]

In a digital switching system that transmits and exchanges PCM signals, multiple low-speed PCM multiplexed signals are usually concentrated and multiplexed into medium- and high-speed PCM multiplexed signals to perform switching connections and to connect to other stations or Transmit to a terminal device, etc.

FIG. 5 shows the overall configuration of a digital switching system that performs the above operations. Multiplexed signals 1-1 to 1-5, each of which has a transmission rate of 1.5 M (mega) bit/s, transmitted from other stations A-E using the PCM24 method are sent to a digital terminal (hereinafter referred to as DT) 2- 1 to 2-5, and is multiplexed into an 8 Mbit/s multiplexed signal 6 under the control of a digital terminal common (hereinafter referred to as DTC) 3, and sent to a digital switching module (hereinafter referred to as an exchange) which is an exchange.
(referred to as DSM) 4. Then, the 8 Mbit/s multiplexed signal 6 exchange-connected by the DSM 4 is received by the terminal device 5 as it is, for example.

FIG. 6 shows the format of the 1.5 Mbit/s multiplexed signals 1-1 to 1-5 in FIG. 5. These signals each follow the PCM24 system, and one channel stores one sample of audio data 8 in 8 bits from bit 1 to bit 8 as shown in the figure, and this is stored in channels 0 to 8 as shown in the figure. 23 and 24 channels are time-division multiplexed. Further, a 1-bit F/S bit 7 for frame synchronization and multi-frame synchronization (described later) is added to the beginning of the frame, and this is called a frame. Here, the time width of one frame is 125 μ (micro) seconds.

That is, the audio data 8 of each channel is 125μse
It is possible to transmit 8-bit audio data for 24 people in real time with a sampling frequency of 8 kHz.

As a result, the transmission rate per second is 1.5 Mbit
/s (strictly speaking, 1.544 Mbit/s).

Next, FIG. 7 shows the 8 output from DTC3 in FIG.
The format of the M bit/s multiplexed signal 6 is shown. Now, the 1.5 Mbit/s multiplexed signal 1-1 in FIG.
1-5 each has 24 audio channels per frame as shown in FIG. 6, so the total number of 5 channels is 120 channels. These audio channels are 8 Mbi
In the t/s multiplexed signal 6, as shown in FIG. 7, time slots (hereinafter referred to as TS) 4 to TS6 of one frame
The signal is time-division multiplexed into 120 channels of 3 and TS68 to TS127. Naturally, each channel corresponds to 8 in FIG.
It has a bit configuration.

Next, 1.5 Mbit/s multiplexed signals 1-1 to 1-
Each F/S bit 7 (see FIG. 6) of 5 channels is common to each channel and has 1 bit per frame, and 5 bits for 5 channels. Each of these 1.5 Mbit/s multiplexed signals 1-
Assuming that the F/S bits corresponding to 1 to 1-5 are 7-1 to 7-5, in the 8 M bit/s multiplexed signal 6, four control channels 21 of TSO to TS3 are used as shown in FIG.
Of these, it is stored in 5 bits, bits 2 to 6 of TS3. Note that control information such as failure information is stored in TSO to TS2 of the control channel 10 in the DTC3 of FIG.

Furthermore, in the 8 Mbit/s multiplexed signal 6, the seventh
The signaling channel 11 of TS64 to TS67 in the figure includes the 1.5 Mbit/s multiplexed signal 1-1 in FIG.
~1-5 are stored with signaling bits for call control (not particularly shown in FIG. 6).

The time width of one frame of the 8 Mbit/s multiplexed signal 6 in FIG. 7 is 125 μsec. That is, the audio data 8 of each channel is transmitted every 125 μsec, and the 8-bit audio data with a sampling frequency of 8 kHz is transmitted in real time for 120 people, or 1.5 Mbit.
It is possible to transmit five /s multiplexed signals l-1 to 1-5 (FIG. 5). A total of 128 channels can be transmitted including the voice channel 9, control channel 10, and signaling channel 11 in FIG. 7, and as a result, the transmission rate per second is 8 Mbit/s (strictly speaking, 8.
192 Mbit/s).

Here, in the F/S bit 7 (Fig. 6) added to the beginning of each frame of the 1.5 Mbit/s multiplexed signal, the F/S bit of the frame with an odd frame number is S bit 7 (F bit) is, for example, rlolol
It has a bit pattern for frame synchronization as shown in "o". Therefore, each DT2-1 to 2-5 in FIG.
．． By extracting the above patterns from the 5 Mbit/s multiplexed signals 1-1 to 1-5, the timing of frame separation is detected and frame synchronization is established. On the other hand, F/S bit 7 of frames with even frame numbers (
S bit) has a bit pattern for identifying each multiframe as shown in roolollJ for every predetermined plurality of frames (hereinafter referred to as multiframe), for example every 12 frames. Here, each 1.5 M signal stored in the signaling channel 11 shown in FIG.
Although not specifically shown, the signaling bits of the bit/s multiplexed signals 1-1 to 1-5 constitute one piece of call information or the like in each multiframe unit. Therefore, after the frame synchronization is established, each device in FIG. The call information, etc. is detected.

The terminal device 5 etc. in FIG. 5 also has a speed of 8 Mbit/s.
1.5 M bits each multiplexed into multiplexed signal 6
/s multiplexed signals 1-1 to 1-5 may be required, so it is necessary to establish multi-frame synchronization of each multiplexed signal. In this case, the seventh
Each 1.5 M bit/s multiplexed signal 1-1 is multiplexed into an 8 Mbit/s multiplexed signal 60TS3 in the figure.
When the F/S bits 7-1 to 7-5 of 1-5 are viewed in the frame direction, they are as shown in FIG. 9, for example. In the same figure,
The portions separated by single lines are frame separations, and the portions separated by double lines are multiframe separations.

[Problem to be solved by the invention]

In FIG. 9, the multiframe break positions for each F/S bit 7-1 to 7-5 are different. This is the 1.5 Mbit/s multiplexed signal 1-1 in FIG.
This is because 1-5 are processed by separate stations A-E and are not synchronized with each other.

Therefore, the termination device 5 in FIG.
In order to establish multi-frame synchronization of the /s multiplexed signals 1-1 to 1-5, multiplexing is performed on TS3 of the 8 Mbit/s multiplexed signal 6 in FIG. 7 as shown in FIGS. 7 and 9. It is necessary to individually perform multi-frame synchronization for each of the F/S bits 7-1 to 7-5, which are configured as F/S bits 7-1 to 7-5, which increases the circuit scale for establishing synchronization in the terminal device 5. This has the problem of increasing processing time and cost.

An object of the present invention is to realize an F/S bit synchronization establishment method that eliminates the need to establish synchronization of F/S bits in a terminal device, etc. for each multiplexed signal, and can reduce the burden of establishing synchronization. shall be.

[Means to solve the problem]

FIG. 1 is a block diagram of the present invention. The present invention is based on a signal transmission method in which a plurality of first time division multiplexed signals 12-1 to 12-N are concentrator-multiplexed and transmitted as a second time division multiplexed signal 13. Here, the first time division multiplexed signal 12 is a 1.5 Mbit/s multiplexed signal obtained by time division multiplexing of 24 audio channels according to the PCM system, for example, and the second time division multiplexed signal 13 is the first time division multiplexed signal 12 of 5 trees, for example, assuming N=5.
This is an 8 Mbit/s multiplexed signal that stores 120 audio channels by concentrating and multiplexing -1 to 12-5.

In FIG. 1, each of the first time division multiplexed signals 12-1 to 1
F/S bit extraction means 15-1 to 15-1 provided for each 2-N
15-N is each of the first time division multiplexed signals 12-1 to 15-N.
F/S bits 14-1 to 12-N are inserted into each predetermined time division unit, for example, one frame (24 channels), and constitute one information unit with a predetermined plurality of bits, for example, a plurality of frames (multiframe). -Extract N.

The means includes, for example, each of the first time division multiplexed signals 12-1 to 12-1.
means for extracting a clock from 12-N; means for detecting a synchronization pattern of each F/S bit 14-1 to 14-N to establish synchronization;
This is a means for extracting 1 to 14-N.

Next, each of the first time division multiplexed signals 12-1 to 12-
The buffer means 16-1 to 16-N provided for each
The F/S bits 14-1 to 14-N extracted by each F/S bit extraction means 15-1 to 15-N are temporarily stored. In this case, writing and reading can be controlled independently.

The means is, for example, an elastic store memory.

Furthermore, the F/S bit multiplexing means 17 synchronizes and reads out the F/S bits 14-1 to 14-N stored in each of the buffer means 16-1 to 16-N in the information unit, and The signal is multiplexed into two time division multiplexed signals 13. The means synchronizes the division of the multi-frames, reads each F/S bit 14-1 to 14-N from each buffer means 16-1 to 16-N, and outputs the second time division multiplexed signal 13. This means multiplexing the data into predetermined time slots.

In addition to the above means, F/S bit multiplexing means 17
When each F/S bit 14-1 to 14-N is multiplexed into the second time division multiplexed signal 13 by Delimiter information 19 is added.

For example, the means applies a logic signal to an empty bit of a time slot in which each of the F/S bits 14-1 to 14-N on the second time division multiplexed signal 13 is multiplexed, for each first frame of the multi-frame. This is a means of setting a bit of "1".

In addition, in FIG. 1, each first time division multiplexed signal 12
Alternatively, the audio channel portions -1 to 12-H are phase-synchronized with each other by buffer means (not particularly shown) and are multiplexed as the second time division multiplexed signal 13.

[For production]

In FIG. 1, each first time division multiplexed signal 12-1 to
Since F/S bits 14-1 to 14-N are often transmitted from different exchanges, F/S bits 14-1 to 14-N are synchronized with each other in predetermined multiple-bit information units (for example, multi-frame units). do not have.

These F/S bits 14-1-14-N are
The data are temporarily stored in buffer means 16-1 to 16-N via bit extraction means 15-1 to 15-N, respectively.

Then, the F/S bit multiplexing means 17 converts the information unit (multi-frame unit) into each F/S bit 14-1-14-H temporarily stored in each buffer means 16-1 to 16-N. The data is read out with the delimiters matching each other and multiplexed into the second time division multiplexed signal 13.

As a result, when a terminal device (not shown) that receives the second time division multiplexed signal 13 establishes synchronization of each of the first time division multiplexed signals 12-1 to 12-H, one of the
If synchronization is established for only the F/S bits for the two first time division multiplexed signals, synchronization can be established for all the first time division multiplexed signals 12-1 to 12-N.

Particularly, when multiplexing each of the F/S bits 14-1 to 14-N into the second time division multiplexed signal 13, the delimiter information adding means 18 adds delimiter information 1 for each delimiter of the information unit.
By adding 9, the terminal device etc. can establish synchronization for all the first time division multiplexed signals 12-1 to 12-N just by monitoring this delimiter information 19, and the F/S There is no need to perform a synchronization establishment operation for any of bits 14-1 to 14-N. This allows F/
In addition to the pattern for establishing synchronization, arbitrary information (inter-station control information, etc.) can be placed on the S bits 14-1 to 14-N.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

First, the overall configuration of the digital switching system is the same as that shown in FIG. 5, which has already been explained.

Next, FIG. 2 shows DT2-1 to 2-5 and DT2-5 in FIG.
FIG. 3 is a diagram showing the configuration of an embodiment of the present invention regarding a portion C3.

The 1.5 Mbit/s multiplexed signals 1-1 to 1-5 from other stations A to E in FIG. 5 are input to DTs 2-1 to 2-5, respectively. Since all DTs 2-1 to 2-5 have the same configuration, only DT 2-1 will be explained.

First, the clock extracting unit 20 has a speed of 1.5 Mbit/s.
A clock signal is extracted from multiplexed signal 1-1.

The synchronization establishment unit 21 establishes synchronization on a frame-by-frame and multi-frame basis for the 1.5 Mbit/s multiplexed signal 1-1.

The audio signal extraction unit 22 extracts only the audio channel portion from the 1.5 Mbit/S multiplexed signal 1-1 based on the clock signal extracted by the clock extraction unit 20.

The elastic store (hereinafter referred to as ES-A) 23 stores E based on the clock signal from the clock extractor 20.
1 and 5 M extracted from the audio signal extraction section 22 according to the write signal generated from the S-A write signal generation section 24
The audio channel portion of the bit/s multiplexed signal 1-1 is buffered. The stored contents are then read out according to the successive signal generated from the ES-A successive signal generation section 25 based on the successive timing signal from the successive timing signal generation section 30 in the DTCa, and
The multiplexing circuit 33 in DT'C3 is multiplexed with the output of -5.
Enter. Note that the write operation and read operation for the ES-A 23 can be performed independently.

The F/S bit extraction section 26 extracts the F/S bit 7-1 based on the clock signal from the clock extraction section 20 and the frame synchronization signal from the synchronization establishment section 21.

The elastic store (hereinafter referred to as ES-B) 27 stores E based on the clock signal from the clock extractor 20.
1 and 5 extracted from the F/S bit extractor 26 according to the write signal generated from the S-B write signal generator 28
F/S bit 7-1 of M bit/s multiplexed signal 1-1
buffer. And this memory content is DT
It is read out in accordance with the successive signal generated from the ES-B successive signal generation section 29 based on the successive timing signal from the successive timing signal generation section 30 in Ca,
It is multiplexed with the outputs of 2 to 2-5 and input to the F/S bit adding section 31 in the DTC'3. In addition, ES-82
Write and read operations for ES-A23
It can be done independently as in the case of .

Next, the configuration of the DTC 3 will be explained.

As described above, the successive timing signal generating section 30
A successive timing signal is supplied to the ES-A successive signal generating section 25 and the ES-B read signal generating section 29 in T2-1 to T2-5.

The F/S bit addition unit 31 adds each F/S bit output from each ES-827 in each DT2-1 to 2-5. -1~
7-5 to 8 through a multiplexing circuit 33 as described later.
It is multiplexed into an M bit/s multi-electrification signal 6. Further, when information indicating that a multi-frame delimiter is inputted from the F/S bit adding section 31, the leading bit adding section 32 inputs 8 M through the multiplexing circuit 33 as described later.
The leading bit 34 is multiplexed into the bit/s multiplexed signal 6.

The 8 Mbit/s multiplexed signal 6 obtained by multiplexing in the multiplexing circuit 33 as described above is 03 in FIG.
Output to M4.

The operation of the embodiment having the above configuration will be explained below.

First, each 1.5 Mbit/s multiplexed signal 1-1 to 1
The format of 5 is the same as that of FIG. 6 already explained, and the 8-bit audio data 8 of FIG. 6 is time-division multiplexed for 24 channels as shown in the same figure, and a 1-bit F/S Bit 7 is added to make one frame.

Next, in Fig. 3, the 8M bi output of DTC3 in Fig. 2 is shown.
The format of the t/s multiplexed signal 6 according to this embodiment is shown. This format is roughly the same as the conventional example shown in FIG. 7, and as shown in FIG. 3, one frame consists of 120
a voice channel 9 of channels, a control channel IO of 4 channels and a signaling channel 11 of 4 channels
It consists of 28 channels. However, the TS of control channel lO
The difference is that the first bit 34 is inserted into bit 7 of 3. This will be discussed later.

Now, the 24 audio channels of the 1.5 Mbit/s multiplexed signal 1-1 are extracted by the audio signal extraction unit 22, and then sent to other DTs 2-2 to 2-2 via the ES-A 23.
5 and are multiplexed together to form 120 audio channels 9 shown in FIG. In this case, each 1.5 Mbit/s multiplexed signal 1-1-1-5
are transmitted from separate stations A to E, so the clocks extracted from the clock extraction sections 20 in each of the DTs 2-1 to 2-5 are also not synchronized with each other. Therefore, each 1.
The audio channels of the 5 Mbit/S multi-electrification signals 1-1 to 1-5 are transmitted to each ES-A2 in the DTs 2-1 to 2-5.
After that, the successive timing signal generating section 30 in DTCa operates the ES-A read signal generating section 25 in each DT2-1 to DT2-5 in synchronization to perform the read operation of each ES-A23. By doing this, the phases of each audio channel are synchronized and multiplexed. This makes it possible to absorb the phase shift between each line. In addition, in the above read operation, the successive timing signal generation section 3 in DTCa
0 is operated based on a clock extracted from an 8 Mbit/s multiplexed signal (not shown) which is transmitted from 03M4 to DTC3 in FIG.
Synchronization with 03M4 in the figure is guaranteed.

Next, F/S bits 7-1 to 7- which are directly related to the present invention
The multiplexing method No. 5 will be explained.

First, in FIG. 2, the F/S bit extractor 26 in the DT 2-1 outputs 1.5 Mbit/s based on the clock signal from the clock extractor 20 and the frame synchronization signal from the synchronization establishment section 21. From multiplexed signal 1-1, the sixth
The F/S bit 7-1 at the beginning of each frame in the figure is extracted.

In this case, as explained in FIG. 8, the F/S bit 7-1 (F bit) of the frame with an odd frame number is
For example, the F/S bits 7-1 (S bits) of frames with even frame numbers, which have a bit pattern for frame synchronization as shown in "rlololo", are It has a bit pattern for multi-frame identification.

This F/S bit 7-1 is held in the ES-827, but in this case, the ES-B write signal generation section 28 generates a multiframe synchronization signal based on the multiframe synchronization signal from the synchronization establishment section 21. A write signal is generated so that consecutive F/S bits 7-1 from F/S bit 7-1 of the first frame are stored in order from a specific address of the ES-827.

The above F/S bit holding operation is performed for each DT2-1 to 2-5.
It is done every.

On the other hand, the successive timing signal generating section 30 in the DTC3 operates the ES-B successive signal generating section 29 in each DT2-1 to DT2-5 in synchronization, and starts from the specific address of each ES-827. Each F/S bit 7-1 to 7-5 is read out in synchronization with each other. That is, in each F/S bit 7-1 to 7-5 read from each ES-B 27,
The divisions of each multiframe are completely synchronized. In addition,
In this read operation, as in the case of the operation for the ES-A 23, the successive timing signal generation section 30 in the DTCa extracts from, for example, an 8 Mbit/s multiplexed signal (not shown) that is transmitted from the DSM 4 to the DTC 3 in FIG. If you operate based on the clock, the fifth
Synchronization with 03M4 in the figure is guaranteed.

Each F/S bit 7-1~ read out as above
7-5 is input to the F/S bit adding section 31 in DTCa. The adding unit 31 then sends each F/S bit 7-1 to 7-5 via the multiplexing circuit 33 to the 8 bits shown in FIG.
T in the control channel 10 of the M bit/s multiplexed signal 6
Multiplexed into bits 2 to 6 of S3.

If we look at the contents of <TS3 in the frame direction based on the above operation, we will see, for example, as shown in FIG. 4. In the figure, portions delimited by single lines are frame delimiters, and portions delimited by double lines are multiframe delimiters. As can be seen from the figure, the multiframe divisions are completely synchronized for each F/S bit 7-1 to 7-5.

Along with the above operation, the F/S bit addition unit 31 in DTCa in FIG.
Every time bits 7-1 to 7-5 are read, the leading bit adding unit 32 is notified of this, and as a result, the leading bit adding unit 3
2 is sent via the multiplexing circuit 33 to the 8 Mbit/s multiplexed signal 6 of FIG.
In this step, the first bit 34 is added to bit 7 of TS3 in the control channel 10. The situation is shown in Figure 4.

The 8 Mbit/s multiplexed signal 6 multiplexed as described above is transmitted to the terminal device 5 via 03M4 in FIG. In the terminal device 5, when establishing synchronization of each of the 1.5 Mbit/s multiplexed signals 1-1 to 1-5 multiplexed into the 8 Mbit/s multiplexed signal 6, the control channel 10 of FIG. By simply monitoring the first bit 34 added to bit 7 of TS3, each 1.5 Mb
Multi-frame synchronization can be established simultaneously between the it/s multiplexed signals 1-1 to 1-5.

Therefore, each 1.5 Mbit/s multiplexed signal 1-1~
The F/S bits 7-1 to 7-5 of 1-5 are used as signals for establishing synchronization in DT2-1 to 2-5 in FIG.
From DTC3 to 03M4 and terminal device 5, each F/S bit 7-1 to 7-5 multiplexed in 8 Mbit/s multiplexed signal 6 is no longer needed for synchronization establishment. become.

On the other hand, in each DT2-1 to DT2-5, F/S bits 7-1 to 7-5 do not require a synchronization establishment pattern for each multiframe, but synchronization is established every few multiframes. It is sufficient if the pattern for Therefore, in the F/S bits 7-1 to 7-5, for example, control information between exchanges, etc. can be placed in the position indicated by "*" of the S bit in FIG. Therefore, by multiplexing each F/S bit 7-1 to 7-5 into the bit/s multiplexed signal 6, the above control information is transmitted to 03M4 or the terminal device 5 in FIG. It is possible to have this function.

〔Effect of the invention〕

According to the present invention, when a terminal device or the like (not particularly shown) that receives the second time division multiplexed signal establishes synchronization of each first time division multiplexed signal, any one of the first time By establishing synchronization only for the F/S bits related to the division multiplexed signal, synchronization can be established for all the first time division multiplexed signals.

In particular, when multiplexing each of the above F/S bits into the second time division multiplexed signal, by adding delimiter information,
The terminal device or the like can establish synchronization for all the first time division multiplexed signals simply by monitoring this delimiter information, and there is no need to perform a synchronization establishment operation for any of the F/S bits.

As a result, it is possible to reduce the circuit scale for establishing synchronization in a terminal device, etc., and it is possible to improve processing speed and reduce costs.

Furthermore, since it is no longer necessary to carry a synchronization establishment pattern on the F/S bits, it becomes possible to carry arbitrary information (inter-station control information, etc.) on them.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the present invention. FIG. 2 is a configuration diagram of an embodiment of DT and DTC according to the present invention. FIG.
FIG. 4 shows a multiplexed signal format of 8 Mbit/s in an embodiment of the present invention.
Figure 5 is a diagram showing the contents of TS3 of the multiplexed signal, and Figure 6 is a diagram showing the configuration of the digital switching system.
Fig. 7 is a diagram showing the 8 M bit/s multiplexed signal format in the conventional example. Fig. 8 is an explanatory diagram of the F/S bit. Fig. 9 1 is a diagram showing the contents of TS3 of an 8 Mbit/s multiplexed signal in a conventional example. 12-1 to 12-N...First time division multiplexed signal, 13...Second time division multiplexed signal, 14-1 to 14-N...F/S bit, ■5- 1 to 15-N F/S bit extraction means, 16-1 to 16-N...buffer means, 17...F
/S bit multiplexing means, 1st... Delimiter information adding means, 19... Delimiter information.

Claims (1)

[Scope of Claims] 1) A signal transmission system in which a plurality of first time division multiplexed signals (12) are line-multiplexed and transmitted as a second time division multiplexed signal (13), comprising: Each of the first time division multiplexed signals for extracting the F/S bit (14) which is inserted into the time division multiplexed signal (12) in each predetermined time division unit and constitutes one information unit with a predetermined plurality of bits. (12) F/S bit extracting means (15) provided for each of the first time-division multiplexers that can temporarily store the extracted F/S bits (14) and independently control writing and reading. Buffer means (16) provided for each signal (12)
and synchronously reading out the F/S bits (14) stored in each of the buffer means (16) in the information unit;
F/ to be multiplexed on the second time division multiplexed signal (13)
An F/S bit synchronization establishment method characterized by comprising S bit multiplexing means (17). 2) The F/S bit multiplexing means (17) converts each F/S bit (14) into the second time division multiplexed signal (
13), each F is multiplexed for each information unit.
2. The F/S bit synchronization establishment method according to claim 1, further comprising delimiter information adding means (18) for adding delimiter information (19) common to the /S bit (14).