JPH0691523B2 - Frame synchronization method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal synchronization type frame synchronization system in a digital data transmission system for transmitting in frame units.

(Background of the Invention and Problems to be Solved by the Invention) In the internal synchronization type frame synchronization method, it is difficult to add a synchronization signal without damaging information.

Furthermore, in order to discriminate between the information signal and the synchronization pattern, a synchronization pattern having a certain length is required. Therefore, there is a problem in that the synchronization pattern generator on the transmission side, for example, the PN code generator, and the synchronization pattern detection circuit on the reception side are large-scaled.

Furthermore, there is a problem that a circuit size is further increased because a synchronization protection circuit is required to cope with the loss of the synchronization pattern and the generation of the pseudo pulse.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and provide a frame synchronization method capable of accurately performing frame synchronization with a short synchronization pattern without damaging the information carried by the information signal.

(Means for Solving the Problems) The frame synchronization system of the present invention is a frame synchronization system of a digital data transmission system for transmitting digital data of NRZ code in frame units.
The transmitting side is provided with a first converting means for converting the above bits into an RZ code which is contrary to the regulation of the RZ code to be frame synchronization data, and converting the data other than the one or more bits into the RZ code. Second conversion means for converting the transmitted n-row RZ code into an NRZ code by performing a reverse conversion to the conversion by the first conversion means, and detecting the existence time of the frame synchronization data in the n-row RZ code. A receiving side is provided with n detection means and a majority decision judging means for receiving a detection output from the n detection means and making a majority decision, and the conversion timing of the second conversion output is controlled according to the output of the majority decision means. It is characterized by.

(Operation) Since the present invention is configured as described above, the NRZ code input to the transmission side is converted into an RZ code in which the first bit of one frame is contrary to the regularity of the RZ code and the other bits are converted into an RZ code. It Since the RZ code that violates the regularity is the frame synchronization data, the frame synchronization data can be short. Further, since the receiving side performs the reverse conversion to the conversion on the transmitting side, the receiving side outputs the same bit stream as the NRZ code input to the transmitting side. Further, the existence time of the frame synchronization data in the RZ code of the n-th row sent from the transmitting side is detected by the detection means, respectively, and the detection output is majority-judged by the majority judgment means. The conversion timing on the receiving side is controlled in accordance with this majority decision output. Therefore, the conversion timing is stable and the synchronization is protected unless the loss of the synchronization data and the generation of the pseudo pulse due to the occurrence of the code error occur at the same time as the majority of n or more.

(Examples) Hereinafter, the present invention will be described with reference to Examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 1 (a) shows the transmitting side and FIG. 1 (b) shows the receiving side.

On the transmission side, the bit stream of NRZ code is input to the shift register 1. The bit stream input to the shift register 1 is as schematically shown in FIG.

The bit stream input to the shift register 1 is shifted according to the first clock signal output from the system control unit 4. Outputs NR0, NR1, and NR2 from three stages including a predetermined stage of the shift register 1 and an instruction signal ▲ ▼ appearing in a frame cycle from the system control unit 4 are supplied to the logic gate circuit 2, and the 3-bit signal of the NRZ code is supplied to the RZ code. Convert to a 6-bit signal in the format. The output from the shift register 1 is schematically shown in FIG. 3 (a).
The support signal ▲ ▼ is generated at the timing shown in FIG. 2 (b). FIG. 3 (b) is a reprint of FIG. 2 (b). This timing is the 3rd bit (NR
Z data standard), that is, NR0, NR1 and NR2 are a, b,
It occurs when it is c.

2 and 3, x, a, b, and c are logical "0".
Or it indicates “1”.

The logic gate circuit 2 has the following logical expression.

CR0 = NR0 + CR1 = CR2 = NR1 + NR0 / NR2 / CR3 = NR0 / CR4 = NR2 CR5 = NR0 / NR1 / NR2. Here in the above logical expression The data CR0 to CR5 indicate each bit of the converted data output from the logic gate circuit 2, and FIG.
As shown in (c).

The data output from the logic gate circuit 2 is supplied to the shift register 3 and converted into serial data according to the second clock signal output from the system control unit 4 and sent out. Here, the second clock signal is synchronized with the first clock signal and is set to a frequency twice the frequency of the first clock signal. The frequency is doubled because the logic gate circuit 2 converts the NRZ code bit stream to the RZ code bit stream.

The shift register 1, the logic gate circuit 2, and the shift register 3 configured as described above are provided, and n transmission sides controlled by the common system control unit 4 are provided.

NRZ code data NR0 to NR input to the logic gate circuit 2
2 is converted by the logic gate circuit 2 into the data in the middle column as shown in the left two columns in Table 1. In Table 1, lines [I] to [VIII] show the bit pattern of the first 3 bits of one frame when the instruction signal ▲ ▼ is in the logic "0" state, and the [IX] line shows the instruction signal ▲.
The black triangle indicates a logical "1" state, that is, a 3-bit bit pattern other than the designated portion in FIG. In Table 1, a, b and c indicate a logical "0" or a logical "1", and CR1, CR3 and CR in the [IX] line.
The reason why 5 becomes a logical "0" is that the NRZ code is converted to the RZ code. As is clear from Table 1, the serial data output from the shift register 3 has a logic "1" in the first 2 bits of each frame ([I] line to [VIII] line).
The last 1 bit of each frame is logical "0" (line [IX])
And as shown in FIG. 2 (c).

Therefore, the first 2 bits “11” of each frame are “10”
It violates the regularity of the RZ code represented by (1) or "00" (0). Therefore, "011" in combination with the last 1 bit "0" of the immediately preceding frame is used as a synchronization pattern to discriminate from the information signal. Further, in order not to damage the information in the sync pattern portion, the information is held by making it a portion (“11XXXX” in FIG. 1 (c)) in which not only the 2 bits at the beginning of the frame but 6 bits are converted. Here, "XXXX" of the 3rd to 6th bits at the beginning of Fig. 1 (c) is the 7th The logical expression is set so that the pattern of "011" does not appear considering the eye bit and the circuit is as simple as possible, and the synchronization pattern signal is added while holding the information signal. can do.

The serial bit stream from the shift register 3 formed as described above is transmitted to the receiving side.

Next, the receiving side will be described.

The serial bit stream transmitted from the transmission side is received by the shift register 5, converted into parallel data shifted by the second clock signal from the system control unit 10, and then supplied to the logic gate circuit 6 to be supplied to the logic gate circuit. 6
Is converted into parallel 3-bit data of NRZ code. The real bit stream input to the shift register 5 is as shown in FIG. 2 (c), and the data CR0 to CR5 output from the shift register 5 are as shown in FIG. 3 (d).

The logical expression of the logic gate circuit 6 is NR0 = CR0 ・ ▲ ▼ + CR0 ・ CR1 ・ CR3 NR1 = NR2 ・ ▲ ▼ + CR0 ・ CR1 ・ CR2 ・ CR3 (CR4 ・ CR5 ＋ ▲ ▼ ・ ▲ ▼) NR2 ＝ CR4.

Data NR0 to NR2 converted by the logic gate circuit 6 are shown in FIG.
It is as shown in (f). The data NR0 to NR2 output from the logic gate 6 are supplied to the shift register 7, converted into a serial bit stream by the first clock signal from the system control unit 10, and output.

On the other hand, the data CR0 to CR2 output from the shift register 5
Is supplied to the frame sync detection circuit 8 to output a frame sync detection signal.

There are n reception sides each consisting of the shift register 5, the logic gate circuit 6, the shift register 7, and the frame synchronization detection circuit 8, which are controlled by a common system control unit 10.
The frame synchronization detection signal from each frame synchronization detection circuit 8 is supplied to the majority decision determination circuit 9, and the majority decision determination output ▲
The system control unit 10 is controlled by ▼.

Then, the serial bit stream transmitted from the transmitting side is shifted by the shift register 5 and converted by the logic gate circuit 6 into 3-bit parallel data of NRZ code. Here, the logic gate circuit 6 is configured so as to satisfy the above-mentioned logical expression, and as is apparent from the above-mentioned logical expression, the 6 bits at the head of the frame are converted into the original information signal of the NRZ code. That is, as shown in the right two columns of Table 1, the input data of the RZ code shown in the middle column [I] line to [VIII] line is converted by the logic gate circuit 6, and the logic gate circuit 6 outputs the left column. NRZ for lines [I] to [VIII]
The code-converted data is output, and the shift register 7
Is converted into a serial bit stream by and output. In addition to the 6 bits at the beginning of the frame, the input data in the RZ format shown in the [IX] line in the middle column of Table 1 is converted to the NRZ code data shown in the [IX] line in the right column of Table 1. Is output. Therefore, as is clear from a comparison between the left column of Table 1 and the right column of Table 1, the NRZ code input to the transmission side is converted into the original bit stream as shown in Fig. 3 (g) and received. It will be output from the side.

On the other hand, the frame synchronization detection circuit 8 which receives the outputs CR0 to CR2 from the shift register 5 outputs the frame synchronization detection signal when the outputs CR0 to CR2 are "011". The generation timing of the frame synchronization detection signal is as shown in FIG.
The frame synchronization detection signal output from each frame synchronization detection circuit 8 is majority-judged, and as a result, it is supplied to the system control unit 10 as a frame synchronization signal ▲ ▼ of the system. System control unit 10 is frame synchronization
Controlled by ▼, the output from the logic gate circuit 6 in FIG. 3 (f) is always input to the shift register 7 at the timing when NR0 to NR2 become a to c. Therefore, a protection operation is performed against the loss of synchronous data and the occurrence of pseudo pulse due to a code error.

(Effects of the Invention) As described above, according to the present invention, conversion between NRZ code and RZ code and a frame synchronization signal can be added,
Since the above conversion and addition of the frame synchronization signal are performed by using the violation of the regularity of the RZ code, there is no loss of information. Further, a complicated timing circuit is not required for returning the added frame synchronization signal to the original information signal and for returning the RZ code to the NRZ code, and only a simple combinational logic circuit can be used. Moreover, if PLD is used, only one integrated circuit is required.

Further, since the sync pattern signal is added by utilizing the regularity violation of the RZ code, the number of bits of the sync pattern can be small and the sync pattern can be easily detected.

Further, there is also an effect that the timing of the reverse conversion by the receiving side is controlled according to the result of the majority decision of the n frame synchronization detection signals, so that the loss of the synchronization pattern and the generation of the pseudo pulse are protected.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 2 and 3 are schematic diagrams for explaining the frame structure and operation of one embodiment of the present invention. 1, 3, 5 and 7 ... Shift registers, 2 and 6 ...
... Logic gate circuits, 4 and 10 ... System control unit, 8
...... Frame synchronization detection circuit, 9 ... Majority decision circuit.

Claims (1)

[Claims] 1. In a frame synchronization method of a digital data transmission system for transmitting NRZ code digital data in units of frames, frame synchronization is performed by converting 1 or more bits at the head of one frame into an RZ code which is contrary to the regularity of the RZ code. The transmitting side is provided with a first converting means for converting data other than the one or more bits into an RZ code, and the n-row RZ code sent from the transmitting side is converted by the first converting means. Second conversion means for converting to an NRZ code and R of the n-th column
N for detecting the existence period of frame synchronization data in Z code
The receiving side is provided with a majority decision judging means for receiving the detection output from each of the detecting means and the n detecting means and making a majority decision, and the conversion timing of the second converting means is controlled in accordance with the output of the majority decision judging means. Characteristic frame synchronization method.