JP2586340B2 - Test signal insertion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test signal insertion circuit, and more particularly to a test signal insertion circuit for inserting a test signal into a digital signal in a digital circuit test of a communication device.

[0002]

2. Description of the Related Art Conventionally, in this type of test signal insertion circuit, a plurality of or plural directions of digital signals having the same frame format and bit rate but different bit phases due to different clock supply sources and the like. On the other hand, a test signal having the same frame format and bit rate is inserted into any one digital signal.

As shown in FIG. 2, the test signal insertion circuit includes test signal generation circuits 11 and 12 for generating test signals 211 and 212 from clocks (CLK) 205 and 206 and frame pulses 207 and 208, and an input signal. Data (DA
TA) 201, 202 and selection circuits 13, 14 for selecting one of the test signals 211, 212.

That is, the test signal generation circuit 11 generates a test signal 211 from the clock 205 and the frame pulse 207 respectively corresponding to the input data 201, and the test signal generation circuit 12 generates the test signal 211 corresponding to the input data 202.
06 and a frame pulse 208 to generate a test signal 212. Here, the test signal generation circuits 11 and 12 are circuits that generate a pseudo random pattern.

The selection circuit 13 inserts the test signal 211 from the test signal generation circuit 11 into the input data 201 and outputs it as output data 203. The selection circuit 14 outputs the input data 2
02, the test signal 212 from the test signal generation circuit 12 is inserted and output as output data 204.

A conventional test signal insertion circuit is, as described above,
A test signal generation circuit is provided corresponding to each of a plurality of digital signals having different bit phases or a plurality of directions.

[0007]

In the above-described conventional test signal insertion circuit, if the bit phases of a plurality of digital signals in a plurality of directions are different from each other due to different clock supply sources, etc. A test signal generation circuit is required.

When the test signal is inserted into an arbitrary digital signal, a clock synchronized with the digital signal into which the test signal is inserted is selected from a clock and a frame pulse synchronized with each digital signal. By selecting the frame pulse and inputting it to the test signal generation circuit, the number of test signal generation circuits can be reduced.

However, in general, a selected clock may have waveform degradation such as waveform dullness and whiskers, and the test signal generation circuit may malfunction due to the waveform degradation of the selected clock, causing an error in the test signal. Therefore, the means for selecting a clock cannot be used in the test signal insertion circuit.

Therefore, the number of test signal generation circuits increases as the number of digital signals into which test signals are inserted or the number of directions of the digital signals increases, so that the circuit scale of the test signal insertion circuit increases.

An object of the present invention is to provide a test signal insertion circuit which can solve the above problems and can reduce the circuit scale.

[0012]

A test signal insertion circuit according to the present invention converts a test signal preset to first and second digital signals having the same frame format and bit rate and different bit phases from each other. A test signal insertion circuit to be inserted, comprising: first phase changing means for changing the phase of a frame pulse corresponding to the second digital signal; and a frame pulse corresponding to the first digital signal and the first phase changing means. First selecting means for selecting one of the outputs of the phase transfer means, and test signal generating means for generating a test signal based on the output of the first selecting means and a clock corresponding to the first digital signal. Second selecting means for selecting one of the first digital signal and the output of the test signal generating means, and an output of the test signal generating means. And a third selecting means for selecting a second phase transfer means for phase transfer, one of the outputs of said second digital signal and said second phase transfer means.

[0013]

The test signal generation circuit for generating a test signal in synchronization with the first clock corresponding to the first input data is subjected to a phase transfer to a signal synchronized with the first clock by a bit buffer. , A test signal is generated, and this test signal is transmitted to the second bit buffer by another bit buffer.
After performing phase change to a signal synchronized with the second clock corresponding to the input data of the second input data, and then inserting the signal into the second input data.

Thus, the test signal can be inserted into the first and second input data with only one test signal generation circuit regardless of the number of digital signals or the number of directions in which the test signal is inserted. .

In this case, since the circuit size of the bit buffer is smaller than the circuit size of the test signal generation circuit, when the number of digital signals and the number of directions are increased, the number of bits is larger than that of the test signal generation circuit. Increasing the number of buffers can reduce the circuit scale, and the circuit scale can be reduced as compared with the related art.

[0016]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, a test signal insertion circuit according to one embodiment of the present invention includes bit buffers 1 and 5, selection circuits 2, 4, and 6, and a test signal generation circuit 3.

The bit buffer 1 stores input data (DAT
A) Clocks (CLK) corresponding to 101 and 102 respectively
Based on 105 and 106, the phase of the frame pulse (FP) 108 corresponding to the input data 102 is changed, and the frame pulse 111 is output to the selection circuit 2.

The selection circuit 2 selects one of the frame pulse 107 corresponding to the input data 101 and the frame pulse 111 from the bit buffer 1, and outputs the selected signal to the test signal generation circuit 3 as the selected frame pulse 112. .

The test signal generation circuit 3 generates a test signal 113 from the clock 105 and the selected frame pulse 112 from the selection circuit 2, and outputs the test signal 113 to the selection circuit 4 and the bit buffer 5, respectively.

The selection circuit 4 selects one of the input data 101 and the test signal 113 from the test signal generation circuit 3, and outputs the selected signal as output data (DATA) 103.

The bit buffer 5 has clocks 105 and 10
6, the test signal 113 from the test signal generation circuit 3 is phase-shifted, and the phase-shifted test signal 114 is output to the selection circuit 6.

The selection circuit 6 selects one of the input data 102 and the test signal 114 from the bit buffer 5,
The selected signal is output as output data 104.

The operation of one embodiment of the present invention will be described with reference to FIG. First, when inserting a test signal into the output data 103, the selection circuit 2 selects the frame pulse 107 corresponding to the input data 101, and outputs the selected frame pulse 107 as the selected frame pulse 112 to the test signal generation circuit 3. .

The test signal generation circuit 3 generates a test signal 113 from the clock 105 and the selected frame pulse 112, and outputs the test signal 113 synchronized with the clock 105 to the selection circuit 4.

Thus, by selecting the test signal 113 from the test signal generation circuit 3 by the selection circuit 4 as the input data 101, the output data 103 in which the test signal 113 is inserted into the input data 101 is output.

Next, when inserting a test signal into the output data 104, the selection circuit 2 selects the frame pulse 111 from the bit buffer 1 and uses the selected frame pulse 111 as the selected frame pulse 112 to generate a test signal generation circuit. Output to 3.

Here, the bit buffer 1 stores the input data 1
02, that is, a frame pulse 108 synchronized with the clock 106,
The phase is changed to a signal synchronized with 5. Therefore, the frame pulse 108 synchronized with the clock 105 is output from the bit buffer 1 to the selection circuit 2 as the frame pulse 111.

The test signal generation circuit 3 generates a test signal 113 from the clock 105 and the selected frame pulse 112, and outputs the test signal 113 synchronized with the clock 105 to the bit buffer 5.

The bit buffer 5 changes the phase of the test signal 113 from the test signal generation circuit 3 synchronized with the clock 105 to a signal synchronized with the clock 106. Therefore, the test signal 114 synchronized with the clock 106 is output from the bit buffer 5 to the selection circuit 6.

By selecting the test signal 114 synchronized with the clock 106 from the bit buffer 5 by the selection circuit 6, the output data 104 in which the test signal 114 is inserted into the input data 102 is output.

As described above, the test signal generating circuit 3 that generates the test signal 113 in synchronization with the clock 105 corresponding to the input data 101 is supplied to the clock 10 by the bit buffer 1.
A test signal 113 is generated by inputting the frame pulse 108 which has been phase-shifted to a signal synchronized with the signal 5, and the test signal 113 is phase-shifted to a signal synchronized with the clock 106 by the bit buffer 5 before being input. Data 10
2, the test data 113 and 114 can be inserted into the input data 10 by only one test signal generation circuit 3 regardless of the number of digital signals or the number of directions in which the digital signals are inserted.
The test signals 113 and 114 can be inserted into the first and the second test signal 102.

In this case, since the circuit scale of the bit buffers 1 and 5 is smaller than the circuit scale of the test signal generation circuit 3, the test signal generation circuit 3 may be used when the number of digital signals or the number of directions is increased. The circuit scale can be made smaller by increasing the bit buffers 1 and 5 than by increasing the number of bit buffers, and the circuit scale can be made smaller than in the conventional case.

That is, while the test signal generation circuit generally comprises 15 or 23 stages of flip-flops, etc., the bit buffer comprises 2 or 3 stages of flip-flops or the like. Increasing the number of bit buffers can reduce the circuit scale.

Since the number of flip-flop stages in the test signal generation circuit increases as the transmission speed increases, the above effect becomes more remarkable.

In the case where the number of test signal patterns is large or the test signal has a complicated pattern, the above-mentioned effect becomes remarkable because the circuit scale of the test signal generation circuit becomes considerably large.

[0037]

As described above, according to the present invention, a preset test signal is inserted into first and second digital signals having the same frame format and bit rate and different bit phases from each other. The test signal insertion circuit changes the phase of the frame pulse corresponding to the second digital signal, and selects one of the frame pulse subjected to the phase change and the frame pulse corresponding to the first digital signal to perform a test. The test signal generating means generates a test signal based on a clock corresponding to the first digital signal, and selects one of the first digital signal and the output of the test signal generating means. Output, and the output of the test signal generating means is phase-shifted, and the phase-shifted signal is compared with the second digital signal. By selecting one out,
There is an effect that the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1,5 bit buffer 2,4,6 selection circuit 3 test signal generation circuit 101,102 input data 103,104 output data 105,106 clock 107,108,111 frame pulse 112 selected frame pulse 113,114 test signal

Claims (3)

(57) [Claims] 1. A test signal insertion circuit for inserting a preset test signal into first and second digital signals having the same frame format and bit rate and different bit phases from each other, wherein A first phase changing means for changing the phase of a frame pulse corresponding to the digital signal, and a first means for selecting one of a frame pulse corresponding to the first digital signal and an output of the first phase changing means. Selection means, test signal generation means for generating a test signal based on the output of the first selection means and a clock corresponding to the first digital signal, and the first digital signal and the test signal generation means A second selecting means for selecting one of the outputs of the test signal generating means, a second phase changing means for performing a phase change of the output of the test signal generating means, 2 digital signal and the second digital signal.
And a third selecting means for selecting one of the outputs of the phase changing means. 2. The method according to claim 1, wherein the first phase changing means includes a second phase changing means.
The frame pulse corresponding to the digital signal of the second
The second phase change means is configured to perform a change from a signal synchronized with a clock corresponding to the digital signal to a signal synchronized with a clock corresponding to the first digital signal. 2. The apparatus according to claim 1, wherein an output is changed from a signal synchronized with a clock corresponding to the first digital signal to a signal synchronized with a clock corresponding to the second digital signal. Test signal insertion circuit. 3. The test signal insertion circuit according to claim 1, wherein said test signal generation means is configured to generate a pseudo random pattern.