JPH06350581A - Data phase conversion circuit - Google Patents

Abstract

PURPOSE:To realize the phase conversion of data without giving the phase replacement timing control signal from a data phase conversion circuit. CONSTITUTION:A serial parallel conversion circuit 15 of a data phase conversion circuit realizing data phase replacement through parallel expansion of input data ID applies serial parallel expansion to a write frame pulse WFP similarly to the case with the input data ID. A replacement pulse signal generating circuit 16 makes re-timing based on a read clock signal RCK to realize phase replacement of data by generating a phase conversion timing pulse (read frame pulse) nearly in the midposition. Thus, the scale of a phase conversion frame pulse generating circuit is reduced and the number of signals for frame pulse distribution is decreased and 1:5 serial/parallel expansion at all signal speeds is executed uniquely, then data phase conversion is implemented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data phase conversion circuit, and more particularly to a data phase conversion circuit which realizes phase conversion of input data without giving a control signal for timing of phase change.

[0002]

2. Description of the Related Art Conventionally, a data phase conversion circuit which realizes data phase crossing by expanding input data in parallel is a serial / parallel conversion (parallel expansion) of input data, and parallel / serial conversion of parallel data. By this, the phase change of the input data is realized. Serial-parallel conversion of input data is performed using a write clock signal having the same phase as the input data and a serial-parallel conversion timing pulse (write frame pulse) having the same phase as the input data. Parallel / serial conversion of parallel data is performed using a clock signal (reading clock signal) with a transfer phase and a transfer timing pulse (frame pulse for reading) to create a transfer timing for each signal during parallel expansion. Then, the parallel data is transferred at that timing.

FIG. 3 shows the configuration of a conventional data phase conversion circuit for realizing data phase replacement. The illustrated data phase conversion circuit includes a serial / parallel conversion circuit 11, a parallel / serial conversion circuit 12, and a write counter 13.
And a read counter 14. The data phase conversion circuit is supplied with the input data ID, the write clock signal WCK, the write frame pulse WFP, the read clock signal RCK, and the read frame pulse RFP, and the data phase conversion circuit outputs the output data OD. Is output.

A write clock signal WCK and a write frame pulse WFP are supplied to the write counter 13. The write clock signal WCK is the input data I
The clock signal has the same phase as D. Writing counter 1
Reference numeral 3 is a counter that performs a counting operation according to the write clock signal WCK and also has a write frame pulse WFP
It is a counter synchronized with. The write counter 13 outputs the write counter value to the serial / parallel conversion circuit 11. The illustrated write counter 13 is a quinary counter, and the write counter value is the write clock signal WC.
In synchronization with K, change from "0" to "4" by one,
It returns to "0" after "4".

The serial / parallel conversion circuit 11 is supplied with the input data ID and the write clock signal WCK, and the write counter 13 supplies the write counter value. Serial-parallel conversion circuit 1 shown
1 is the first to fifth latch circuits 11-1, ..., 11-
It consists of 5. First to fifth latch circuits 11-1
Each of 11-5 is composed of a selector (SEL) 11a and a D flip-flop 11b. The input data ID is supplied to the first input terminal A of the selector 11a, and the data output from the output terminal Q of the D flip-flop 11b is supplied to the second input terminal B. Selector 11a
Selects one of the input data ID and the output data from the D flip-flop 11b according to the write counter value from the write counter 13, and supplies the selected data to the input terminal D of the D flip-flop 11b. The write clock signal WCK is supplied to the clock terminal C of the D flip-flop 11b. The D flip-flop 11b latches the selected data in synchronization with the write clock signal WCK. In this example, the selector 11a of each of the first to fifth latch circuits 11-1 to 11-5 selects the input data ID when the write counter value is “0” to “4”, and selects the selected data. Is supplied to the corresponding D flip-flop 11b. The serial / parallel conversion circuit 11 includes the first to fifth latch circuits 11-1.
11-5 outputs the first and fifth latched data latched respectively as parallel data.

Similarly, the read counter 14 has a read clock signal RCK and a read frame pulse RF.
And P are supplied. The read counter 14 is a counter that performs a count operation according to the read clock signal RCK and is a counter that is synchronized with the read frame pulse RFP. The read counter 14 outputs the read counter value to the parallel / serial conversion circuit 12. Like the write counter 13, the illustrated read counter 14 is also a quinary counter.

The parallel / serial conversion circuit 12 is supplied with a read clock signal RCK, and the serial / parallel conversion circuit 11 and the read counter 14 are supplied with parallel data and a read counter value, respectively. The parallel / serial conversion circuit 12 shown in the figure
First to fifth latch circuits 12-1, ..., 12-5,
And a selector 12-6. The first to fifth latch circuits 12-1 to 12-5 include the first to fifth latch circuits 1 of the serial-parallel conversion circuit 11, respectively.
The first to fifth latch data output from 1-1 to 11-5 are supplied. First to fifth latch circuits 12-
Each of 1 to 12-5 is composed of a selector 12a and a D flip-flop 12b. First to fifth latch circuits 1
2-1 to 12-5 first input terminal A of selector 12a
Are respectively connected to the first to fifth latch circuits 11-1 to 11-1.
The first to fifth latch data from 11-5 are supplied to the second input terminal B of the D flip-flop 12b.
The data output from the output terminal Q is supplied. The selector 12a selects one of the supplied latched data and the output data from the D flip-flop 12b according to the read counter value from the read counter 14, and selects the selected data from the input terminal D of the D flip-flop 12b.
Supply to. The read clock signal RCK is supplied to the clock terminal C of the D flip-flop 12b. D
The flip-flop 12b receives the read clock signal RC
The selected data is latched in synchronization with K. In the present example, the selectors 11a of the first to fifth latch circuits 12-1 to 12-5 select the first to fifth latch data when the read counter value is "0" to "4", respectively. Then, the selected data is supplied to the corresponding D flip-flop 12b. First to fifth latch circuits 12-1
12-5 supplies the latched first and fifth latched data to the selector 12-6. Selector 12-
Reference numeral 6 denotes the first to fifth latch circuits 12-1 to 12- according to the read counter value from the read counter 14.
Select one of the first and fifth latch data from 5,
The selected data is output as output data OD. In this example, the selector 12-6 selects the fifth latch data and the first to fourth latch data when the read counter value is "0" to "4", respectively. In addition, this selector 12
It goes without saying that the selection operation of -6 is not limited to this.

Next, the operation of the conventional data phase conversion circuit will be described with reference to FIG. First, the operation when converting input data ID that is serial data into parallel data will be described, and then the operation when converting parallel data into output data OD will be described.

During serial / parallel conversion, the serial / parallel conversion circuit 11 converts the input data ID into parallel data by latching the input data ID with the write counter value output from the write counter 13. It becomes possible to perform serial / parallel conversion of the signal of each time slot indicated by the write frame pulse WFP in a steady state.

During parallel / serial conversion, the parallel / serial conversion circuit 12 uses the read counter value output by the read counter 14 to latch the parallel data output by the serial / parallel conversion circuit 11 according to the read clock signal RCK. And then transfer
By selecting the latch data by the read counter value output from the read counter 14, the parallel data is converted from parallel to serial and the output data OD is output.

As is apparent from FIG. 4, the rise of the clock at the pulse position of the read frame pulse RFP of the read clock signal RCK is the rise of the clock at the pulse position of the write frame pulse WFP of the write clock signal WCK. On the other hand, within the phase range shown by the dotted line in the figure, the data phase conversion can be performed even if it changes.

[0012]

In this conventional data phase conversion circuit, the degree of parallel expansion of input data is the amount of variation by the device from the reference clock signal to the write clock phase in each device configuration using this circuit. And the amount of device variation from the reference clock signal to the read clock phase.

Further, in a device such as a communication device having an enormous circuit scale, a package is divided for each processing unit and a plug-in unit configuration is adopted to continue and maintain the service. At that time, each main signal data is processed by the clock from the package that controls the clock supply (hereinafter, referred to as a clock supply package), and the maintenance unit corresponds to the package in this case. When evaluating the failure, make sure that the failure detection capability of the own package does not decrease when some failure (mainly input clock disconnection) occurs in the package that supplies the main signal to the own package (hereinafter referred to as the previous main signal package). design. Therefore, when receiving the main signal from the previous main signal package, the main signal is often transferred to the clock of the own package, and the failure evaluation is often performed at the clock of the own package.

When the data phase conversion is performed in a large number of places in the apparatus for the above-mentioned reason, a specific timing slot portion (data start position, here, frame pulse position corresponds to this) of each main signal data is re-timed by a clock. Therefore, it is necessary to manage the timing at the device. In addition, it is necessary to consider the degree of parallel expansion at each data phase conversion location based on the amount of variation due to the above device.

Such a design eliminates the versatility of the data phase conversion circuit and makes the device design complicated and requires a lot of design man-hours. Further, it is necessary to supply a large number of frame pulses having different phases from the clock supply package to each main signal package, which causes a pin neck of the package plug and the like.

An object of the present invention is to reduce the scale of a frame pulse generation circuit in a clock supply package by adopting a system in which a read frame pulse signal is not used for data phase conversion, and a signal for frame pulse distribution. To reduce the number.

[0017]

A data phase conversion circuit according to the present invention is a data phase conversion circuit which realizes a data phase change by parallelly expanding input data, and is synchronized with a frame pulse for writing supplied from the outside. Then, the count operation is performed by the write clock signal supplied from the outside in the same phase as the input data, and the write counter that outputs the write counter value and the input data are synchronized with the write clock signal based on the write counter value. , A serial-to-parallel converter for data that performs serial-to-parallel conversion to parallel data, and a read counter that performs a count operation with a read clock signal supplied from the outside in synchronization with a read frame pulse and outputs a read counter value. , Parallel data read A parallel / serial conversion circuit that performs parallel / serial conversion to output data in synchronization with the read clock signal based on the counter value, and a serial / parallel conversion for frame pulse that expands the write frame pulse in parallel in synchronization with the write clock signal. The circuit and the parallel-expanded frame pulse signal output from this frame pulse serial-parallel conversion circuit are phase-shifted to the read clock signal, and at the position approximately in the center of the pulse position of the parallel expanded frame pulse signal. And a crossover pulse signal generation circuit that creates a crossover pulse having a one-clock cycle width of the read clock signal, and supplies the crossover pulse to the read counter as a read frame pulse.

The data phase conversion circuit further includes a window pulse generation circuit that creates a window pulse by decoding the read counter value, and a read frame to the read counter when the replacement pulse deviates from the window pulse. It is preferable to have a switching timing fluctuation absorbing circuit that supplies a pulse.

[0019]

The writing frame pulse is serially / parallel expanded like the input data, retimed with the read clock signal, and a phase conversion timing pulse (reading frame pulse) is generated at a position approximately at the center thereof.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, a data phase conversion circuit according to an embodiment of the present invention includes a read frame pulse R.
3 is the same as that shown in FIG. 3 except that it has no FP and is provided with a serial / parallel conversion circuit 15, a transfer pulse signal generation circuit 16, a window pulse generation circuit 17, and a gate circuit 18. It has the configuration of. Therefore, components having the same functions as those of the components shown in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. Below, only the differences will be described in detail.

The serial / parallel conversion circuit 15 is supplied with the write frame pulse WFP and the write clock signal WCK, and is also supplied with the write counter value from the write counter 13. The serial / parallel conversion circuit 15 uses the write frame pulse WFP.
Serial-parallel conversion circuit 1 for input data ID
Similar to 1, this is a circuit that performs parallel expansion according to the write counter value from the write counter 13. As described above, since the write counter 13 is a counter synchronized with the write frame pulse WFP, the serial counter
The parallel conversion circuit 15 can be realized by one latch circuit. That is, the latch circuit that constitutes the serial-parallel conversion circuit 15 includes the selector 15a and the D flip-flop 16b. The write frame pulse WFP is supplied to the first input terminal A of the selector 15a, and the D flip-flop 15b is supplied to the second input terminal B.
The data output from the output terminal Q is supplied. The selector 15a selects one of the write frame pulse WFP and the output data from the D flip-flop 15b according to the write counter value from the write counter 13, and supplies the selected data to the input terminal D of the D flip-flop 15b. To do. The write clock signal WCK is supplied to the clock terminal C of the D flip-flop 15b. The D flip-flop 15b latches the selected data in synchronization with the write clock signal WCK. In this example, the selector 15a selects the write frame pulse WFP when the write counter value is "0", and supplies the selected signal to the D flip-flop 15b. Therefore, the serial-parallel conversion circuit 15 latches the write frame pulse WFP for a time corresponding to 5 clock cycles of the write clock signal WCK,
The latched signal is output as a frame pulse expanded in parallel.

The read-out clock signal RCK is supplied to the transfer pulse signal generation circuit 16 and the frame pulse expanded in parallel is supplied from the serial-parallel conversion circuit 15. The transfer pulse signal generation circuit 16 retimes the parallel-developed frame pulse output from the serial-parallel conversion circuit 15 by the read clock signal RCK, and reads the frame pulse at a substantially central position of the parallel-developed frame pulse. It is a circuit that creates a transfer timing pulse having a width corresponding to one clock cycle of the clock signal RCK.

Generally, the pulse signal generation circuit 1 for transfer
6 is a delay unit 16-1 in the preceding stage including n (n is an integer of 1 or more) stages of delay circuits, and m (m is an integer of 1 or more).
A delay unit 16-2 in the subsequent stage including a delay circuit in the stage,
A transfer circuit 16-3 that collectively transfers the output of the delay unit 16-1 at the preceding stage to the delay unit 16-2 at the subsequent stage and a output of the delay unit 16-2 at the subsequent stage are fed back to the delay unit 16-1 at the preceding stage. And a feedback circuit 16-4 for

The first to nth delay circuits 16-11 to 16-1n forming the delay unit 16-1 at the preceding stage are composed of an OR gate 16a and a D flip-flop 16b.

In the first delay circuit 16-11, the OR gate 16a takes the logical sum of the frame pulse expanded in parallel and the feedback signal from the feedback circuit 16-4, and the logical sum result of the D flip-flop 16b. It is supplied to the data input terminal D. D flip
The read clock signal RCK is supplied to the clock input terminal C of the flop 16b. The D flip-flop 16b holds the logical sum result from the OR gate 16a in synchronization with the read clock signal RCK, and supplies the held signal to the delay circuit 16-12 of the next stage (second).

Second to n-th delay circuits 16-12 to 16
In −1n, the OR gate 16a takes the logical sum of the output signal of the delay circuit from the previous stage and the feedback signal,
The result of the logical sum is supplied to the data input terminal D of the D flip-flop 16b. The D flip-flop 16b synchronizes with the read clock signal RCK and the OR gate 16
The logical sum result from a is held, and the held signal is supplied to the delay circuit at the next stage.

The transfer circuit 16-3 is composed of an OR gate, and takes the logical sum of the output signals of the first to nth delay circuits 16-11 to 16-1n forming the delay unit 16-1 of the preceding stage, and performs the logical sum. The result is supplied to the delay unit 16-2 in the subsequent stage.

The first to mth delay circuits 16-21 to 16-2m forming the delay unit 16-2 at the subsequent stage are composed of D flip-flops. First delay circuit 16-21
Holds the output signal of the transfer circuit 16-3 and supplies the held signal to the delay circuit 16-22 of the next stage (second). Second
The to m-th delay circuits 16-22 to 16-2m hold the output signals of the preceding delay circuits, respectively, and supply the held signals to the subsequent delay circuits.

The feedback circuit 16-4 is composed of a NAND gate, takes the NAND of the output signals of the first to m-th delay circuits 16-21 to 16-2m constituting the delay unit 16-2 in the subsequent stage, and feeds back the NAND result. And is supplied to the first to n-th delay circuits 16-11 to 16-1n forming the delay unit 16-1 at the preceding stage.

Here, the number n of stages of the delay unit 16-1 in the preceding stage and the number m of stages of the delay unit 16-2 in the subsequent stage depend on how much the read clock signal RCK is delayed.
In the case of the present example, since the parallel-developed frame pulse output from the serial-parallel conversion circuit 15 has a pulse width corresponding to 5 clock cycles of the write clock signal WCK, the frame for which the transposition timing pulse is expanded in parallel is used. The read clock signal RCK may be delayed by two clock cycles in order to bring it to a position approximately at the center of the pulse. Therefore, in this example, each of n and m is 1.

At this time, as shown in FIG. 2, since there is no relation between the change point of the parallel-developed frame pulse and the rising phase of the read clock signal RCK, the read clock is near the change point of the parallel-expanded frame pulse. When the signal RCK rises, the generated timing pulse for replacement is set to 1 as the read clock signal RCK.
It is possible that the phase always fluctuates with a clock cycle shift. In order to absorb this fluctuation, in the present embodiment, the window pulse generating circuit 17 and the gate circuit 1 which will be described later are provided.
8 and.

The window pulse generation circuit 17 is a circuit which decodes the read counter value output from the read counter 14 to generate a window pulse which is expanded by 1 bit before and after the pulse position at which the read counter 14 is loaded. Window pulse generation circuit 17
Has a decoder 17-1 and an SR flip-flop 17-2 composed of two NAND gates.

The gate circuit 18 is a gate circuit for absorbing the fluctuation of the transfer timing pulse output from the transfer pulse signal generation circuit 16. That is, the gate circuit 18 masks the transfer timing pulse output from the transfer pulse signal generation circuit 16 with the window pulse generated from the window pattern generation circuit 17, thereby changing the transfer pulse from the window pulse. Only when is removed, the read counter 14 is loaded. This eliminates the phase replacement error of the data due to the fluctuation of the replacement timing pulse that can be generated from the replacement pulse signal generation circuit 16.

When the data phase conversion circuit of the present embodiment is used, the degree of parallel expansion of the input data is determined by the window pulse width (3 clock widths) in consideration of the change of the transfer timing pulse and the latch of the serial / parallel conversion circuit. The timing margin (setup / hold timing margin) is further taken by one clock width before and after,
It is only necessary to perform 1: 5 serial / parallel expansion, and it is uniquely determined.

The present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the gist of the present invention.

[0037]

As described above, in the data phase conversion circuit of the present invention, the write frame pulse is serially / parallel expanded similarly to the input data, retimed by the read clock signal, and read at a substantially central position. The generation of the frame pulse for use has the effects of reducing the scale of the frame pulse generation circuit in the clock supply package and reducing the number of signals for frame pulse distribution in terms of the device configuration.

Further, conventionally, the degree of parallel expansion of input data depends on the amount of device variation from the reference clock to the write clock phase and the read clock phase from the reference clock in each device configuration using the conventional data phase conversion circuit. Although it was obtained from the sum of the fluctuation amounts due to the devices up to, the degree of parallel expansion can be uniquely determined by serial / parallel expansion of 1: 5 by using the configuration of the present invention. This has the effect of reducing the number of design steps.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data phase conversion circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing the details of the timing of a pulse signal generating circuit for transfer in the data phase conversion circuit shown in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional data phase conversion circuit.

FIG. 4 is a timing chart of each part in the data phase conversion circuit shown in FIG.

[Explanation of symbols]

 11 serial / parallel conversion circuit 12 parallel / serial conversion circuit 13 write counter 14 read counter 15 serial / parallel conversion circuit 16 transfer pulse signal generation circuit 17 window pulse generation circuit 18 transfer timing fluctuation absorption circuit

Claims (2)

[Claims] 1. A data phase conversion circuit that realizes data phase crossing by expanding input data in parallel, and is supplied from the outside in the same phase as the input data in synchronization with a frame pulse for writing supplied from the outside. And a write counter that performs a counting operation according to the write clock signal and outputs a write counter value, and the input data is serial-parallel converted into parallel data in synchronization with the write clock signal based on the write counter value. In synchronization with the data serial-parallel conversion circuit and the read frame pulse, the count operation is performed by the read clock signal supplied from the outside.
A read counter that outputs a read counter value; a parallel-serial conversion circuit that converts the parallel data into output data in parallel / serial conversion in synchronization with the read clock signal based on the read counter value; and the write frame. A serial / parallel conversion circuit for a frame pulse that expands a pulse in parallel in synchronization with the write clock signal, and a parallel expanded frame pulse signal output from the serial / parallel conversion circuit for a frame pulse is phased to the read clock signal. And a crossover pulse signal generation circuit for creating a crossover pulse having a one-clock cycle width of the read clock signal at a position approximately at the center of the pulse position of the frame pulse signal subjected to parallel expansion. And then the ride A data phase conversion circuit, wherein a replacement pulse is supplied to the read counter as the read frame pulse. 2. A data phase conversion circuit that realizes data phase crossing by expanding input data in parallel, and is supplied from the outside in the same phase as the input data in synchronization with a writing frame pulse supplied from the outside. And a write counter that performs a counting operation according to the write clock signal and outputs a write counter value, and the input data is serial-parallel converted into parallel data in synchronization with the write clock signal based on the write counter value. In synchronization with the data serial-parallel conversion circuit and the read frame pulse, the count operation is performed by the read clock signal supplied from the outside.
A read counter that outputs a read counter value; a parallel-serial conversion circuit that converts the parallel data into output data in parallel / serial conversion in synchronization with the read clock signal based on the read counter value; and the write frame. A serial / parallel conversion circuit for a frame pulse that expands a pulse in parallel in synchronization with the write clock signal, and a parallel expanded frame pulse signal output from the serial / parallel conversion circuit for a frame pulse is phased to the read clock signal. A crossover pulse signal generation circuit for crossovering and creating a crossover pulse having a one-clock cycle width of the read clock signal at a position approximately at the center of the pulse position of the frame pulse signal expanded in parallel; Readout power A window pulse generation circuit that creates a window pulse by decoding the counter value; and, when the replacement pulse deviates from the window pulse, supplies the readout frame pulse to the readout counter and absorbs the transition timing variation. And a data phase conversion circuit.