JPH0568025A - Clock replacement circuit - Google Patents

Abstract

PURPOSE:To realize the clock replacement circuit capable of outputting correct data when phase fluctuation of a 1st clock to be replaced is within a specific bit width with respect to a 2nd clock having an equal frequency. CONSTITUTION:The circuit is made up of a serial parallel converter 2 converting data inputted serially synchronously with a clock A into a 3-bit parallel signal with respect to an output pulse of a 3-bit ring counter 1, an enable FF4 using an output pulse of a 1.5 bit width pulse generating section 3 as an enable signal and using a clock B as a clock signal, a falling detection section 5 outputting a pulse of 1-bit width when a falling of an output pulse of the 1.5 bit width pulse generating section 3 at first with the clock B, an enable FF6 using an output pulse of the falling detection section 5 as an enable signal and using the clock B for the clock signal, a 3-bit ring counter 7 set by an output pulse of the falling detection section 5, and a parallel serial converter 8 converting a 3-bit parallel signal outputted from the enable FF6 into a serial signal by using an output of the 3-bit ring counter 7.

Description

Detailed Description of the Invention

[0001]

The present invention relates to data generated by using a first clock as data synchronized with a second clock whose frequency is equal to that of the first clock but whose phase variation is within 1 bit. It relates to a clock transfer circuit for doing.

FIG. 4 is a block diagram showing an application field of an example clock transfer circuit. The data communication LSi 40 operating with the clock B (master clock) causes internal delay when the operating speed becomes high, and the clock A extracted from the output has the same frequency as the clock B but a delayed phase, and also the output data. Since it is synchronized with the clock A, the phase is delayed.

Therefore, when the data is transferred to the data communication LSi 42 which operates at the next clock B, the data communication LSi 4
It is necessary to input output data synchronized with the clock A of 0 as data synchronized with the clock B. For this purpose, the clock transfer circuit 41 is used as shown in FIG.

In the clock transfer circuit 41, when the clock A is transferred to the clock B having the same frequency and a phase difference of 1 bit or less, it is possible to output correct data even if the phase difference becomes about 1 bit. Is desired.

[0005]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional clock transfer circuit, and FIG. 6 is a time chart of each part of FIG.
A, DATAIN, (A) to (G), CLKB, (H)
(M) and DATAOUT correspond to the same reference numerals in FIG.

In order to change the data synchronized with the clock A into the data synchronized with the clock B having a different phase, it is necessary to use data of 3 bits or more when changing to the clock B. Therefore, the clock transfer circuit converts the data of 3 bits. It is one unit.

In FIG. 5, a pulse having a 1-bit width for every 3 bits whose phase is shifted by 1-bit width as shown in FIGS. 6A, 6B, and 6C in synchronization with the clock A shown in CLKA of FIG. The output of the 3-bit ring counter 52 for outputting the enable signal is used as an enable signal, and a flip-flop with an enable (hereinafter referred to as F
(F)) 50.

In the FF 50 with enable, the DAT of FIG.
When the enable signal is at the H level, the input signal indicated by AIN is taken into the FFs 55 to 57, respectively. When the enable signal is at the L level, the FF is fetched.
The outputs of 55 to 57 are held, and the data shown in FIGS. 6D to 6F is output from the output of the FFs 55 to 57 by the selector 51.
To the AND circuits 58-60.

Meanwhile, the 3-bit ring counter 52 shown in FIG.
The pulse shown in (A) is J of the set signal output circuit 53,
Input as a set signal of K and FF62, and when the pulse shown in (A) is at H level, the clock A shown in CLKA in FIG.
6 is reset in synchronism with clock A when the pulse in synchronism with clock B, which is slightly out of phase with clock A shown in FIG.
The pulse shown in (G) and the signal shown in FIG. 6 (H) obtained by punching this pulse with the clock B using the FF 63 are obtained, and this signal is punched with the clock B using the FF 64.
A signal as shown in (I) is obtained.

Here, a signal obtained by ANDing the inverted output of the FF 64 and the output of the FF 63 by the AND circuit 65 is used as a set signal of the 3-bit ring counter 54, and is synchronized with the clock B from the 3-bit ring counter 54. 6
As shown in (J), (K), and (L), a pulse having a 1-bit width is output for every 3 bits whose phase is shifted by 1-bit width and is input to AND circuits 58, 59, 60 of the selector 51.

The outputs of the AND circuits 58 to 60 are OR circuits 6.
The output of the OR circuit 61 is as shown in FIG.
The signal becomes as shown in (M), is input to the FF 66, is punched out by the clock B, and outputs data synchronized with the clock B as shown in DATAOUT in FIG.

[0012]

However, as shown in FIG. 6C.
When the phase of the clock B is slightly deviated as shown in (a) of LKB, the FF 63 of the set signal output circuit 53 causes the FF 63 of FIG.
Since the signal shown in (2) is punched out twice in succession with the clock B, the output has a wide L level as shown in (B) of FIG. 6 and the set signal output from the AND circuit 65 is delayed by 1 bit width. The signal of the bit ring counter 54 shown in FIG. 6 (J) has an H level width of 2 bits.
As shown in C of (M), G data is output twice from the OR circuit 61.

Therefore, the DAT shown in FIG.
The G data is output twice as indicated by AOUT. That is,
If the phase of the clock B fluctuates, there is a problem that correct data cannot be output.

An object of the present invention is to provide a clock transfer circuit capable of outputting correct data if the phase fluctuation of the clock B to be transferred is within 1 bit width as compared with the clock A having the same frequency.

[0015]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, a first 3-bit ring counter 1 that outputs a pulse having a 1-bit width every 3 bits of the first clock, and data that is serially input in synchronization with the first clock are The output pulse of the first 3-bit ring counter 1 is used as the reference of the signal width, and the serial-parallel converter 2 is set as a parallel 3-bit parallel signal, and the output pulse of the first 3-bit ring counter 1 is used as the reference. And a 1.5-bit width pulse generator 3 that outputs a 1.5-bit width pulse
And a flip-flop using the output pulse of the 1.5-bit width pulse generator 3 as an enable signal and the 3-bit parallel signal output from the serial-parallel converter 2 as a clock when the output pulse is at the H level. To the first enable flip-flop 4 that holds the output of the flip-flop when it is at the L level and the falling edge of the output pulse of the 1.5-bit width pulse generator 3 by the second clock. The fall detection unit 5 that outputs a pulse having a 1-bit width when first detected, and the first enable flip-flop 4 when the output pulse of the fall detection unit 5 is an H level 2 bit parallel signal is taken into a flip-flop that uses the second clock as a clock, and a second enable that holds the output of the flip-flop when it is at the L level. And a second flip-flop 6 with a loop and a second pulse for outputting a pulse having a 1-bit width for every 3 bits which is set by the output pulse of the fall detection unit 5 and has a phase shift of 1-bit width. 3 bit ring counter 7 and a parallel-serial converter 8 for converting the 3 bit parallel signal output from the second enable flip-flop 6 into a serial signal using the output from the second 3 bit ring counter 7. It will be configured.

[0016]

According to the present invention, the 1.5-bit width pulse of the first clock output from the 1.5-bit width pulse generator 3 is used as the enable signal of the enable FF 4, and when the enable signal is at the H level. Since the signal input to the enable FF 4 is punched out by the second clock, the input signal can be always punched out even if there is a phase change of the second clock.

Further, when the trailing edge detector 5 first detects the trailing edge of the 1.5-bit width pulse output from the 1.5-bit width pulse generator 3 at the second clock, the following output is made. The 3-bit ring counter 7 is set with a pulse having a 1-bit width until the rising edge of the second clock.

This set signal is output if the phase fluctuation of the second clock is within 1 bit, and the set signal is output from the 3-bit ring counter 7 in synchronization with the second clock and shifted in phase by 1 bit for each 3 bits. A 1-bit width pulse is output to the parallel-serial converter 8 and this output pulse enables F with enable.
Since the 3-bit parallel signal output from F6 is converted into a serial signal, normal data is output even if the phase of the second clock fluctuates within 1 bit width.

[0019]

FIG. 2 is a block diagram of a clock transfer circuit according to an embodiment of the present invention, and FIG. 3 is a time chart of each part of FIG.
LKA, DATAIN, (A) to (E), CLKB,
(F) to (P) and DATAOUT correspond to the same reference numerals in FIG.

In FIG. 2, the 3-bit ring counter 1 is provided for each 3 bits of the clock A shown in CLKA of FIG.
As shown in (A), a pulse having a 1-bit width is output and input as an enable signal of the enable FF 9 of the serial-parallel converter 2.

The signal shown in DATAIN in FIG. 3 is input to the serial-parallel converter 2, and becomes a 3-bit parallel signal via the FFs 10, 11, and 12 and is input to the enable FF 9,
When the enable signal shown in (A) is at the H level, the input signal is taken into the FFs 13 to 15 and punched out by the clock A, and when it is at the L level, the outputs of the FFs 13 to 15 are held, and FIG.
(C) A 3-bit parallel signal as shown in (D) is input to the enable FF4.

The 1-bit width input signal to the FF 22 of the 3-bit ring counter 1 is a 1.5-bit width pulse generator 3
A pulse having a 1.5-bit width synchronized with the head of the 3-bit parallel signal as shown in FIG. 3C is output from the output of the OR circuit 23 and is input to the enable FF 4 as an enable signal.

In the enable FF 4, when the enable signal is at the H level, the signals shown in FIGS. 3 (B), (C) and (D) are taken into the FFs 16 to 18, punched out at the clock B shown in FIG. Since the outputs of the FFs 16 to 18 are held at this time, the outputs of the FFs 16 to 18 are shown in FIG.
As shown in (G) and (H).

In this case, since the enable signal has a width of 1.5 bits as shown in FIG. 3 (E), the input signal is always passed through even if the phase of the clock B changes. The falling edge detection unit 5 receives the signal having the 1.5-bit width shown in FIG. 3 (E), and the clock B at which the falling edge having the 1.5-bit width is first detected is shown in FIG. 3 (I). Next clock B
A pulse having a width up to the rising edge of is output from the NOR circuit 24 and input to the FF 6 with enable as an enable signal and to the 3-bit ring counter 7 as a set signal.

In the FF6 with enable, when the enable signal shown in FIG. 3 (I) is at H level, FIG. 3 (F) (G)
The input signal shown in FIG.
It is punched out by the clock B shown in CLKB, and when it is at the L level, the outputs of the FFs 19 to 21 are held.
A signal as shown in (L) is obtained and input to the AND circuits 28, 29, 30 of the parallel-serial converter 8.

In the 3-bit ring counter 7, as shown in FIG.
The signal shown in (I) is used as a set signal in FIGS.
As shown in (O), a pulse having a 1-bit width is output for every 3 bits whose phase is shifted by 1 bit and is input to the AND circuits 28 to 30 of the parallel-serial converter 8.

Therefore, the OR circuit 31 of the parallel-serial converter 8 outputs a signal as shown in FIG. 3 (P), which is input to the FF 32 and is punched out by the clock B to output a signal as shown in DATAOUT in FIG.

Here, as shown in D and E of CLKB in FIG.
The pulse shown in FIGS. 3 (I) and 3 (O), which rises and falls when the phase shifts within 1 bit width, is generated even though the width is narrowed. Therefore, the output of the enable FF 6 is shown in FIG.
As shown in (J), (K), and (L), signals A, B, and C,
In addition, the output (M) (N) of the 3-bit ring counter 7
Since the signals shown in (O) are also generated in order, the output of the OR circuit 31 of the parallel-serial converter 8 is A, as shown in FIG.
B, C, ..., so the output of FF32 is shown in FIG.
Normal data is output as indicated by TAOUT.

[0029]

As described in detail above, according to the present invention, a clock transfer circuit capable of outputting correct data can be obtained if the phase fluctuation of the clock B to be transferred is within 1 bit width as compared with the clock A having the same frequency. is there.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention,

FIG. 2 is a block diagram of a clock transfer circuit according to an embodiment of the present invention,

FIG. 3 is a time chart of each part of FIG.

FIG. 4 is a block diagram showing an application field of an example clock transfer circuit;

FIG. 5 is a block diagram of a conventional clock transfer circuit,

FIG. 6 is a time chart of each part of FIG.

[Explanation of symbols]

1, 7, 52, and 54 are 3-bit ring counters, 2 is a serial-parallel converter, 3 is a 1.5-bit width pulse generation unit, 4, 6, 9 and 50 are enable flip-flops, and 5 is a fall detection unit. , 8 is a parallel-serial converter, 10-22, 32, 55-57, 62-64, 66 are flip-flops, 23, 31, 61 are OR circuits, 24, 25 are NOR circuits, 26-30, 58-60 , 65 is an AND circuit, 51 is a selector, and 53 is a set signal output circuit.

Claims (1)

[Claims] 1. A first 3-bit ring counter (1) for outputting a pulse having a 1-bit width for every 3 bits of a first clock, and data inputted in series in synchronization with the first clock. The output pulse of the first 3-bit ring counter (1) and the serial-parallel converter (2) that uses the output pulse of the first 3-bit ring counter (1) as a reference of the signal width to generate a 3-bit parallel signal. A 1.5-bit width pulse generator (3) that outputs a pulse of 1.5-bit width as a reference, and an output pulse of the 1.5-bit width pulse generator (3) as an enable signal At the time of, the 3-bit parallel signal output from the serial-to-parallel converter (2) is taken into a flip-flop that uses the second clock as a clock, and when at the L level, the first enable flip-flop with the output of the flip-flop is held. (4) and a trailing edge detector (1) that outputs a pulse of 1-bit width when the trailing edge of the output pulse of the 1.5-bit-width pulse generator (3) is first detected at the second clock ( 5) and using the output pulse of the fall detection section (5) as an enable signal, the 3-bit parallel signal of the first enable flip-flop (4) is used as the second clock when the output pulse is at the H level. Take it to the flip-flop used as a clock and
The second which holds the output of the flip-flop at the time of the level
Of the enable flip-flop (6) and the output pulse of the fall detection section (5), and a pulse of 1-bit width is synchronized with the second clock for every 3 bits whose phase is shifted by 1-bit width. And a second 3-bit ring counter (7) for outputting the 3-bit parallel signal of the output of the second flip-flop with enable (6) using the output of the second 3-bit ring counter (7). A clock transfer circuit comprising a parallel-serial converter (8) for converting a serial signal.