JPH04292017A - Serial/parallel conversion circuit - Google Patents

Abstract

PURPOSE:To equalize the phase of input data and the phase of output data with each other. CONSTITUTION:At a shifting part 1, serial data is converted into parallel data by every N-bits in accordance with an input clock synchronous with said serial data, and at a clock generating part 10, N-kinds of the clocks which are N- frequency-divided input clock are generated. At a data array detecting part 30, phase difference including output parallel data is detected at the time when the above-mentioned parallel data is latched by the clock of an optional phase on the basis of a case that the input serial data and the output parallel data are of the same phase. At an S/P converting timing selecting part 20, the clock having the phase difference equal to the phase difference detected at the time of the clock of the optional phase is selected as the clock for latching, and at a latching part 2, the parallel data of the shifting part 1 is latched by this clock for latching, and the output parallel data is generated.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a serial-to-parallel conversion circuit that converts serial data to parallel data, and in particular, it is capable of always keeping a data pattern in serial data and a data pattern in parallel data after conversion in the same phase. This relates to a serial-to-parallel conversion circuit that can perform

[0002] In communication devices, when monitoring and processing high-speed data consisting of input serial data, there is a method in which serial-to-parallel conversion is performed to convert it into low-speed data (parallel data) and then predetermined processing is performed. Generally used.

[0003] In this case, if the phase relationship between the parallel data that has been slowed down by conversion and the original serial data is not the same (for example, the first bit of the serial data becomes the first bit of the parallel data), then the Data monitoring and various processing become difficult.

Therefore, there is a need for a serial-to-parallel conversion circuit that can always make the phase of parallel data after conversion the same as the phase of serial data before conversion.

[0005]

2. Description of the Related Art FIG. 6 shows a conventional serial-to-parallel conversion circuit, illustrating an example of converting each byte of serial data consisting of 8 bits into parallel data, in which reference numeral 11 denotes an 8-bit shift register; 12 is a flip-flop, and 13 is a 1/8 frequency divider circuit.

Input serial data is applied to data input D of 8-bit shift register 11 and clock input C
K is shifted by applying a clock CLK synchronized with the input data to produce an 8-bit parallel data output, which is applied to the data input D of the flip-flop 12. On the other hand, input clock CLK
is divided by 1/8 by the 1/8 frequency divider circuit 13 and applied to the clock input CK of the flip-flop 12, so that the 8 bits from the 8-bit shift register 11 are
Bit parallel data is latched to generate 8-bit low-speed parallel data.

[0007]

In this case, the 1/8 frequency divided clock output from the 1/8 frequency divider circuit 13 may have eight types of phases with respect to the input serial data. Therefore, the probability that data of a predetermined repeated data width (1 byte 8 bits) in the input serial data is output from the flip-flop 12 as 8 parallel data having the same phase as this serial data is 1/8. , it is not guaranteed that they will always be in phase.

On the other hand, in the state of parallel data, alarm (ALM) monitoring that takes into account the frame length (data width),
When performing various other types of processing, there is a problem in that if the phase of the parallel data does not match the phase of the input serial data, it is difficult to perform the correct processing.

The present invention aims to solve the problems of the prior art, and provides a serial-to-parallel conversion circuit that can convert input serial data into output parallel data that is always in the same phase as the serial-to-parallel conversion circuit. The purpose is to provide a serial-parallel conversion circuit.

0010

[Means for Solving the Problems] The present invention provides an input clock C synchronized with input serial data.
A shift unit 1 converts N bits into parallel data in accordance with LK, a latch unit 2 that latches the parallel data with a latch clock and generates output parallel data, and N types of input clocks divided by N. The phase difference between the clock generator 10 that generates a clock and the output parallel data when latched with a clock of an arbitrary phase in the clock generator 10 is defined as the reference phase when the input serial data and the output parallel data are in the same phase. A data array detecting section 30 that detects and generates an output, and an S/S/S/2 clock that selects as a latch clock a clock having a phase difference corresponding to the phase difference detected from a clock of an arbitrary phase in the output clock of the clock generating section 10. The present invention is characterized in that it includes a P conversion timing selection section 20.

[0011]

[Operation] FIG. 1 shows the basic structure of the present invention. In the shift section 1, the input serial data is shifted to N according to the input clock CLK synchronized with the input serial data.
Convert bit by bit to parallel data. On the other hand, the clock generator 10 generates N types of clocks by dividing the input clock by N. Also, output parallel data when the data array detection unit 30 latches the above parallel data with a clock of an arbitrary phase in the clock generation unit 10, with the case where the input serial data and output parallel data are in the same phase as the reference phase. It detects the phase difference between the two and generates an output. Furthermore, the S/P conversion timing selection section 2
0, a clock having a phase difference corresponding to the phase difference detected from the above arbitrary phase clock in the output clock of the clock generating section 10 is selected as a latch clock and is provided to the latch section 2. Then, the latch section 2 latches the parallel data of the shift section 1 using this latch clock to generate output parallel data.

Therefore, according to the present invention, it is possible to realize a serial-to-parallel conversion circuit that can convert input serial data into output parallel data that is always in phase with the input serial data.

[0013]

Embodiment FIG. 2 shows an embodiment of the present invention, in which the bit width to be converted is 8 bits. The same parts as in FIG. 6 are indicated by the same numbers, and 10 is a clock generation section that divides the input clock to generate a plurality of clocks, and 14 is an 8-bit shift register. 20 represents an S/P conversion timing selection unit that determines the timing of conversion from serial data to parallel data; 212 to 218 are AND gates;
23 is an OR gate, and 24 is a selector. Further, 30 is a data array detection section, 15 is a flip-flop,
312 to 318 are case detection units for cases ■ to case ■, respectively.

As in the conventional case shown in FIG.
LK to produce an 8-bit parallel data output, which is applied to the data input D of the flip-flop 12 and latched in response to a latching clock applied to the clock input CK. Produces an output consisting of data.

On the other hand, the clock CLK is divided by 1/8 frequency dividing circuit 1
The output clock obtained by dividing the frequency by 8 by adding 3 to 3 is added to the 8-bit shift register 14, and the original clock CLK is added to the clock input CK and shifted, thereby generating 8 types of clocks with different timings. do.

FIG. 3 shows the timing of S/P conversion, in which data A1-1 to A1-8 of a certain byte (A1) of serial data and data generated from the 1/8 frequency dividing circuit 13 are shown. , clocks with eight types of timings ■ to ■ are shown.

In FIG. 2, when there is no output from the OR gate 23, the selector 24 is switched to the "0" side, and the clock at a certain timing among the clocks output from the 8-bit shift register 14 is sent to the flip-flop. 15 clock inputs CK. As a result, flip-flop 15 becomes flip-flop 12.
The output of the flip-flop 12 is latched, and eight types of data arrays are generated as a relationship between the 8-bit parallel data that is the output and the parallel data that is the output of the flip-flop 12.

FIGS. 4 and 5 show data arrays (1) and (2), and FIG. 4 shows cases ■ to ■.
Figure 5 shows the data array (1) for cases ■~■
The data array (2) for the case is shown. Case ■ indicates the case where the latching occurs at the timing ■ shown in Figure 3, Case ■ indicates the case where the latching occurs at the timing ■ shown in Figure 3, Case ■ indicates the case where the latching occurs at the timing ■ shown in Figure 3. The case ■ shows the case where the latch is performed at the timing ■ shown in FIG. 3, the case ■ shows the case where the latch is performed at the timing ■ shown in FIG. A case (2) shows a case where the signal is latched at the timing (2) shown in FIG.

In FIG. 2, case detection units 312 to 3
Reference numeral 18 detects data arrays corresponding to cases 1 to 2 in FIG. 4 and cases 2 to 2 in FIG. 5, respectively. That is, since the input serial data includes information indicating a frame break in a specific bit, the case detection units 312 to 318 detect this information and output the output of the flip-flop 12 and the flip-flop 15. By detecting the phase difference between the output of the flip-flop 12 and the output of the flip-flop 15, it is possible to detect which of cases ■ to case ■ corresponds to the data array of the output of the flip-flop 12 and the output of the flip-flop 15. In the case of a data array, the case detection section can generate an "H" output indicating the detection result.

Now, when the detection unit 315 generates an "H" output for case (2), this corresponds to the case where serial-to-parallel conversion is performed at timing (2) as described above, and the serial data and parallel data are in the same phase. Compared to case (2), the clock timing is delayed by 4 bits. The output of the detection unit 315 is the AND gate 2
15 and turns it on, the clock from the 8-bit shift register 14 with a timing 4 advanced by 4 bits is applied to the selector 24 via the OR gate 22. At the same time, an input is given to the selector 24 via the OR gate 23 due to the output generation of the detection unit 315, so that the selector 24 is switched to the "1" side, and the clock indicated by timing 2 passes through the selector 24 to the clock of the flip-flop 15. given to input CK.

As a result, the phase of the clock applied to the flip-flop 12 advances by 4 bits, resulting in the same state as when serial-to-parallel conversion is performed in case (2) shown in FIG. 4, and the phase of the input serial data and output parallel data is will match. The selector 24 continues to be “1”.
”, this state will be maintained from now on.

Note that when the first selected clock is timing ■, the output of the flip-flop 12 is for case ■, and each case detection section 312 to 31
Since no output is generated from 8, the selector 24 is set to “1”.
This state will continue to be maintained without being switched to the other side.

[0023]

As explained above, according to the present invention, in a serial-to-parallel conversion circuit that converts serial data to parallel data, the data pattern in input serial data and the data pattern in output parallel data after conversion can always be changed. It is possible to have the same phase,
Subsequent data monitoring and various processing performed using this parallel data will not become difficult.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing the timing of S/P conversion.

FIG. 4 is a diagram showing data array (1), in which case ■
~Case ■ shows data arrays with different timings.

FIG. 5 is a diagram showing data array (2), in which case ■
~Case ■ shows data arrays with different timings.

FIG. 6 is a diagram showing a conventional serial-parallel conversion circuit.

[Explanation of symbols]

1 Shift part 2 Latch part 10 Clock generation section 20 S/P conversion timing selection section 30 Data array detection section

Claims (1)

[Claims] 1. A shift unit (1) that converts input serial data into parallel data every N bits according to an input clock (CLK) synchronized with the input serial data, and latches the parallel data with a latch clock. a latch unit (2) that generates output parallel data, a clock generator (10) that generates N types of clocks obtained by dividing the input clock by the N, and a clock generator (10) that generates N types of clocks by dividing the input clock by the N, and a clock generator (10) that generates output parallel data with the same phase as the input serial data and the output parallel data. a data array detection section (30) that detects a phase difference of the output parallel data when latched with a clock of an arbitrary phase in the clock generation section (10) and generates an output, using the case as a reference phase;
and an S/P conversion timing selection unit ( 20)
A serial-to-parallel conversion circuit characterized by comprising: