JP2811671B2 - Synchronous signal detection device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization signal detection device, and more particularly to a synchronization signal detection device that detects a synchronization signal from a serial signal sequence input at high speed.

[Conventional technology]

Conventionally, when detecting a data pattern of a synchronizing signal from a serial signal sequence input at a high speed (for example, 64 MbPS), it is necessary to input the above-described serial signal sequence to a shift register and perform high-speed data pattern matching detection. Was common.

[Problems to be solved by the invention]

In the prior art as described above, a high-speed logic circuit (ECL) must be used, and if the data pattern of the synchronization signal is long or the algorithm for matching detection is complicated, the above-described technique is used. There have been various problems in configuring a logic circuit (ECL). That is, whether the logic circuit (ECL) is assembled discretely, or is formed into a gate array or an IC, not only the device becomes large, but also the degree of integration becomes insufficient and the power consumption becomes excessive. Therefore, improvement of these problems has been desired.

Therefore, an object of the present invention is to detect a short data pattern in a serial signal stream input at a high speed in advance, thereby detecting a data pattern of a sync signal in the serial signal stream at a lower speed. A detection device is provided.

[Means for solving the problem]

The present invention relates to a synchronization signal detecting device for detecting a synchronization signal of a specific data pattern in input serial data, a serial-parallel conversion means for converting input serial data into parallel data and outputting the parallel data, Phase detection means for detecting a phase relationship between the parallel data and the synchronization signal from data of a plurality of upper bits of the parallel data and fewer bits than the synchronization signal when a data pattern of the synchronization signal is included; Means for shifting the phase of the parallel data based on the phase, and means for detecting the synchronization signal based on the shifted data, wherein the phase for converting the serial data to parallel data matches the synchronization signal. When the phase to be converted from the current state is shifted one bit at a time in the lower direction, Tsu City of data patterns different from each other, a synchronization signal detection apparatus characterized by selecting the data pattern of the synchronization signal.

[Action]

Serial data input at high speed is converted into parallel data. From the data converted in parallel, a data pattern considered to be a synchronization signal and a phase in the case of a synchronization signal are detected.

Based on the above detection result, parallel data is shifted in order to correct the data pattern to be a normal synchronization signal. The shifted data pattern is compared with the synchronization signal, and if they match, a data pattern [synchronization signal] and data are output in which the above-described phase difference has been eliminated.

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

 FIG. 1 shows a block diagram of a synchronization signal detecting device.

A flip-flop 1 is connected to a terminal 9 to which serial digital data is added, and further, flip-flops 1 to 8 are cascaded.
The outputs of the flip-flops 1 to 8 are supplied to the flip-flop 15 in an 8-bit parallel state.

As shown in FIG. 2, one block of the serial data added at a high speed, for example, 64 MbPS from the terminal 9 is composed of a synchronization signal SYNC (16 bits) + ID signal (16 bits) + data signal (186 × 8 bits). This is supplied continuously. The synchronization signal is a fixed data pattern, and an address is extracted from the ID signal.

Now, assuming that data of the N-th block (an address extracted from the ID signal is, for example, N) is supplied, this data is synchronized with the clock signal CK1 supplied from the terminal 10 to generate a flip-flop. From the flip-flop 1 to the flip-flop 8. By simultaneously taking out the respective outputs of the flip-flops 1 to 8, the data is converted from serial to 8-bit parallel and supplied to the 8-bit flip-flop 15. The flip-flop 15 supplies 8-bit parallel data to the memory 11.

The above-described clock signal CK1 is also supplied to the frequency dividing circuit 12,
The frequency is divided by the frequency dividing circuit 12 to 1/8. The frequency-divided clock signal CK2 is supplied to the flip-flops 15 to 19, the memory 11, and the flip-flop 25 described later.
To the flip-flop 28.

In synchronization with the frequency-divided clock signal CK2, 8-bit parallel data is taken into the flip-flop 15.
Flip-flops 16, 17, 1 for flip-flop 15
8 and 19 are cascaded, and data is sequentially shifted from the flip-flop 15 to the flip-flop 19 in synchronization with the frequency-divided clock signal CK2. Outputs of the flip-flops 16 to 19 are supplied to the barrel shifter 13.
Supplied in 32-bit parallel and flip-flop 19
(Hereinafter referred to as 4-bit data) is supplied to the phase detector 14.

The phase detector 14 determines whether or not the data being input with only the input 4-bit data corresponds to the fixed data pattern of the synchronization signal without detecting all 16 bits corresponding to the synchronization signal. It is to detect.
If the above 4-bit data corresponds to a part of the fixed data pattern of the synchronization signal, the position of the 4-bit data in the fixed data pattern is determined, and the first bit of the fixed data pattern shown in FIG. The number of bits from to the first bit of the 4-bit data is calculated as the correction amount CN.
Then, a correction signal SC corresponding to the correction amount CN is output to the barrel shifters 13, 20 and the latch 21.

As shown in FIG. 3A, when the fixed data pattern of the synchronization signal is, for example, 16 bits of “0000110010101111”, the fixed data pattern of the synchronization signal serial-parallel-converted by an appropriate phase is shown in FIG. There are only eight types (P1 to P8) as shown in FIGS. The eight types of phases P1 to P1 shown in FIGS.
It can be seen that the leading 4-bit data of the fixed data pattern of P8 is an independent data pattern. Therefore, by looking at the 4-bit data, it is possible to detect what phase the synchronization signal is included in. The phase detector 14 detects the supplied 4-bit data as a part of the fixed data pattern. When the phase is detected as, for example, a phase P4 shown in FIG. 3E, a correction amount CN (3 bits in the case of the phase P4) is calculated, and the correction signal SC corresponding to the correction amount CN is output to the barrel shifters 13, 20.
And output to the latch 21. The above correction amount CN is shown in FIG.
Is the number of bits from the first bit to the first bit of the 4-bit data in the fixed data pattern of the synchronization signal shown in FIG. 4A, and the correction amount is 3 bits at the phase P4 in FIG.

The details of the phases P1 to P8 of the fixed data pattern in FIG. 3A are shown in FIGS. B to I, and FIGS. 4A to H.
Shows the relationship between the 32-bit data pattern corresponding to each of the phases P1 to P8 and the correction amount CN. FIGS. 3B to I correspond to FIGS. 4A to 4H, respectively.

As described above, the memory 11 stores the 8-bit parallel data from the flip-flop 15, specifically, one block of data (synchronous signal 16 bits + ID signal 16 bits + data signal 186 × 8 bits) shown in FIG. It is something to memorize.

As described above, the data of the N-th block is output in 8-bit parallel from the flip-flop 15, and at the same time,
Data one block delayed from the memory 11, that is, (N-1)
The data of the third block (the address is (N-1)) is supplied to the flip-flop 25 in synchronization with the clock signal CK2. Each of the cascade-connected flip-flops 25 to 28 has eight flip-flops arranged in parallel, similarly to the flip-flops 16 to 19 described above. The data of the (N-1) th block is sequentially shifted from the flip-flop 25 to the flip-flop 28 in synchronization with the clock signal CK2 formed by frequency division, and the output of each flip-flop is a barrel shifter. Supplied in 32-bit parallel to 20.
The flip-flop 28 supplies 8-bit parallel data to the barrel shifter 22.

The barrel shifters 13 and 20 hold the lower-order 7-bit data of the previously input data together with the input 32-bit data. Then, a 32-bit data pattern is determined based on the correction amount CN defined by the above-described correction signal SC. And in barrel shifters 13 and 20, the fourth
As shown in FIG. D, the shift of the phase P4 shown in FIG. 3E is eliminated by shifting the range of the data pattern by 3 bits of the correction amount CN defined by the aforementioned correction signal SC. , A new data pattern that is considered to include a synchronization signal and an ID signal. Of the 32-bit data pattern, the upper 16 bits are a fixed data pattern considered as a synchronization signal, and the lower 16 bits are data considered as an ID signal.

The new upper 16-bit data pattern set by the barrel shifters 13 and 20 is supplied to the synchronization signal detection circuit 23, and the new lower 16-bit data is transmitted to the ID signal detection circuit 24.
Supplied to

In the synchronization signal detection circuit 23, the signal is supplied from the barrel shifter 13. The fixed data pattern of the N-th block and the fixed data pattern of the (N-1) -th block supplied from the barrel shifter 20 are respectively set to the fixed data pattern "00".
00110010101111 ", and when they match, an H level signal is output. When they do not match, an L level signal is AND gated.
Output to 29.

The ID signal detection circuit 24 extracts the address N based on the lower 16-bit data supplied from the barrel shifter 13, and extracts the address (N-1) based on the 16-bit data supplied from the barrel shifter 20. , The subtraction between the addresses [that is, N- (N-1) = 1] is performed. An H level signal is output to the AND gate 29 when the subtraction value matches 1, and an L level signal when the subtraction value does not match.

The AND gate 29 outputs an H-level signal to the latch 21 and outputs it to the terminal 31 as a synchronization signal output only when an H-level signal is supplied from both the synchronization signal detection circuit 23 and the ID signal detection circuit 24. .

The latch 21 is always supplied with the correction signal SC from the phase detector 14, and when an H-level signal is applied from the AND gate 29, the correction signal SC corresponding to the three bits of the correction amount CN
Is added to the barrel shifter 22.

The barrel shifter 22 holds the previously input lower 7 bits together with the 8 bits of data input from the flip-flop 28, and stores the 7 bits of data before the next input 8 bits of data. I have arranged. Then, the data range is shifted by 3 bits based on the 3 bits of the correction amount CN defined by the above-described correction signal SC, and the lower 3 bits of the 7-bit data and the upper 5 bits of the 8-bit data are used. New data is created and the clock signal CK
Synchronized with 2 and taken out from terminal 30 in 8-bit parallel.
In this way, the data of the (N-1) th block is corrected to the correct phase and output. Then, in the same manner as in the above-described process, the data of the (N-1) th block, the Nth data, and the (N + 1) th data are continuously output.

As shown in this embodiment, it is checked in advance whether or not the pattern corresponds to the fixed data pattern of the synchronization signal using only the 4-bit data pattern, and if the phase is detected, the synchronization signal, I
Detection of D signals and the like can be performed at a low processing speed, and the circuit configuration can be simplified.

〔The invention's effect〕

According to the present invention, since the synchronization signal can be detected at a lower speed, a small-sized, highly integrated, and low-power circuit (gate array, memory for 1SYNC delay, etc.) can be used, and thereby a complicated and flexible circuit can be used. It is possible to detect the synchronization signal, and there is an effect that the cost can be reduced. In particular, if the processing speed is reduced to the processing speed of the CMOS, it becomes possible to use a CMOS gate array.
And there is an effect that cost can be reduced. Also, if you pay attention to the choice of the data pattern of the sync signal,
There is also an effect that the configuration of the phase detecting means becomes simpler.

According to the embodiment, it is checked in advance whether or not the fixed data pattern of the synchronization signal corresponds with only the 4-bit data pattern, and if the phase is detected, the synchronization signal and the ID signal of the ID signal are thereafter determined based on this. There is an effect that detection can be performed at low speed and the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a schematic diagram showing a serial data structure, FIG. 3 is a schematic diagram used for describing the embodiment, and FIG. FIG. 9 is a schematic diagram illustrating a state where a range of a data pattern changes according to an amount. Explanation of main symbols used in the drawings 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, 17, 18, 19, 25, 26, 27, 28: flip-flop, 14: phase detector , 23: Sync signal detection circuit, 2
4: ID signal detection circuit, 29: AND gate.

Claims (1)

(57) [Claims] 1. A synchronizing signal detecting device for detecting a synchronizing signal of a specific data pattern in input serial data, a serial / parallel converting means for converting the input serial data into parallel data and outputting the parallel data; When the data pattern of the synchronization signal is included in the parallel data, a phase relationship between the parallel data and the synchronization signal is detected from data of a plurality of upper bits of the parallel data and less bits than the synchronization signal. Phase detection means, means for shifting the phase of the parallel data based on the detected phase, and means for detecting a synchronization signal based on the shifted data, wherein the serial data is converted into parallel data. The phase to be converted from a state where the phase to be converted to When shifted by one bit to the direction, as the data pattern of the plurality of bits are different from each other in the upper, the synchronization signal detecting apparatus characterized by selecting the data pattern of the synchronization signal.