JPH0746143A - Operation control system for parallel-serial conversion circuit and for serial-parallel conversion circuit - Google Patents

Abstract

PURPOSE:To provide the operation control system for parallel-serial conversion circuit and serial-parallel conversion circuit which suppresses the extension of the circuit scale even in the case of the increase of the number of parallel- serial conversion circuits and serial-parallel conversion circuit, whose operations are controlled with the same phase, and where the timing design and the high- speed operation are easy. CONSTITUTION:A reset signal S41 outputted from a first n:1 parallel-serial conversion circuit 1 is connected to a second n:1 parallel-serial conversion circuit 1, and a reset signal S42 outputted from the second n:1 parallel-serial conversion circuit 1 is connected to a third n:1 parallel-serial conversion circuit 1, and hereafter, a reset signal S4m-1 outputted from an (m-1)th n:1 parallel-serial conversion circuit 1 is connected to an m-th n:1 parallel-serial conversion circuit 1 in the same manner. Since each n:1 parallel-serial conversion circuit 1 resets the lower-order n:1 parallel-serial conversion circuit 1, serial signals from all of n:1 parallel-serial conversion circuits 1 are outputted with the same phase.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel / serial conversion circuit and a serial / parallel conversion circuit, and more particularly to an operation control system for combining a plurality of parallel / serial conversion circuits operating at high speed or a plurality of serial / parallel conversion circuits.

[0002]

2. Description of the Related Art FIG. 17 shows a conventional parallel-serial conversion circuit disclosed in a document (Miyakawa et al .: "Examination of ultra-high-speed multiplexing circuit module", 1991 IEICE Fall Conference, B-660). It is a block diagram which shows an operation control system. In the figure, reference numeral 1 is a first one for converting n-bit parallel data S21 into serial data S31 based on a clock pulse S1.
N: 1 parallel-serial column conversion means and n-bit parallel data S22 to serial data S3 based on the clock pulse S1.
2nd n: 1 parallel-serial conversion means for converting into 2
Is reset signal generating means for generating a reset signal S40 based on the clock pulse S1. The reset signal S40 generated by the reset signal generation means 2 is supplied to the first n: 1 parallel-serial conversion means 1 and the second n: 1 parallel-serial conversion means 1 as reset signals S41 and S42.
Is a distribution means for distributing as.

FIG. 18 is a block diagram showing the first n: 1 parallel / serial conversion means 1 and the second n: 1 parallel / serial conversion means 1. In the figure, 101 counts n bits by the clock pulse S1 and reset signal S4m (m
= 1, 2), a frequency dividing counter circuit whose operation phase is controlled, 102 is a latch circuit which holds n-bit parallel data S2m in an n-bit cycle, and 103 is a frequency divider for an n-bit signal held in the latch circuit. It is a selector circuit which sequentially selects according to the address value of the counter circuit and outputs the serial data S3m.

Next, the operation will be described with reference to the timing chart shown in FIG. Here, n = 4 is set for simplicity of description.

First, as an initial state, it is assumed that the address value of the frequency division counter circuit 101 in the first n: 1 parallel-serial conversion means 1 operates from "3" with respect to the change point of the parallel data S21. . The frequency division counter circuit 101 starts counting based on the clock pulse S1, and when the frequency division counter address value becomes “2”, the latch circuit 102 holds the parallel data S21 and sends it to the selector circuit 103. The selector circuit 103 has the address value “3” of the frequency division counter.
Data "a1" for "4" and data "a" for "4"
The data "a3" for "2" and the data "a4" for "2" are sequentially output as serial data S31.

Similarly, as an initial state, it is assumed that the address value of the frequency division counter circuit 101 in the second n: 1 parallel / serial conversion means 1 operates from "2" with respect to the change point of the parallel data S22. Then, the data "b" of the serial data S32
The position of "1" is shifted by 3 bits from the position of the data "a1" of the serial data S31 and is output.

Therefore, the reset signal S40 generated by the reset signal generating means 2 is first divided into the reset signal S41 and the reset signal S42 by the distributing means 3, respectively.
And the second n: 1 parallel-to-serial conversion means 1 so that the address values of the respective frequency dividing counters 101 are controlled to be equal. As a result, the data "a9" of the serial data S31 and the data "b9" of the serial data S32 are output in the same phase.

FIG. 20 is a block diagram showing the operation control system of the conventional serial-parallel conversion circuit shown in the above document.
In the figure, 4 indicates the serial data S31 and the clock pulse S
1st 1: n serial-parallel conversion means for converting into n-bit parallel data S21 based on 1 and serial data S32 based on clock pulse S1 n-bit parallel data S2.
2nd 1: n serial-parallel conversion means for converting into 2
Is a reset signal generating means, and 3 is a distributing means, which is the same as the conventional example.

FIG. 21 is a block diagram showing the first 1: n series / parallel conversion means 4 and the second 1: n series / parallel conversion means 4. In the figure, 101 is a frequency division counter circuit, 1
Reference numeral 02 denotes a latch circuit, which has the same configuration as that of the conventional example, and 104 denotes a shift register circuit which sequentially shifts the serial data S3m based on the clock pulse S1 and outputs n-bit data.

Next, the operation will be described with reference to the timing chart shown in FIG. Here, n = 4 as in the conventional example.

First, as an initial state, the address value of the frequency division counter circuit 101 in the first 1: n serial-parallel conversion means 4 is "3" with respect to the data "a1" of the serial data S31.
Suppose it is working from. The shift register circuit 104 sequentially shifts the serial data S31 based on the clock pulse S1, and the frequency division counter circuit 101 starts counting based on the clock pulse S1. When the frequency division counter address value becomes "4", The latch circuit 102 holds the data from the shift register circuit 104 all at once and outputs it as parallel data S21.

Similarly, as an initial state, the address value of the frequency division counter circuit 101 in the second 1: n serial / parallel conversion means 4 operates from "2" with respect to "b1" of the serial data S32. Then, the parallel data S22 is output in a phase different from the parallel expansion phase of the parallel data S21.

Therefore, the reset signal S40 generated by the reset signal generating means 2 is first divided into the reset signal S41 and the reset signal S42 by the distributing means 3, respectively.
And the second 1: n serial-to-parallel conversion means 4, and control is performed so that the address values of the respective frequency division counters 101 become equal. As a result, the parallel expansion phase of the parallel data S21 and the parallel expansion phase of the parallel data S22 become the same phase.

[0014]

Since the conventional parallel-serial conversion circuit and the operation control system of the serial-parallel conversion circuit are configured as described above, the parallel-serial conversion circuit and the serial-parallel conversion for controlling the operation in the same phase. When the number of circuits increases, the circuit scale of the distribution means increases, and it becomes difficult to reduce the delay difference between a plurality of distributed reset signals, which makes timing design difficult, which in turn makes high-speed operation difficult. was there.

The present invention has been made in order to solve the above problems, and it is possible to suppress an increase in circuit scale even if the number of parallel-serial conversion circuits and series-parallel conversion circuits that control the operation in the same phase increases. Another object of the present invention is to obtain a parallel-serial conversion circuit and an operation control method of the serial-parallel conversion circuit that facilitates timing design and high-speed operation.

[0016]

The operation control system of the parallel-serial conversion circuit according to the present invention has a plurality of n:
A reset signal is output from the frequency division counter in the 1-parallel serial conversion circuit, and the frequency division counter in the lower n: 1 parallel-serial conversion circuit is reset. That is, a first parallel-serial conversion circuit and at least a second parallel-serial conversion circuit are provided, and a reset signal is output from the parallel-serial conversion circuit,
It is characterized in that a plurality of parallel / serial conversion circuits are operated in the same phase by resetting the lower parallel / serial conversion circuits.

Further, if the phase difference between the phase of the parallel data and the operating phase of the parallel / serial converting circuit is detected in the first parallel / serial converting circuit and it is within a predetermined prohibited phase range, the operating phase of the previous period is changed. It is characterized in that a plurality of parallel / serial conversion circuits can be stably operated in the same phase by providing a phase comparison circuit for performing the above.

Further, according to the control operation method of the serial-parallel conversion circuit of the present invention, a reset signal is output from the frequency dividing counters of the 1: n serial-parallel conversion circuit arranged in parallel.
Each resets the frequency division counter in the lower 1: n serial-parallel conversion circuit. That is, a plurality of series-parallel conversion circuits are provided by including a first series-parallel conversion circuit and at least a second series-parallel conversion circuit, outputting a reset signal from the series-parallel conversion circuit, and resetting the lower serial-parallel conversion circuit. It is characterized in that the conversion circuits are operated in the same phase.

Further, a phase control circuit for controlling the parallel data to be output in a predetermined parallel expansion order is provided in the first serial-parallel conversion circuit, and the phase control is applied only to the first serial-parallel conversion circuit. Then, a plurality of serial-parallel conversion circuits are operated so that parallel data are output in the same phase and in a predetermined parallel expansion order.

[0020]

In the present invention, a plurality of n: 1 parallel / serial conversion circuits each output a reset signal, and the lower n:
1 parallel to serial conversion circuit is reset, so all n: 1
The serial signals from the parallel-serial conversion circuit are output with the same phase.

Further, since the plurality of 1: n serial / parallel conversion circuits each output a reset signal and reset the lower 1: n serial / parallel conversion circuits, the parallel data from all the serial / parallel conversion circuits have the same phase. Is output with.

[0022]

EXAMPLES Example 1. Embodiments of the present invention will be described below with reference to the drawings. 1 is a configuration diagram showing a first embodiment of an operation control system of a parallel-serial conversion circuit according to the present invention. In the figure, reference numeral 1 is a first to m-th (m is an integer) n: 1 parallel-serial conversion means, which has the same structure as the one denoted by the same reference numeral in FIG. 17, but the first n: 1 The reset signal S41 from the parallel / serial conversion means is connected to the second n: 1 parallel / serial conversion means, and the reset signal S42 from the second n: 1 parallel / serial conversion means is the third n: 1 parallel / serial conversion means. Similarly, the reset signal S4m−1 from the (m−1) th n: 1 parallel / serial conversion means is connected to the mth n: 1 parallel / serial conversion means.

Further, FIG. 2 shows the above first to mth (m is an integer)
It is a block diagram which shows the n: 1 parallel-serial conversion means 1. In the figure, reference numeral 101 is a frequency division counter circuit, 102 is a latch circuit, and 103 is a selector circuit, which has the same configuration as that denoted by the same reference numerals in FIG. 18, but the frequency division counter circuit 101 has a reset signal S4m. -1 is input and the reset signal S4m is output.

Next, the operation will be described with reference to the timing chart shown in FIG. Here, for comparison with the conventional example, n = 4 and m = 2.

First, as an initial state, it is assumed that the address value of the frequency division counter circuit 101 in the first n: 1 parallel-serial conversion means 1 operates from "1" with respect to the change point of the parallel data S21. . Further, the frequency division counter circuit 101 starts counting based on the clock pulse S1, and when the frequency division counter address value becomes “2”, the latch circuit 102 holds the parallel data S21 and sends it to the selector circuit 103. . The selector circuit 103 outputs the data “a1” for the frequency division counter address value “3”, the data “a2” for “4”, and the data “a3” for “1”.
For serial data S for serial data S
It outputs as 31.

Similarly, as an initial state, it is assumed that the address value of the frequency division counter circuit 101 in the second n: 1 parallel / serial conversion means 1 operates from "2" with respect to the change point of the parallel data S22. Then, the data "b" of the serial data S32
The position of "1" is shifted by one bit with respect to the position of the data "a1" of the serial data S31 and is output.

Here, the first n: 1 parallel-serial conversion means 1
Of the reset signal S41 from the second n: 1 parallel / serial conversion means 1 at the position where the first frequency division counter address value is "4".
Since the frequency division counter 101 therein is reset, the second frequency division counter address value becomes equal to the phase of the first frequency division counter address value. Therefore, the data "a3" of the serial data S31 and the data "b3" of the serial data S32 are output in the same phase.

Further, since the reset signal S42 also has the same phase as the reset signal S41, when the operation control of the third n: 1 parallel-serial conversion means 1 is performed with m = 3, for example, the reset signal S42 is used. By resetting the frequency dividing counter 101 in the third n: 1 parallel / serial conversion means 1, all the first to third n: 1 parallel / serial conversion means 1 can be easily operated in the same phase.

FIG. 4 is a detailed circuit example showing the case of n = 4 of the frequency division counter 101 shown in FIG. In the figure, 1
001 to 1004 are flip-flops, 1005 is a 4-input NOR, and 1006 is an inverter, which constitutes a 4-bit ring counter. According to this, the reset signal S4m only needs to take the output of the flip-flop 1004 through the inverter 1006. In addition, in order to apply a reset, the reset signal S is input to the 4-input NOR 1005.
Since only 4m-1 needs to be input, the increase in circuit scale due to these functions is extremely small.

Example 2. FIG. 5 is a configuration diagram showing a second embodiment of the operation control system of the serial-parallel conversion circuit according to the present invention. In the figure, 4 is 1: n of the first to m-th (m is an integer)
The serial / parallel conversion means has the same configuration as that of the same reference numerals in FIG. 17, but the reset signal S41 from the first 1: n serial / parallel conversion means is the second 1: n serial / parallel conversion means. Means, the reset signal S42 from the second 1: n serial-parallel conversion means is connected to the third 1: n serial-parallel conversion means, and so on. The reset signal S4m-1 from the parallel conversion means is connected to the m-th 1: n serial-parallel conversion means.

Further, FIG. 6 shows the above first to mth (m is an integer)
It is a block diagram showing the 1: n serial-parallel conversion means 4 of. In the figure, 101 is a frequency division counter circuit, 102 is a latch circuit, and 104 is a shift register circuit, which have the same configuration as those denoted by the same reference numerals in FIG. 18, but the frequency division counter circuit 101 has a reset signal. S4m-1 is input,
The reset signal S4m is output.

Next, the operation will be described with reference to the timing chart shown in FIG. Here, for comparison with the conventional example, n = 4 and m = 2.

First, as an initial state, the address value of the frequency division counter circuit 101 in the first 1: n serial-parallel conversion means 4 is "1" with respect to the data "a1" of the serial data S31.
Suppose it is working from. The shift register circuit 104 sequentially shifts the serial data S31 based on the clock pulse S1, and the frequency division counter circuit 101 starts counting based on the clock pulse S1. When the frequency division counter address value becomes "4", The latch circuit 102 holds the data from the shift register circuit 104 all at once and outputs it as parallel data S21.

Similarly, as an initial state, the address value of the frequency division counter circuit 101 in the second 1: n serial-parallel conversion means 4 operates from "2" with respect to "b1" of the serial data S32. Then, the parallel data S22 is output in a phase different from the parallel expansion phase of the parallel data S21.

Here, the first 1: n serial-parallel conversion means 4
Reset signal S41 from the second 1: n serial-parallel conversion means 4 at the position where the first frequency division counter address value is "4".
Since the frequency division counter 101 therein is reset, the second frequency division counter address value becomes equal to the phase of the first frequency division counter address. Therefore, the parallel expansion phase of the parallel data S21 and the parallel expansion phase of the parallel data S22 are the same phase.

Further, since the reset signal S42 also has the same phase as the reset signal S41, when the operation control of the third 1: n series-parallel conversion means 4 is performed with m = 3, for example, the reset signal S42 is used. By resetting the frequency dividing counter 101 in the third 1: n series / parallel conversion means 4, all the first to third 1: n series / parallel conversion means 4 can be easily operated in the same phase.

Example 3. FIG. 8 is a configuration diagram showing a third embodiment of the operation control system of the parallel-serial conversion circuit according to the present invention. In the figure, 1 is the first to the m-th (m is an integer) n: 1.
It is a parallel-serial conversion means, and the divided clock S5 is input to the first n: 1 parallel-serial conversion means 1.

FIG. 9 is a block diagram showing the first n: 1 parallel-serial conversion means 1 described above. Reference numeral 105 denotes a phase comparison circuit for comparing the phases of the divided clock pulse S5 and the divided counter circuit 101. Is.

Next, the operation will be described with reference to the timing chart shown in FIG. First, as an initial state,
It is assumed that the address value of the frequency division counter circuit 101 in the first n: 1 parallel-serial conversion means 1 operates from "3" with respect to the change point of the parallel data S21. Frequency division counter circuit 1
01 starts counting based on the clock pulse S1,
When the frequency division counter address value becomes "2", the latch circuit 102 holds the parallel data S21 and the selector circuit 10
Send to 3. The selector circuit 103 outputs the data “a1” for the frequency division counter address value “3”, the data “a2” for “4”, and the data “a3” for “1”.
For serial data S for serial data S
It outputs as 31.

Here, the parallel data S of the latch circuit 102
If the timing of holding 21 is near the change point of the parallel data S21, the latch circuit 102 may malfunction. In order to prevent this, the phase comparison circuit 105 compares the phases of the divided clock pulse S5 synchronized with the change point of the parallel data S21 and the first divided counter address value, and the phase difference is within a predetermined prohibited phase range. If it is, the phase of the frequency division counter 101 is shifted by a predetermined bit (2 bits in FIG. 10). As a result, stable operation of the first n: 1 parallel-serial conversion circuit 1 becomes possible. Further, since the phase of the reset signal S41 also changes, the operation phase of the second n: 1 parallel-serial conversion circuit 1 reset by this also changes, and the same phase as that of the first n: 1 parallel-serial conversion circuit 1 Stable operation becomes possible.

FIG. 11 shows the phase comparison circuit 105 shown in FIG.
3 is a detailed circuit diagram showing the case where n = 4 of the frequency division counter 101. FIG. The frequency division counter 101 constitutes a 4-bit ring counter. The frequency division counter 101 is a 4-input NOR circuit 1.
The reset signal S4m-1 is input to 005, and the reset signal S4m is output via the inverter 1006 using a 4-bit ring counter. This operation is similar to that of the frequency division counter 101 shown in FIG. On the other hand, the phase comparison circuit 105 synchronizes with the divided clock pulse S5 between the second bit and the third bit of the 4-bit ring counter. The phase comparison circuit 105 outputs the output from the flip-flop 1002 to the flip-flop 1008.
Is input to the T flip-flop 1009. Further, the flip-flop 1008 inputs the divided clock pulse S5. The 2-input NAND 1010 is a flip-flop 1
Based on the signal from the flip-flop 1009 and the signal from the T flip-flop 1009, a synchronization signal for shifting the phase of the signal from the flip-flop 1002 of the second bit of the frequency division counter 101 is output. The 2-input AND 1007 is a phase comparison circuit 10
5 based on the synchronization signal from the flip-flop 1002
The signal from is transmitted to the flip-flop 1003. In this way, the phase comparison circuit 105 shifts the phase of the frequency division counter address value in accordance with the changing timing of the frequency division clock pulse S5. In this example, the case where the phase of the frequency division counter 101 is changed to the second bit has been described. In addition, the frequency division counter 101
When the phase of the reset signal S4m is changed to the second bit, the phase of the reset signal S4m is also changed.

Example 4. FIG. 12 is a configuration diagram showing a fourth embodiment of the operation control system of the serial-parallel conversion circuit according to the present invention. In the figure, 4 is 1: n of the first to m-th (m is an integer)
The phase control signal S6 is input to the first 1: n serial-parallel conversion means 4 which is a serial-parallel conversion means.

FIG. 13 is a block diagram showing a case where the serial-parallel conversion circuit shown in FIG. 12 is applied to a frame synchronization circuit in a receiving section of digital signal transmission.
-60062. In the figure, 5
Is a 1: k series / parallel conversion means, 6 is a 1: n series / parallel conversion means group composed of first to m-th 1: n series / parallel conversion means as shown in FIG. 12, 7 is a pattern detection means, 8
Is a frame synchronization determining means, 10 is a signal rearranging means, and 9 is
Is the phase control signal S6 and the select signal S from the frame synchronization pattern detection result S9 detected by the pattern detection means 7.
10 is a shift control means for generating 10 to control the 1: n serial / parallel conversion means group 6 and the signal rearranging means 10, respectively.

Next, the operation of FIG. 13 will be described. now,
The 1: k serial / parallel conversion means 5 performs 1: 2 serial / parallel conversion (k = 2) of the high-speed serial data S7, and the 1: n serial / parallel conversion means group 6 makes the serial data S31 to S3m 1: 4, respectively. It is assumed that serial / parallel conversion (n = 4) is performed.

First, in the 1: k serial-parallel conversion means 5, the received high-speed serial data S7 is converted into the high-speed clock pulse S8.
And two serial data S31 to S32 are output in parallel to the 1: n serial-parallel conversion means group 6 together with the clock pulse S1.

Next, in the 1: n series / parallel conversion means group 6,
1: two serial data S3 from the k-serial / parallel conversion means 5
1 to S32 are expanded in parallel to 4 and parallel data S2
1 to S22 are output to the signal rearranging means 4.

The parallel data S21 to S22 are also fetched by the pattern detecting means 7 to detect a predetermined frame synchronization pattern. This pattern detection means 7
The frame synchronization pattern detection result S9 is sent to the frame synchronization determination means 8 and the shift control means 9, and the frame synchronization determination means 8 determines the timing of the frame synchronization pattern detection position of the pattern detection means 7 and the built-in frame counter. , Provide well-known front and rear protection.

Here, when the parallel data S21 to S22 are not expanded in parallel in a predetermined order when the frame synchronization is restored, the shift control means 9 which detects the parallel data corresponds to the parallel expansion phase shift amount with respect to the predetermined order. The phase control signal S6 to the 1: n serial / parallel conversion means group 6 and the select signal S10 to the signal rearrangement means 10 are generated. The signal rearrangement unit 10 corrects the phase shift of the parallel expansion order by the 1: k serial / parallel conversion unit 5 according to the select signal S10. The phase control signal S6 corrects the phase shift in the parallel expansion order in the 1: n series / parallel conversion means group 6, but here, the phase control signal S6 is 1 with respect to the phase shift amount of the 1-bit parallel expansion order. Bit-width pulse, 2-bit width pulse with respect to 2-bit parallel expansion order phase shift amount, n
-1 for the phase shift amount in the parallel expansion order of 1 bit
The operation of the 1: n series-parallel conversion means group 6 configured by FIG. 12 will be described below with reference to FIGS. 14 and 15 in the case of generation as a pulse having a bit width.

FIG. 14 is a block diagram showing the first 1: n serial / parallel conversion means 4, and 106 is a phase control circuit for controlling the operating phase of the frequency division counter circuit 101 in accordance with the input phase control signal S6. is there.

Next, the operation will be described with reference to the timing chart shown in FIG. In the initial state, the first and second 1: n serial-parallel conversion circuits 4 operate in the same phase, but the parallel data S21 and the parallel data S
22 may not be the predetermined parallel expansion order. Here, there is shown a case where there is a 1-bit shift with respect to a predetermined parallel expansion order. To correct this, the phase control signal S
When a pulse having a 1-bit width of parallel data is input to 6, the phase control circuit 106 in the first 1: n serial-parallel conversion circuit 4 is input.
Shifts the phase of the first frequency division counter address value by 1 bit. As a result, the parallel data S21 has a predetermined parallel expansion order. On the other hand, since the phase of the reset signal S41 is also shifted by 1 bit, the phase of the second 1: n serial-parallel conversion circuit 4 which is reset by this is also shifted, and the parallel data S22 has the same phase as the parallel data S21 and the predetermined parallel data S22. It is a parallel expansion order.

FIG. 16 shows the phase control circuit 10 shown in FIG.
6 is a detailed circuit example showing the case where n = 4 of 6 and the frequency division counter circuit 101. The phase control circuit 106 is composed of a flip-flop 1011. Flip flop 1
011 outputs a reset signal to the frequency division counter circuit 101 according to the bit width of the phase control signal S6. The reset signal is the flip-flop 1 of the frequency division counter circuit 101.
003 is input to reset the flip-flop 1003. In this way, the phase control circuit 106 shifts the phase of the frequency division counter address value. Similarly, the phase of the reset signal S4m is also shifted.

In the above embodiment, the case where the parallel data expansion order is rearranged by decreasing the phase of the frequency dividing counter by "1" has been described, but it is "2" or "3".
Other values such as the above, and the frequency division ratio may be increased, and in any case, the same effect as that of the above-described embodiment is obtained.

[0053]

Since the present invention is constructed as described above, it has the following effects.

Since the frequency division counter in the n: 1 parallel / serial conversion circuit outputs a reset signal to reset the lower frequency division counter in the n: 1 parallel / serial conversion circuit, the operation is performed in the same phase. Even if the number of n: 1 parallel-serial conversion circuits to be controlled is increased, it is possible to suppress an increase in the circuit scale for performing operation control, and facilitate timing design and high-speed operation.

Further, since the frequency dividing counter in the 1: n serial-parallel conversion circuit outputs the reset signal and the lower frequency dividing counter in the 1: n serial-parallel conversion circuit is reset, the same phase is maintained. Even if the number of 1: n serial-parallel conversion circuits for controlling the operation is increased, similarly, it is possible to suppress an increase in the circuit scale for performing the operation control, and the timing design and high-speed operation are facilitated.

In the first n: 1 parallel-to-serial conversion circuit, the phases of the frequency-divided clock synchronized with the change point of the parallel data and the frequency-divided counter address are compared, and when the difference is within a predetermined prohibited phase range. By providing the phase comparison circuit that shifts the phase of the frequency division counter, all the n: 1 parallel-serial conversion circuits can be stably operated in the same phase.

A phase control circuit for controlling the operation phase of the frequency dividing counter is provided in the first 1: n serial-parallel conversion circuit so that the parallel data to be output has a predetermined parallel expansion order.
By controlling only the first 1: n serial / parallel conversion circuit, the parallel data output from all the 1: n serial / parallel conversion circuits can be in the same phase and in a predetermined parallel expansion order.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing an n: 1 parallel-serial conversion means according to the first embodiment of the present invention.

FIG. 3 is a timing diagram illustrating the operation of the first embodiment of the present invention.

FIG. 4 is a detailed circuit diagram of a frequency division counter circuit according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram showing a second embodiment of the present invention.

FIG. 6 is a configuration diagram showing a 1: n serial-parallel conversion means in Embodiment 2 of the present invention.

FIG. 7 is a timing diagram illustrating the operation of the second embodiment of the present invention.

FIG. 8 is a configuration diagram showing a third embodiment of the present invention.

FIG. 9 is a configuration diagram showing an n: 1 parallel-serial conversion means according to a third embodiment of the present invention.

FIG. 10 is a timing diagram illustrating the operation of the third embodiment of the present invention.

FIG. 11 is a detailed circuit diagram of a phase comparison circuit and a frequency division counter circuit according to a third embodiment of the present invention.

FIG. 12 is a configuration diagram showing a fourth embodiment of the present invention.

FIG. 13 is a configuration diagram showing a frame synchronization circuit using a serial-parallel conversion circuit according to a fourth embodiment of the present invention.

FIG. 14 is a configuration diagram showing a 1: n series-parallel conversion means in embodiment 4 of the present invention.

FIG. 15 is a timing diagram illustrating the operation of the fourth embodiment of the present invention.

FIG. 16 is a detailed circuit diagram of a phase control circuit and a frequency division counter circuit according to a fourth embodiment of the present invention.

FIG. 17 is a configuration diagram showing an operation control system of a conventional parallel-serial conversion circuit.

FIG. 18 is a configuration diagram showing a conventional n: 1 parallel-serial conversion means.

FIG. 19 is a timing diagram illustrating an operation control system of a conventional parallel-serial conversion circuit.

FIG. 20 is a configuration diagram showing an operation control system of a conventional serial-parallel conversion circuit.

FIG. 21 is a configuration diagram showing a conventional 1: n serial-parallel conversion means.

FIG. 22 is a timing diagram illustrating an operation control system of a conventional serial-parallel conversion circuit.

[Explanation of symbols]

 1 n: 1 parallel / serial conversion means 4 1: n serial / parallel conversion means 101 frequency division counter circuit 105 phase comparison circuit 106 phase control circuit S21 to S2m parallel data S31 to S3m serial data S41 to S4m reset signal S5 frequency division clock pulse S6 Phase control signal

Claims (6)

[Claims] 1. At least first and second parallel-serial conversion circuits, wherein the first parallel-serial conversion circuit outputs a reset signal for resetting the second parallel-serial conversion circuit,
The operation control method of the parallel-serial conversion circuit, wherein the second parallel-serial conversion circuit performs reset processing based on a reset signal from the first parallel-serial conversion circuit. 2. The operation control system of the parallel-serial conversion circuit further comprises a third parallel-serial conversion circuit, wherein
Parallel-serial conversion circuit outputs a reset signal for resetting the third parallel-serial conversion circuit based on the reset signal from the first parallel-serial conversion circuit, and the third parallel-serial conversion circuit is the third parallel-serial conversion circuit. 2. The operation control system of the parallel-serial conversion circuit according to claim 1, wherein reset processing is performed based on a reset signal from the parallel-serial conversion circuit 2. 3. The first parallel-serial conversion circuit detects a phase difference between a phase of parallel data to be parallel-serial converted and a phase of parallel-serial conversion operation, and based on the phase difference, the parallel-serial conversion operation is performed. The operation control system of the parallel-serial conversion circuit according to claim 1, further comprising a phase comparison circuit that shifts the phase. 4. At least first and second serial-parallel conversion circuits, wherein the first serial-parallel conversion circuit outputs a reset signal for resetting the second serial-parallel conversion circuit,
The operation control method of the serial-parallel conversion circuit, wherein the second serial-parallel conversion circuit performs reset processing based on a reset signal from the first serial-parallel conversion circuit. 5. The operation control system of the serial-parallel conversion circuit further comprises a third serial-parallel conversion circuit, wherein
Of the serial-parallel conversion circuit outputs a reset signal for resetting the third serial-parallel conversion circuit based on the reset signal from the first serial-parallel conversion circuit, and the third serial-parallel conversion circuit is the third serial-parallel conversion circuit. 5. The operation control system of the serial-parallel conversion circuit according to claim 4, wherein the reset process is performed based on the reset process from the serial-parallel conversion circuit 2. 6. The operation control system for a serial-parallel conversion circuit according to claim 4, wherein the first serial-parallel conversion circuit includes a phase control circuit for shifting the phase of the serial-parallel conversion operation.