JP2621668B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit in digital transmission, and in particular, to a TSSI (Time s
The present invention relates to a means for configuring a high-speed synchronous circuit on a small scale while securing lot sequence integrity.

[0002]

2. Description of the Related Art Hitherto, a frame synchronizing circuit for a high-speed digital signal has been proposed in FIG.
The configuration was as follows. The high-speed digital signal on the digital transmission line is subjected to serial / parallel conversion at the input of the frame synchronization circuit so as to reduce the speed of signal processing at the next stage and thereafter, and is converted into a digital signal of 1 / N speed.
In FIG. 2, the serial-parallel conversion is 1: 4 (N = 4) as an example, but the division ratio is not limited to this. In order to detect a frame synchronization pattern, the digital signals whose speed has been reduced in parallel are subjected to pattern matching for a specific channel by a synchronization pattern detection circuit 3 comprising a shift register. Now, when a frame collation pattern is input as an input signal, the parallel output of the serial-parallel conversion circuit 1 may be switched to cycling by the number corresponding to the number of divisions, depending on the initial state of the frequency division counter 2. The channel selector 5 is controlled in accordance with which pattern is compared, and the order of the output data is changed in accordance with the order of the input pattern. On the other hand, the frame information detected by the synchronization pattern detection circuit 3 is output by the synchronization position detection circuit 4 as a frame synchronization pulse.

[0003]

The above-described conventional frame synchronization circuit detects a synchronization pattern after serial-to-parallel conversion. However, since the order of output data is changed according to the initial state of the frequency division counter, the synchronization pattern sequence is not changed. Therefore, a channel selector for switching the order of the output data series is required in accordance with the above, and there is a disadvantage that the circuit becomes large-scale.

[0004]

A frame synchronization circuit according to the present invention has a synchronous pattern detection circuit connected to an output of a serial / parallel conversion circuit controlled by a frequency dividing counter, and a serial / parallel connection is output by an output of a synchronous position detection circuit. It has a configuration for controlling a delay circuit connected to the preceding stage of the conversion circuit.

[0005]

Next, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention. A synchronous pattern detecting circuit 3 composed of a shift register is connected to an arbitrary output of the serial-parallel conversion circuit 1, and a detection result is transmitted to a synchronous position detecting circuit 4.
, And controls the delay circuit 6 connected before the serial-parallel conversion circuit 1. The high-speed digital signal input to the frame synchronization circuit is separated into four series by the serial / parallel conversion circuit 1. Pattern matching is performed by the synchronous pattern detection circuit 3 on an arbitrary sequence. At this time, depending on the initial state of the frequency division counter 2, there may be cases where four types of collation patterns are encountered, and the output of the serial-parallel conversion circuit 1 may be switched cyclically. Now, in the frame synchronization circuit, (... F6F62828 ...) h =
(... 1111011000101000 ...) The case where the repetition digital signal is input is demonstrated. At this time, the output of the serial-parallel conversion circuit 1 has the states of Case 1 to Case 4 as shown in FIG. In each case of Case 1 to Case 4, pattern matching is performed by the synchronous pattern detection circuit 3 and Cas
The synchronous position detection circuit 4 supplies a control pulse to the delay circuit 6 connected to the preceding stage of the serial-parallel conversion circuit 1 in accordance with which of the patterns e1 to Case4 the pattern is matched, thereby reducing the delay amount of the input DATA by 1 bit. The first bit of the frame collation pattern (frame synchronization pattern) is from the output signal 1 of the serial-parallel conversion circuit 1, the second bit is the output signal 2 of the serial-parallel conversion circuit 1, and the third bit is the serial-parallel conversion circuit 1. The fourth bit can be extracted from the output signal 4 of the serial-parallel conversion circuit 1 from the output signal 3 of FIG.

[0006]

As described above, according to the present invention, the output of the serial / parallel conversion circuit controlled by the frequency dividing counter is connected to the synchronous pattern detecting circuit, and the synchronous position detecting circuit
The frame synchronization circuit, which establishes bit synchronization and selects the channel of the output data signal, controls the delay circuit connected in front of the serial-parallel conversion circuit according to the sequence of the synchronization check pattern, and changes the amount of delay By letting
There is an effect that an extremely small-scale and high-speed frame synchronization circuit can be realized.

[Brief description of the drawings]

FIG. 1 is an embodiment of the present invention.

FIG. 2 is a prior art of the present invention.

FIG. 3 is an operation principle of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Serial-parallel conversion circuit 2 Dividing counter 3 Synchronization pattern detection circuit 4 Synchronization position detection circuit 5 Channel selector 6 Delay circuit

Claims (2)

(57) [Claims] A digital signal having a predetermined frame synchronization pattern is serial-to-parallel converted, and first to N-th signals synchronized with a clock output frequency-divided by a frequency division counter.
(N is an integer of 2 or more) a serial-parallel conversion circuit that generates a parallel output, and only one of the first to N-th parallel outputs is input, and the frame synchronization pattern is predetermined. A synchronous pattern detection circuit for determining which one of the first to Nth patterns has been matched, and a digital signal connected to a stage preceding the serial-parallel conversion circuit for delaying the digital signal, And a delay circuit that applies the serial-parallel conversion circuit to the serial-parallel conversion circuit, and is connected to the synchronization pattern detection circuit, and according to which of the first to Nth patterns the frame synchronization pattern matches. The delay amount of the delay circuit is controlled so that the first to Nth bits of the frame synchronization pattern can be respectively taken out as the first to Nth parallel outputs of the serial / parallel conversion circuit. Frame synchronization circuit, characterized in that it comprises a synchronization position detector that way. 2. The frame synchronization circuit according to claim 1, wherein said synchronization pattern detection circuit has a shift register.