JPS63294151A - Parallel type frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To obtain a synchronism restoring characteristic which is equivalent to that of a 1-bit instantaneous shifting system, by providing a means which controls a selection circuit by using the output signal of a storing means and taking frame synchronism by detecting a frame synchronous pattern from (r) pieces of low-speed signals outputted from the selection circuit. CONSTITUTION:A monitoring means 2 which monitors part of signals of a frame synchronous pattern contained in (m) pieces of specific low-speed signals in the low-speed signals which are parallel-developed to (n+r-1) pieces and outputs a monitored result as parallel-developing phase signals of a parall- developed frame synchronous pattern, is provided. In addition, a storing means 3 which stores phase signals from the monitoring means 2 and a controlling means 9 which controls a selection circuit 1 by using the output signal of the monitoring means 2 at the time of hunting operations, during which a frame synchronous pattern is searched, and by using the output signal of the storing means 3 in the other case, are provided and frame synchronism is taken by detecting a frame synchronous pattern from signals outputted from the selection circuit 1. Therefore, a synchronism restoring characteristic equivalent to the one-bit instantaneous shifting system can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a frame synchronization circuit used in a digital communication device, and particularly relates to a low-speed parallel signal obtained by expanding input signals in n (an integer of 2 or more) in parallel. The present invention relates to a parallel frame synchronization circuit that performs frame synchronization for various types of frames.

[Conventional technology]

Regarding the conventional parallel frame synchronization technology, there is Japanese Patent Application Laid-Open No. 61-5641. In this prior art, a frame synchronization pattern detection circuit is connected to the output of the signal selection circuit, and when no frame synchronization pattern is detected, the frame counter is immediately shifted by 1 bit for one low-speed clock after parallel expansion. Frame counter is 1
If the frame synchronization pattern is not detected even after shifting by one frame, select the signal selection circuit and shift the output signal from the selection circuit by one phase with respect to the high speed clock before parallel expansion. It is configured to search for frame synchronization patterns.

According to the above-mentioned conventional technology, the worst average synchronization return time Ts, which is an index of the performance of the frame synchronization circuit, can be approximately determined by the following formula.

Here, n is the number of parallel expansions, T is the frame period, and r is 1
The number of bits of the frame synchronization pattern of the series, N is the total number of bits of the frame, K is the number of series of frame synchronization patterns included in one frame, P is the number of bits of the frame synchronization pattern included in the comparison target. The worst average synchronization return time T/8 using the 1-bit immediate shift method compared in the published patent publication disclosing the prior art is approximately determined by the following formula.

Here, Tf, N, r and P have the same meanings as in the case of formula (1) for T8 above.

[Problem that the invention seeks to solve]

If there is a relationship between p, n, r, and N as described above, it will be equivalent to the worst average synchronization recovery time of the parallel frame synchronization method according to the prior art. However, if the above equation (3) does not hold, there is a problem that the worst case average synchronization return time is significantly longer than in the 1-bit immediate shift method.

An object of the present invention is to provide a parallel frame synchronization circuit that can shorten the worst average synchronization recovery time of a parallel frame synchronization circuit to the same level as a 1-bit immediate shift method and improve synchronization recovery characteristics without being subject to the limitations of equation (3). Our goal is to provide the following.

[Problems and means to solve them]

The above purpose is to monitor a part of the frame synchronization pattern included in specific m low-speed signals among (n + r-1) low-speed signals developed in parallel, and to parallelize the monitoring results. monitoring means for outputting the developed frame synchronization pattern as a parallel development phase signal, storage means for storing the phase signal from the monitoring means, and selection according to the output signal from the monitoring means during a hunting operation to search for the frame synchronization pattern. A control means for controlling the circuit and, in other cases, controlling the selection circuit by the output signal from the storage means is provided, and the frame synchronization pattern is detected from the signal output from the selection circuit and frame synchronization is performed. achieved by things.

[Effect]

The monitoring means monitors specific m low-speed signals among (n+r-1) input to one selection circuit, and detects a partial pattern of the r-bit frame synchronization pattern. Among the parallel expansion phases of , a unique phase that is likely to be the parallel expansion phase of the frame synchronization pattern is determined, and the parallel expansion phase is output as a signal. During a hunting operation in which a frame synchronization pattern is searched, the control means controls a selection circuit using the parallel expansion phase signal output from the monitoring means, and selects r signals whose phase is synchronized with the parallel expansion phase of the frame synchronization pattern. , output from the selection circuit. At this time, a frame synchronization pattern is detected for the r parallel output signals from the selection circuit by a detection means for detecting a frame synchronization pattern. If a frame synchronization pattern is not detected, the above-mentioned hunting operation is continued; if a frame synchronization pattern is detected, the state shifts to the phase synchronization operation state, and the parallel expansion phase in which the frame synchronization pattern is detected is memorized. The contents of the stored storage means are held until the frame counter operates and the timing for detecting the next frame synchronization pattern comes, and during that time, the control means controls the selection circuit using the parallel expansion phase signal output from the storage means.
Selectively output signals. In this case, at the next frame synchronization pattern detection timing, the frame synchronization pattern is detected for the signal output from the selection circuit by using the signal output from the storage means as a control signal, and the frame synchronization pattern is detected. If detected, the above-mentioned phase synchronization operation state is continued, and if no detection is detected, the above-mentioned notching operation state is entered and a frame synchronization pattern is searched.

Through the above operation, it is possible to obtain synchronization recovery characteristics equivalent to the one-bit instant shift method.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a parallel frame synchronization circuit according to a first embodiment of the present invention. In this embodiment, the number of parallel expansions n is 4, and the number of bits r of the frame synchronization pattern is 4. The frame synchronization circuit of this embodiment has input signals D1 to D4.
are input in parallel, and of these, D4 is the most significant bit (MSB) of the signal, and D4 is the least significant bit (LSB). Of the input signals D2 to D4, D2 to D4 are input to a delay circuit 5 that delays the signal by 1 bit, and the input signals D2 to D4 are
401-pit delay signals D'2 to D'4 are output from the delay circuit 5, and are input to the selection circuit 1 together with the input signals D1 to D4. Signal D input to selection circuit 1
D'4 of I2-D'4 and -D4. The three signals D and D2 are input to the monitoring circuit 2, and the monitoring circuit 2
A parallel expanded phase signal outputted from the control circuit 9 and the storage circuit 3 are input to the control circuit 9 and the storage circuit 3. The control circuit 9 receives a phase signal from the storage circuit 3 in addition to the phase signal from the monitoring circuit 2,
One of them is selected and applied to the selection circuit 1 as a control signal. The selection circuit 1 selects the input signals D'2 to D'4 and 7 to D4 according to the control signal from the control circuit 9.
Four parallel signals s to b4 are selected from among the signals and output. For example, if the control signal indicates phase ■,
Input signal D'2. D'3. D'4゜D, is the parallel signal b1
~b4, and when the control signal indicates phase ■, input signals D', , D'4. D.

D2 is output as a parallel signal ~b4.

The synchronization pattern detection circuit 4 receives this output signal.

A frame synchronization pattern is detected from ~b4 and input to the pattern match determination circuit B, and the pattern match determination circuit 6 determines whether or not a frame synchronization pattern is detected at the frame detection timing received from the frame counter 8. The determination result is sent to the control circuit 9 and the AND circuit (AN
D circuit) Output to 7. The AND circuit 7 receives the input signal,
The input clock having the same rate as ~D4 and the signal from the pattern matching determination circuit 6 are ANDed and outputted to the frame counter 8.

Next, the operation of the parallel frame synchronization circuit shown in FIG. 1 will be explained. FIG. 2 shows four possible parallel expansion phases of the frame synchronization pattern included in the seven parallel signals D'2 to D'4 and D4 inputted to the selection circuit 1. It 1100If arranged vertically in Figure 2
This pattern is the frame synchronization pattern in this case. Moreover, the X mark in the figure is a random signal other than the frame synchronization pattern.

First, the hunting operation state will be explained.

In this embodiment, among the signals D'2 to D'4 and -D4, the signal D'4. D, and D2, and the second
The monitoring circuit 2 determines only one possible phase from among the four parallel expansion phases indicated by ■ to ■ in the figure.

FIG. 3 shows an example of the configuration of the monitoring circuit 2 in the embodiment. In the monitoring circuit of FIG. 3, the phase of ■: P2=0. P,=O2■
Phase of ' P 2"Oy P 1 "' + Phase of ■:
P 2”'1 r P 1 =0+■ Phase: P2=
'yP is set to 1 and output as parallel expansion phase signals P1+P2, respectively. At this time, the X mark in FIG. 2 is not affected by the signal value. Therefore, in the embodiment, even if the frame synchronization pattern "11001" exists at any phase in the seven parallel signals D'2 to D'4 and D1 to D4, the only correct phase is determined by the monitoring circuit 2. By applying the parallel expansion signal output from the monitoring circuit 2 to the selection circuit 1 as a selection control signal through the control circuit 9, the output signals S to b4 from the selection circuit 1 can be converted into a frame synchronization pattern. The detection of the frame synchronization pattern is performed by the synchronization pattern detection circuit 4 for the output signals S to B4 of the selection circuit 1. The four cases of phase ■ to ■ in Figure 2 are monitored as described above, and the frame synchronization pattern is detected for the signal selected by the selection circuit 1 based on the results. Therefore, the synchronization pattern detection circuit 4 is equivalent to simultaneously detecting four types of frame synchronization patterns of phases ■ to ■ in Fig. 2.The hunting operation is the operation described above, and the synchronization pattern detection circuit 4 The detection circuit 4 detects the frame synchronization pattern If l i 00
This continues until II is detected. If a frame synchronization pattern is detected, a transition is made to the phase synchronization state described below.

In the phase synchronization state, first, the phase signal from the monitoring circuit 2 at the time when the frame synchronization pattern is detected is stored in the storage circuit 3.
This content is stored in the frame counter 8 until the detection timing of the next frame synchronization pattern is reached.During this time, the control circuit 9 uses the parallel development phase signal output from the storage circuit 3 to select the selection circuit 1. and selects four signals to output from the selection circuit 1. In this case, at the detection timing of the next frame synchronization pattern, the signal output from the storage circuit 3 is output from the selection circuit 1 as a control signal. The synchronization pattern detection circuit 4 performs pattern detection on the received signal, and if a frame synchronization pattern is detected, the above-mentioned phase synchronization operation state is continued, and if no frame synchronization pattern is detected, the above-mentioned) Transition to operational state.

The pattern match determination circuit 6 and frame counter 8 are
The operation is the same as in the prior art.

Through the above-described operation, the first embodiment of the present invention can obtain synchronization recovery characteristics equivalent to those of the 1-bit immediate shift method. The frame structure having the frame synchronization pattern shown in Fig. 2 is currently used in the 5th order group transmission line, and its specifications are as follows: frame period T, -4867 μs.
, number of bits of one series of frame synchronization pattern r =
4 bits, total number of bits in the frame N = 1556 bits, number of series of frame synchronization patterns in one frame = 2
In the case of 4-parallel operation as in the first embodiment, the worst average synchronization recovery time using the conventional method is 2159 μs.
In contrast, according to the first embodiment, the time is 201.7 μs, which improves the synchronization return characteristic.

FIG. 4 shows the configuration of a parallel frame synchronization circuit according to a second embodiment of the present invention. In this example, the number of parallel expansions n is 8, and the number of bits r of the frame synchronization pattern is 1.
This is case 2.

The parallel frame synchronization circuit of the second embodiment includes delay circuits 15 and 25, a selection circuit 11, a synchronization pattern detection circuit 14,
Pattern match determination circuit 16, frame counter 18, control circuit 19, monitoring circuit 12, memory circuit 13 and AND
It is composed of a circuit 17. The configuration is basically the same as the first embodiment, and the number n of parallel expansions is 8, while the frame synchronization pattern r is 12. Therefore, in order to increase the number of parallel expansions, an additional stage is provided after the delay circuit 15. 1 delay circuit 2
The only difference is that 5 is provided.

In the second embodiment, the frame synchronization pattern "111110
Frame synchronization is achieved by 1000001'.
In this case, DI6 to D-2D input to the selection circuit 11
', ~Iy8. Out of a total of 19 parallel signals D, to D8, a total of five signals D'5 to DI8 and Dl are monitored by the monitoring circuit 12, so that the signal selection of the selection circuit 11 can be made correctly through the control circuit 19. I can do it.

The other operations are the same as in the first embodiment, so the explanation will be omitted. The frame having the frame synchronization pattern of this embodiment corresponds to a European digital fourth-order group frame, and is 〒1 =21.02 s s s
r = 12 bits.

When N = 2928 bits and a value of -1 is taken and 8 parallel processing is performed as in the embodiment, the worst average synchronization recovery time is 183.3 μS when using the conventional method, whereas in this embodiment According to the method, the time is 36.2 μS, and the synchronization return characteristic is significantly improved.

[Effects of the Invention] According to the present invention, while maintaining the feature of the parallel frame synchronization method that processing operations can be performed at a lower speed than the one-pit instant shift method at the same input signal rate,
Synchronization recovery characteristics equivalent to the bit immediate shift method can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the first embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation of the first embodiment, Fig. 6 is a detailed block diagram of the monitoring circuit in the first embodiment, and Fig. 4 is a diagram of the present invention. FIG. 2 is a configuration diagram of a second embodiment of the invention. 1.11...Selection circuit, 2,12...
Monitoring circuit, 6.13... Memory circuit, 4,14.
...Synchronization pattern detection circuit, 5, 15, 25...
... Delay circuit, 6゜16 ... Pattern match judgment circuit, 8, 18 ... Frame counter, 9
．． 19... Control circuit.

Claims (1)

[Claims] 1. Expand one received signal in parallel into n (an integer where n≧2) low-speed signals, and calculate the number of bits r (where r≧n) included in the n low-speed signals that have been expanded in parallel. In a parallel frame synchronization circuit that detects a frame synchronization pattern (an integer) and performs frame synchronization, n low-moderate signals expanded in parallel are delayed to form a total of (n+r-1) parallel low-speed signals. a selection circuit that selects and outputs r low speed signals from the (n+r-1) parallel low speed signals;
detection means for detecting a frame synchronization pattern from the r low-speed signals from the selection circuit; and a frame included in specific m low-speed signals among the (n+r-1) parallel low-speed signals. monitoring means for monitoring a signal of a part of the synchronization pattern and outputting the monitoring result as a parallel development phase signal of the frame synchronization pattern developed in parallel; storage means for storing the phase signal from the monitoring means; and detection by the detection means. When the signal is not obtained at the frame pulse timing, the frame pulse is shifted and controlled, and the selection circuit is controlled by the output signal from the monitoring means, so that the detection signal of the detection means is obtained at the frame pulse timing. control means for holding the contents of the storage means until the timing of the next frame pulse and controlling the selection circuit according to an output signal from the storage means, A parallel frame synchronization circuit that detects a frame synchronization pattern from a low-speed signal and performs frame synchronization.