JP3264586B2 - Pattern synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern synchronizing circuit for establishing bit synchronization between an input data signal and a comparison pattern signal prior to comparing and collating an input data signal with a comparison pattern signal as a comparison reference. .

[0002]

2. Description of the Related Art For example, an error test apparatus for evaluating a bit error occurring in a transmission process or a data transmission / reception process among various tests on a transmission / reception device and a transmission line in a digital communication network is configured as shown in FIG. .

In this error test apparatus 1, a test signal a having a predetermined bit pattern having a prescribed bit period N ₀ is applied from a test signal generator 3 to a test object 2 such as a data transmitting / receiving apparatus or a transmission line. I do. The test signal a is input again into the error test apparatus 1 via the test object 2 as the input data signal b. The input data signal b input to the error test apparatus 1 is input to the pattern synchronization circuit 4 and the clock recovery circuit 5.

The clock recovery circuit 5 recovers the clock signal c from the input data signal b and sends it to the pattern synchronization circuit 4. The pattern synchronization circuit 4 includes an error detection circuit 6 and a comparison pattern generation circuit 7. Comparative pattern generating circuit 7 outputs a comparison pattern signal having a predetermined bit pattern of the same specified bit cycle N ₀ and the test signal a.
The pattern synchronizing circuit 4 includes a comparison pattern generating circuit 7
The bit synchronization between the comparison pattern signal output from the input data signal b and the input data signal b is established using the error detection circuit 6.

When the bit synchronization is established, the error detection circuit 6 detects a bit error of the input data signal b by comparing it with a comparison pattern signal. Error signal e
Is sent to the error rate measurement unit 8. The error rate measuring unit 8 measures a bit error rate using the error signal e.

FIG. 9 is a detailed block diagram of the pattern synchronization circuit 4. The clock signal c shown in FIG. 10 input from the clock recovery circuit 5 is input to the clock inhibition (inhibit) circuit 9. When the clock inhibition circuit 9 receives the clock inhibition signal h from the synchronization determination control circuit 11,
As shown by 0, the passage of one clock of the input clock signal c is prohibited. Therefore, the clock signal c ₁ output from the clock inhibition circuit 9 has a portion where no clock exists.

The clock signal c ₁ output from the clock inhibition circuit 9 is divided by the frequency divider 10 a in the serial / parallel conversion circuit 10 to 1 / n. Here, n is a positive integer. The frequency-divided clock signal c ₂ shown in FIG. 10 output from the serial-parallel conversion circuit 10 is input to the next comparison pattern generation circuit 7. The comparison pattern generation circuit 7 generates a comparison pattern signal having a predetermined bit pattern of the above-described prescribed bit period N ₀ and sends it to the next error detection circuit 6 as a comparison pattern signal g of n parallel rows.

On the other hand, the input data signal b input from the test object 2 is converted into n columns of input data signals b _{1 by} an S / P (serial / parallel) converter 10 b in the serial / parallel conversion circuit 10.
Is converted to The input data signal b ₁ of n parallel columns output from the serial / parallel conversion circuit 10 is input to the next error detection circuit 6.

The error detection circuit 6 compares the n-th comparison signal pattern g with the n-th input data signal b _1, and if they do not match, sends an error signal e to the synchronization determination control circuit 11. When an error signal e equal to or more than a predetermined ratio is input, the synchronization determination control circuit 11 determines that synchronization has been lost, and sends a synchronization non-establishment signal to the error rate measurement unit 8. In addition, as the predetermined ratio,
Depending on the pattern contents by using, e.g., an error number ¹⁰⁴ bits, etc. per clock ¹⁰⁵ bits is employed.

When the synchronization is not established, the synchronization determination control circuit 11 sends a clock inhibition signal h to the clock inhibition circuit 9 every time a predetermined number of error signals e are input. The predetermined number depends on the operating frequency of the clock, but usually a number of 100 or less is used.

When the ratio of the error signal e from the error detection circuit 6 is equal to or less than a predetermined value, the synchronization determination control circuit 11 determines that synchronization has been established and changes the synchronization non-establishment signal to the synchronization establishment signal i. At the same time, the clock inhibition operation is stopped. As the ratio of the predetermined value, for example, the pattern period N
_A case where there is no error consecutively for the same number as ₀ is adopted.

FIG. 10 is a time chart showing the operation of the pattern synchronization circuit 4. In FIG. 10,
For the sake of simplicity, the input data signal b and the comparison pattern signal g have a specified bit period N ₀ of 4, and the bit pattern is a repeating pattern of [abcd],
Further, it is assumed that the frequency division ratio n is 2.

First, since the bit phases of the input data b ₁ in two parallel rows do not match the bit phases of the comparison pattern signal g in the two parallel rows, synchronization is not established. An inhibit signal h is sent. As a result, one clock disappears in the clock signal c _1, one bit data corresponding to the extinction clock in the input data signal b (in FIG. 10 [b])
Is not converted to a parallel signal by the S / P converter 10b,
The bit phase of the input data signal b ₁ in the n (= 2) column output from the serial-parallel conversion circuit 10 advances by one.

On the other hand, assuming that a divided clock signal c ₂ partially having a clock having a long pulse width is input, bit data is not included in the comparison pattern signal g of n columns output from the comparison pattern generation circuit 7. Since it does not disappear, the bit phase does not change.

[0015] Thus, every time the clock inhibit signal h is outputted, the bit phase of the input data signal b ₁ goes in one by one as compared to the comparison pattern signal g. Thus, as long as the error signal e is output from the error detection circuit 6,
The bit phase changes sequentially. When the ratio of the error signal e from the error detection circuit 6 becomes equal to or less than a predetermined value, it is determined that the input data signal b ₁ has been bit-synchronized with the comparison pattern signal g, and the synchronization determination circuit 11 outputs a synchronization establishment signal i. .

[0016]

However, the pattern synchronization circuit 4 shown in FIG. 9 still has the following problems to be solved. That is, in order to improve the manufacturing productivity of the test apparatus itself and to reduce the size and weight of the apparatus itself, the pattern synchronization circuit 4 is replaced with an ASIC (IC for specific application).
It is eager to make it. However, in general, the frequency of a digital signal handled by a transmission line in a digital communication network or a data transmission / reception device may be as high as several hundred MHz, but the speed is reduced to 1 / n by the serial / parallel conversion circuit 10. Each signal c ₂ , B ₁ The comparative pattern generation circuit 7, the error detection circuit 6, the synchronization determination control circuit 11 and the like which handle the above can be easily and inexpensively formed into an ASIC.

However, the high-speed clock signal before the frequency division is performed.
No. c, c ₁ In order to incorporate the clock inhibition circuit 9 and the serial / parallel conversion circuit 10 to which the input data signal b is input into the ASIC, the ASIC itself needs to be composed of expensive electronic parts that can withstand high speed, and the ASIC itself is very Become expensive.

In order to avoid such a situation, the clock input to the clock inhibition circuit 9 is shifted by moving the clock inhibition circuit 9 between the serial / parallel conversion circuit 10 and the comparison pattern generating circuit 7. Signal speed 1 /
The speed can be reduced to n. Therefore, the serial-parallel conversion circuit 10
Other than the clock inhibition circuit 9, the comparison pattern generation circuit 7,
The error detection circuit 6 and the synchronization determination control circuit 11 can be easily formed into an ASIC at low cost.

However, if the clock inhibit circuit 9 is located after the serial / parallel conversion circuit 10, the following problem occurs. When synchronization judgment control circuit 11 from the clock inhibit signal h is sent, one clock of the divided clock signal c ₂ disappears. As a result, each time the clock inhibition signal h is output, the n-column comparison pattern signal g output from the comparison pattern generation circuit 7 and the n-column input data signal b ₁ output from the serial / parallel conversion circuit 10 are output. The bit phase difference between them changes by n bits. Since no Ika change 1 bit phase at a time, even if sent many times clock inhibit signal h, resulting sometimes forever both signals g, b bit synchronization between ₁ is not established.

A specific example will be described with reference to FIGS. [Abcd] at division ratio n = 2 and bit period N ₀ = 8
efgh] input data signal b having a bit pattern
, The comparison pattern signals g and n (=
2) an input data signal b ₁ column, by chance, when was the relationship shown in FIG. 11, when sent repeatedly clock inhibit signal h, always synchronization is established.

However, if the comparison pattern signal g and the input data signal b ₁ have the relationship shown in FIG. 12, synchronization is not established no matter how many times the clock inhibit signal h is transmitted. The present invention has been made in view of such circumstances, and even if a clock inhibit circuit is inserted after a serial-to-parallel conversion circuit, it is possible to reliably establish bit synchronization between an input data signal and a comparison pattern signal. Accordingly, it is an object of the present invention to provide a pattern synchronous circuit that can incorporate a clock inhibiting circuit into an ASIC that operates at a low speed and that can be reduced in size, weight, and cost.

[0022]

In order to solve the above-mentioned problems, a pattern synchronization circuit according to the present invention divides an input clock signal into 1 / n (n; a positive integer of 2 or more) and divides the input clock signal by a divided clock signal. And a serial-to-parallel conversion circuit that converts a serial input data signal having a known cycle into an n-column input data signal and outputs the same, and an n-column having a known cycle in synchronization with the frequency-divided clock signal. A comparison pattern generation circuit that outputs a comparison pattern signal, and one or more continuous clocks in the divided clock signal that are interposed between the serial-to-parallel conversion circuit and the comparison pattern generation circuit and that respond to the input of the clock inhibition signal A clock inhibiting circuit for inhibiting the passage of a selection signal, and every time a selection signal is input, the output bit phase of the comparison pattern signal of n columns output from the comparison pattern generation circuit is sequentially changed An error signal when the n-column comparison pattern signal having the bit phase selected by the phase selection circuit and the n-column input data signal output from the serial / parallel conversion circuit do not match. It is determined that synchronization is not established when an error detection circuit that outputs and an error signal output from the error detection circuit is equal to or greater than a predetermined ratio, and is determined that synchronization is established when the output ratio of the error signal is less than the predetermined ratio. Until a predetermined number of error signals are output from the error detection circuit, a selection signal is output to the phase selection circuit, and a clock inhibition signal is output to the clock inhibition circuit when the number of transmissions of the selection signal exceeds a predetermined number. And a synchronization determination control circuit.

Further, in another invention, the phase selection circuit in the above invention is moved between the serial / parallel conversion circuit and the error detection circuit. The phase selection circuit sequentially changes the output bit phase of the input data signal of n columns output from the serial / parallel conversion circuit every time the selection signal is input from the synchronization determination control circuit. Further, the error detection circuit according to the present invention determines whether or not the input data signal of n columns having the bit phase selected by the phase selection circuit matches the comparison pattern signal of n columns output from the comparison pattern generation circuit. Is detected.

[0024]

In the pattern synchronizing circuit thus constructed, n columns of comparison pattern signals output from the comparison pattern generation circuit via the phase selection circuit and n columns of input data signals output from the serial / parallel conversion circuit are provided. When the synchronization of the bit phase is not established between the clock determination circuit and the synchronization determination control circuit, first, a clock inhibition signal is sent from the synchronization determination control circuit to the clock inhibition circuit. As a result, the bit phase between the comparison pattern signal and the input data signal changes by n bits. If the bit phases have not yet been synchronized at the time of the change by n bits, a selection signal is sent from the synchronization determination control circuit to the phase selection circuit. The phase selection circuit changes the output bit phase of the comparison pattern signal by one bit phase. Therefore, the bit phase between the comparison pattern signal and the input data signal is 1
It changes by the bit phase. If synchronization is not established in this state, the phase is further changed one pit at a time. n-
Although the phase is shifted by 1 or n bits, if the synchronization is not yet established, the clock is inhibited and the same operation is repeated.

As described above, while the clock inhibit circuit changes the bit phase between the comparison pattern signal and the input data signal by n bit phases at a time, the phase selecting circuit changes the bit phase by n bit phases at a time. The phase is changed every bit phase. Therefore, bit synchronization is always established between the comparison pattern signal and the input data signal.

Therefore, by disposing the clock inhibiting circuit at the subsequent stage of the serial / parallel conversion circuit, the clock inhibiting circuit can be driven at a low speed, and this clock inhibiting circuit can be easily incorporated into a low-speed ASIC.

In another invention, a phase selection circuit is inserted in a signal path of an input data signal. Therefore, when the bit phase between the comparison pattern signal and the input data signal does not match, first, the clock inhibition circuit is activated, and the bit phase between the comparison pattern signal and the input data signal becomes n bit phase. Minute change. If the bit phase has not yet been synchronized at the time of the change by n bits, a selection signal is sent from the synchronous semi-localization control circuit to the phase selection circuit. The phase selection circuit changes the output bit phase of the input data signal by one bit phase.

Therefore, the bit phase between the comparison pattern signal and the input data signal changes by one bit phase as in the above invention. If synchronization is not established in this state, the phase is further changed one pit at a time. Although the phase is shifted by n-1 or n bits, if the synchronization is not yet established, the clock is inhibited and the same operation is repeated. Therefore, also in the present invention, bit synchronization is always established between the comparison pattern signal and the input data signal.

[0029]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of the pattern synchronization circuit of the embodiment. The same parts as those of the conventional pattern synchronization circuit 4 shown in FIG. Therefore,
The detailed description of the overlapping part is omitted.

The clock signal c input from the clock recovery circuit 5 shown in FIG. 8 is divided by the frequency divider 10a in the serial / parallel conversion circuit 10 to 1 / n. Divided clock signal c ₃ output from the serial-parallel conversion circuit 10 is inputted to the clock disabled (inhibit) circuit 9a. The clock inhibition circuit 9a receives the clock inhibition signal h from the synchronization determination control circuit 11a.
When ₁ is input, as shown in FIG. 4, to prohibit the passage of one of the clock signal c ₃ input clock.

The clock signal c ₄ output from the clock inhibition circuit 9 and having a portion where no clock exists exists is input to the comparison pattern generation circuit 7. Comparative pattern generating circuit 7 generates a comparison pattern signal having a predetermined bit pattern of the same specified bit cycle N ₀ and the input data signal b input from the test object 2 in FIG. 8, a comparison of the parallel n string pattern signal g ₁ To the next phase selection circuit 12.

On the other hand, the input data signal b input from the test object 2 in FIG. 8 is converted into n columns of input data signals b ₁ by the S / P converter 10 b in the serial / parallel conversion circuit 10. The input data signal b ₁ of n parallel columns output from the serial / parallel conversion circuit 10 is input to the next error detection circuit 6.

FIG. 5 shows that n = 4 and the prescribed bit period is 8
(N ₀ = 8) and the pattern for each column of (1) (2) (3) (4) of the four columns of input data signal b ₁ when the bit pattern of input data signal b is [abcdefgh] The columns are shown schematically. As shown in FIG.
The bit data of the cycle is output. The input data signal b _! Is [A] [B] [C] [D]
There are four types of output bit phases. Whether the input theta signal b ₁ is output at which output bit phase of the four output bit phase can not be artificially fixed, depending on the start timing and the like.

The phase selection circuit 12, in order to respond to the input data signal _{b 1 [A] [B]} [C] [D], every time the selection signal j from the synchronization judgment control circuit 11a is input,
The output bit phase of the comparison pattern signal g ₁ of the n sequence output from the comparison pattern generating circuit 7 will sequentially changing one bit phase. The comparison pattern signal g ₂ of n columns after the bit phase change output from the phase selection circuit 12 is input to the error detection circuit 6.

As shown in the upper part of FIG. 6, the serial-to-parallel conversion circuit 10 in the case where n = 4, the prescribed bit period is 8 (N ₀ = 8), and the bit pattern is [abcdefgh] Of the output input data signal b ₁
The pattern of each column of (1), (2), (3) and (4) is schematically shown. Figure lower in comparison pattern signal g ₂ output from the phase selection circuit 12 in 6 (1) (2) (3) (4) schematically showing a pattern for each column.

[0036] When the error detection circuit 6 does not match by comparing the input data signal b ₁ of the comparison pattern signal g ₂ and n columns of n sequence, and outputs an error signal e to the synchronization judgment control circuit 11a. For example, as shown in FIG. 6, when the bit arrangements of the columns (1), (2), (3), and (4) do not match, an error signal e is output.

[0037] When the synchronization judgment control circuit 11a clock inhibit signal h ₁ from the inputs to the clock inhibit circuit 9a, since one clock of the divided clock c ₄ input to comparator pattern generating circuit 7 is eliminated, on the left side of FIG. 6 as shown, the comparative pattern generating circuit 7 (1) (2) (3) (4) comparison pattern signal g ₁ output to each column of delay divided by 1 clock the input data signal b _1. When converted to bit phase, 4
Delay by bit phase. When the selection signal j is sent from the synchronization determination control circuit 11a to the phase selection circuit 12, as shown in the lower part of FIG. 6, the signals are delayed by one bit phase as in the switching terminals (2) and (3) (described later). .

FIG. 2 is a specific circuit configuration diagram of the phase selection circuit 12. For simplicity, the comparison pattern signal g ₁ of n columns output from the comparison pattern generation circuit 7 is
It is assumed that there are four (parallel ratio n = 4) columns of parallel signals.

The first input terminal 13 ₁ is connected to the first switching terminal of the first selection switch S ₁ , and the 2.3.4th of each of the selection switches S ₂ , S ₃ , S ₄ . Connected to the switching terminal.

The second input terminal 13 ₂ is connected to the second first switching terminal of the selection switch S _2, and connected to each of the 2.3-th switching terminal of the selection switch S _3, S ₄ Have been. Further, the second input terminal 13 ₂
Is connected to the fourth switching terminal of the _first selection switch S1 via a delay circuit D for delaying one bit.

[0041] Similarly, a third input terminal 13 ₃ is connected to the third of the first switching terminal of the selection switch S _3,
And is connected to the second switching terminal of the selection switch S _4. Furthermore, a third input terminal 13 ₃ Each selection switch S ₁ via the delay circuit D delaying one bit, S
₂ are connected to the third and fourth switching terminals, respectively.

Similarly, the fourth input terminal 13 ₄ is connected to the first switching terminal of the fourth selection switch S ₄ ,
Further, they are connected to the second, third, and fourth switching terminals of each of the selection switches S ₁ , S ₂ , and S ₃ via a delay circuit D that delays by one bit.

The common terminals of the selection switches S ₁ , S ₂ , S ₃ , S ₄ are output terminals 14 ₁ , 14 ₂ , 14, respectively.
_3, is connected to 14 _4. Each selection switch S
₁ , S ₂ , S ₃ , and S ₄ are interlocked, and each time the selection signal j is input from the synchronization determination control circuit 11a, the first to fourth signals are output.
The switching terminals up to the number are sequentially switched and selected.

In the phase selection circuit 12 having such a configuration, when each of the selection switches S _{1 to} S ₄ is connected to the first switching terminal, ₄ is applied to each of the input terminals 13 _{1 to} 13 ₄ . comparison pattern signal g ₁ of the column, as it is output to the output terminals 14 ₁ to 14 _4. In this case, the output comparison pattern signal g ₂ and the input comparison pattern signal g
_There is no bit phase difference with ₁ .

Next, if the selection switch S ₁ to S ₄ were connected to the second switching terminal, the first output terminal 14 fourth input terminal 1 of 1 divided clock cycles before the ₁
3 _4-bit data is output. Further, the second output terminal 14 ₂ is the first input terminal 13 ₁ of the bit data of the current time is output. Furthermore, the third output terminal 1
The 4 ₃ second input terminal 13 _2-bit data of the present time is output. Then, the fourth output terminal 14 ₄ third input terminal 13 _3-bit data of the current time is output.

In this case, the output comparison pattern signal g
₂ and the input comparison pattern signal g ₁ for one bit (1
Phase difference). Further, each selection switch S ₁
If to S ₄ were connected to the third switching terminal, 1
Th to the output terminal 14 ₁ third input terminal 13 _3-bit data of 1-divided clock cycle before is output. Further, the second output terminal 14 ₂ 4 th input terminal 13 _4-bit data of 1-divided clock cycle before is output. Furthermore, the third output terminal 14 ₃ 1 th input terminals 13 _1-bit data of the present time is output.
Then, the fourth output terminal 14 ₄ second input terminals 13 _2-bit data of the present time is output.

In this case, the output comparison pattern signal g
₂ and the input comparison pattern signal g ₁ for two bits (2
Phase difference). Similarly, each selection switch S ₁
If to S ₄ were connected to the fourth switching terminal produces a phase difference of 3 bits (3 columns) or between the comparison pattern signal g ₂ which are output and input comparison pattern signal g _1.

In the lower part of FIG. 6, n = 4, the prescribed bit period is 8 (N ₀ = 8), and the bit pattern is [abc
defgh] and each of the selection switches S _{1 to} S ₄ is connected to the first switching terminal,
Each column (1) (2) when connected to the second switching terminal and when connected to the third switching terminal
(3) The arrangement of each hit data of (4) is shown. As shown in the figure, it can be understood that the bit phase in the bit pattern [abcdefgh] changes by one bit by sequentially switching the switching terminals of the respective selection switches S _{1 to} S ₄ with the selection signal j.

The synchronization determination control circuit 11a is composed of a kind of microcomputer, and when the circuit is started, executes a synchronization establishment detecting process in accordance with the flowchart shown in FIG. The flowchart is started and P (program step) 1
At, it is determined that the non-established state synchronization when an error signal e from the error detection circuit 6 showed more than a certain percentage, and sends the clock inhibit signal h ₁ to the clock inhibit circuit 9a (P
2). Subsequently, the number of outputs k of the selection signal j is initialized to 1 (P3). In this state, when a predetermined number of error signals e are input from the error detection circuit 6 (P4), if the number of outputs k after addition does not exceed the number of columns n (the number of switching terminals of the phase selection circuit 12), (P5), the selection signal j is sent to the phase selection circuit 12 (P6). Then, after 1 is added to the number of outputs k of the selection signal j (P7). Returning to P4, again the error signal e
Check for the presence of

[0050] When the output number k after addition at P7 exceeds the number of columns n, returns to P2, again transmits a clock disable signal h ₁ to the clock inhibit circuit 9a. Usually, the determination as to whether synchronization is established or not is made in parallel with the flowchart of FIG. 3, but the description of this portion is omitted in the flowchart of FIG.

The operation of the thus-configured pattern synchronization circuit will be described with reference to a time chart shown in FIG. In this time chart, the input data signal b and the comparison pattern signal g ₁ are shown for simplicity.
Assume that the prescribed bit period N ₀ is 4, and the bit pattern is a repeating pattern of [abcd]. Further, the frequency division ratio n of the frequency divider 10a of the parallel / serial conversion circuit 10
Is 2, and it is assumed that the parallel signals g ₁ and b ₁ are output in two columns.

First, since the bit phases of the input data b ₁ in two parallel rows do not match the bit phases of the comparison pattern signal g _{1 in} two parallel rows, they are asynchronous and the clock is prohibited by the synchronization determination control circuit 11 a. signal h ₁ is sent. As a result, the dividing one clock in the clock signal c ₄ is disappeared, input comparison pattern signal g ₁ data signal b ₁
Is delayed by one column (two-bit phase), and the bit phase difference between the two signals g ₁ and b ₁ changes.

However, since there is still a mismatch, a selection signal j is sent to the phase selection circuit 12 this time. Then, the bit phase is changed by 1 bit phase component with respect to the original comparison pattern signal g ₁ comparison pattern signal g ₂ output from the phase selecting circuit 12 is outputted from the comparison pattern generating circuit 7. A comparison pattern signal g ₂ after the change and the input data signal b ₁ are compared.

[0054] However, still, because it is a mismatch, is output clock inhibit signal h ₁ again. Then, since there is a further mismatch, the selection signal j is output. Then, a comparison pattern signal g ₂ after the selection signal j output and input data signal b ₁ is matched, bit phase between two signals g _2, b ₁ are synchronized.

As described above, the bit phase between the comparison pattern signal g ₁ and the input data signal b ₁ is changed by n bits at a time by the clock inhibition circuit 9 a, and the n bits are changed by the phase selection circuit 12 at a time. 1 of the changed part
The phase is changed for each bit phase. Accordingly, synchronization is established between the invariably comparison pattern signal g ₂ and the input data signal b _1.

Therefore, by disposing the clock prohibition circuit 9a at the subsequent stage of the serial / parallel conversion circuit 10, the clock prohibition circuit 9a can be driven at a low speed, and the clock prohibition circuit 9a can be driven by the comparison pattern generation circuit 7, the phase selection circuit 1
2. It can be easily incorporated into a low-speed ASIC together with the error detection circuit 6 and the synchronization determination control circuit 11a.

FIG. 7 is a block diagram showing a schematic configuration of a pattern synchronization circuit according to another embodiment of the present invention. The same parts as those in the circuit of the previous embodiment shown in FIG. Therefore, the detailed description of the overlapping part is omitted.

[0058] In the circuit of this embodiment, the phase selecting circuit 12a is interposed in the signal path of the input data signal b ₁ n columns from the serial-parallel conversion circuit 10 to the error detection circuit 6.
This phase selection circuit 12a has the same configuration as the phase selection circuit 12 shown in FIG.

[0059] Then, the phase selecting circuit 12a, the selection signal j from the synchronization judgment control circuit 11a is input, changes the input data signal b _1-bit phase n columns in 1-bit phase units. The input data signal b ₂ of the n-th column after the bit phase is changed is input to the error detector 6. The error detector 6 detects whether or not the bit phase of the comparison pattern signal g ₁ output from the comparison pattern generation circuit 7 matches the bit phase of the input data signal b _2, and outputs an error signal e if they do not match. .

[0060] Also in the pattern synchronizing circuit having such a configuration, the bit phase difference between the comparison pattern signal g ₁ and the input data signal b _2, n by the clock inhibit circuit 9a
The bit phase can be changed at a time and the phase selection circuit 1
With 2a, it can be changed for each bit phase. Therefore,
Since it is always possible to synchronize the bit phases between the two signals g ₁ and b ₂ , it is possible to achieve substantially the same effect as the circuit of the embodiment of FIG.

[0061]

As described above, in the pattern synchronization circuit of the present invention, the phase selection circuit for changing the bit phase of the comparison pattern signal or the input data signal input to the error detection circuit by one bit is provided. . Therefore, even if the clock prohibition circuit is inserted after the serial / parallel conversion circuit, the bit synchronization between the input data signal and the comparison pattern signal can be reliably established, and the clock prohibition circuit is incorporated in an ASIC that operates at a low speed. It is possible to reduce the size, weight, and cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a pattern synchronization circuit according to an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of a phase selection circuit of the circuit of the embodiment.

FIG. 3 is a flowchart showing the operation of a synchronization determination control circuit in the circuit of the embodiment.

FIG. 4 is a time chart showing the operation of the circuit of the embodiment.

FIG. 5 is a diagram showing a bit pattern of a comparison pattern signal output from a comparison pattern generation circuit in the circuit of the embodiment.

FIG. 6 is a diagram showing a bit phase relationship between an input data signal and a comparison pattern signal in the circuit of the embodiment.

FIG. 7 is a block diagram showing a schematic configuration of a pattern synchronization circuit according to another embodiment of the present invention.

FIG. 8 is a diagram showing a general error test apparatus.

FIG. 9 is a block diagram showing a schematic configuration of a conventional pattern synchronization circuit.

FIG. 10 is a time chart showing the operation of the conventional circuit.

FIG. 11 is a diagram illustrating a problem of a conventional circuit.

FIG. 12 is a diagram for explaining a problem of the conventional circuit.

[Explanation of symbols]

Reference numeral 2: Test object, 5: Clock recovery circuit, 6: Error detection circuit, 7: Comparison pattern generation circuit, 9a: Clock inhibition circuit, 10: Serial / parallel conversion circuit, 11a: Synchronization determination control circuit, 12, 12a: Phase selection circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 7/08 H04L 1/00

Claims (2)

(57) [Claims] An input clock signal is set to 1 / n (n; 2 or more)
And a serial-parallel conversion circuit (10) that outputs a frequency-divided clock signal after dividing the frequency of the input data into a divided clock signal, and converts a serial input data signal having a known period into an input data signal of n columns and outputs the data. A comparison pattern generation circuit (7) that outputs n columns of comparison pattern signals having the known period in synchronization with the frequency-divided clock signal; and an interposition between the serial / parallel conversion circuit and the comparison pattern generation circuit. A clock prohibition circuit (9a) for prohibiting the passage of one or more continuous clocks in the divided clock signal in response to a clock prohibition signal input; and generating the comparison pattern each time a selection signal is input. A phase selection circuit (12) for sequentially changing the output bit phases of the n-column comparison pattern signals output from the circuit; and n having the bit phase selected by the phase selection circuit.
An error detection circuit (6) that outputs an error signal when the comparison pattern signal of the column and the input data signal of n columns output from the serial-parallel conversion circuit do not match; When a signal is output, it is determined that synchronization has not been established, and a predetermined number of error signals are output from the error detection circuit until it is determined that the output ratio of the error signal is less than the predetermined ratio and synchronization has been established. A synchronization determination control circuit (11a) for outputting a selection signal to the phase selection circuit each time the number of times the selection signal is transmitted exceeds a predetermined number and outputting a clock inhibition signal to the clock inhibition circuit. Pattern synchronization circuit. 2. An input clock signal is set to 1 / n (n; 2 or more).
And a serial-parallel conversion circuit (10) that outputs a frequency-divided clock signal after dividing the frequency of the input data into a divided clock signal, and converts a serial input data signal having a known period into an input data signal of n columns and outputs the data. A comparison pattern generation circuit (7) that outputs n columns of comparison pattern signals having the known period in synchronization with the frequency-divided clock signal; and an interposition between the serial / parallel conversion circuit and the comparison pattern generation circuit. A clock prohibition circuit (9a) for prohibiting the passage of one or more continuous clocks in the divided clock signal in response to the input of the clock prohibition signal; and A phase selection circuit (12a) for sequentially changing output bit phases of input data signals of n columns output from the circuit; and n having a bit phase selected by the phase selection circuit.
An error detection circuit (6) that outputs an error signal when the input data signal of the column does not match the comparison pattern signal of the n-th column output from the comparison pattern generation circuit; When a signal is output, it is determined that synchronization has not been established, and a predetermined number of error signals are output from the error detection circuit until it is determined that the output ratio of the error signal is less than the predetermined ratio and synchronization has been established. A synchronization determination control circuit (11a) for outputting a selection signal to the phase selection circuit each time the number of times the selection signal is transmitted exceeds a predetermined number and outputting a clock inhibition signal to the clock inhibition circuit. Pattern synchronization circuit.