JPH07235920A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To extremely improve the probability of return from a pseudo synchronization by masking a secondary synchronization circuit against the synchronizing pulse set at a position where a main synchronization circuit is synchronized. CONSTITUTION:The received data and a received clock are inputted to a frame storing register 3, a synchronization pattern retrieving signal is inputted to the 1st and 2nd synchronization pattern decoders 5 and 6 from the register 3 with a delay secured by one bit. The output of the decoder 5 is delayed by a delay circuit 7 by a degree equal to a single received clock and activates both signals A and B at a time. When the decoder 5 detects a synchronization pattern based on the selection signal sent from a main synchronization selecting circuit 8, and the synchronizing conditions are satisfied by a 1st synchronization detecting circuit 10 of a main synchronization circuit and a frame pulse is outputted, this frame pulse is selected by a selector 4 and outputted. Meanwhile a secondary synchronization circuit (2nd synchronization detecting circuit 11) masks the circuit 11 (secondary circuit) by a masking logic circuit 9 after the synchronization of the main synchronization circuit is fixed. Therefore the frame pulse positions different from that of the main synchronization circuit are always retrieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is designed to detect the positions of frame bits inserted in a concentrated or discrete manner.
A frame synchronization circuit having two synchronization detection circuits, one of which is a main synchronization circuit, the other of which is a sub synchronization circuit, and the main synchronization circuit and the sub synchronization circuit are switched and used when the main synchronization circuit is pseudo synchronized, The present invention relates to a frame synchronization circuit capable of significantly improving the probability of recovery from pseudo synchronization.

[0002]

2. Description of the Related Art Generally, there is known a frame synchronization circuit that detects the positions of frame bits that are inserted in a concentrated or discrete manner and thereby establishes frame synchronization.
In this conventional frame synchronization circuit, in the synchronization pull-in process, it is possible to establish pseudo synchronization because it is determined that synchronization has been established by several consecutive matches of detection of several bits. Therefore, after synchronization is established, status monitoring is performed using some kind of error detection method (for example, CRC, parity), false synchronization is determined by the error, and a sub-synchronization circuit that re-detects the synchronization pattern while maintaining the synchronization state. There is a need.

However, a conventional frame synchronizing circuit of this type has two identical first and second synchronization detecting circuits 1 and 2 as shown in FIG. 2 and has the above first and second synchronizing circuits. The detection circuits 1 and 2 input the synchronization pattern search signal from the frame storage shift register 3 to which the received data and the received clock are input, and output the first frame start position signal and the second frame start position signal, respectively. . When the selector 4 selects the first frame start position signal and processes data based on the selected signal, the second sync detection circuit 2 is used for detecting sub sync, and the first sync signal is used. When the synchronization detection circuit 1 of FIG. 1 shifts to a state of performing processing based on the information of the second synchronization detection circuit 2 in pseudo synchronization, the first synchronization detection circuit 1 is used for the sub-synchronization circuit. It That is, the main synchronizing circuit and the sub synchronizing circuit are alternately switched.

In such a frame synchronization circuit, there is a problem that the first and second synchronization detection circuits 1 and 2 operate independently and there is a possibility that they may fall into the same pseudo synchronization pattern. If the same pseudo-synchronization is applied, it is difficult to restore the circuit configuration or normal synchronization cannot be obtained. In particular, in the conventional frame synchronization circuit shown in FIG. 2, when the first and second synchronization detection circuits 1 and 2 simultaneously start searching for a synchronization pattern at the start of operation, synchronization pull-in is likely to occur at the same position. .

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a frame synchronization circuit capable of significantly improving the probability of recovery from pseudo synchronization.

[0006]

SUMMARY OF THE INVENTION To achieve the above object, the present invention has two sync detecting circuits for detecting the position of a frame bit transmitted, one of which is a main synchronizing circuit and the other of which is a sub synchronizing circuit. In a frame synchronization circuit that switches and uses the main synchronization circuit and the sub synchronization circuit when the main synchronization circuit is pseudo-synchronized, the sub synchronization circuit is masked with respect to a synchronization pulse at a position where the main synchronization circuit is synchronized. A mask means is provided. That is, the mask means prevents the sub-synchronization circuit from synchronizing at the synchronization position detected by the main synchronization circuit.

[0007]

The present invention will be described below based on the illustrated embodiments. FIG. 1 is a block diagram showing an embodiment of a frame synchronization circuit according to the present invention. In FIG. 1, this frame synchronization circuit is an n-bit simultaneous collation system (multipoint monitoring) frame synchronization circuit using a 1-bit immediate shift system, and a 5-bit frame storage shift for inputting received data and a received clock. Register 3, first and second sync pattern decoders 5 and 6 connected to the output side of the frame storage shift register 3, and clock delay circuit connected to the output side of the first sync pattern decoder 5. 7
A main synchronization selection circuit 8 for outputting a main synchronization circuit selection signal, and a masking logic circuit 9 connected to the output side of the clock delay circuit 7, the second pattern decoder 6 and the main synchronization selection circuit 8. , First and second synchronization detection circuits 10 connected to the output side of the masking logic circuit 9,
11 and the first and second synchronization detection circuits 10 and 11
And a selector 4 connected to the output side of.

In the frame synchronization circuit, the frame synchronization pattern is 4 bits, and the synchronization pattern is shifted by 1 bit from the 5-bit frame storage shift register 3 to the first and second synchronization pattern decoders 5 and 6. A search signal is sent. The masking logic circuit 9 has a main synchronization circuit selection signal from the main synchronization selection circuit 8 and first and second frames from the first and second synchronization detection circuits 10 and 11, as will be described later. The sub synchronizing circuit is masked with respect to the synchronizing pulse at the position where the main synchronizing circuit synchronizes based on the pulse.

Next, the operation of the frame synchronization circuit having the above configuration will be described. First, when the received data and the received clock are input to the frame storage shift register 3, the synchronization pattern search signal is shifted by 1 bit from the frame storage shift register 3 and the first and second synchronization pattern decoders 5, Sent to 6. That is, the shift register 3 for frame storage is QA → QB → QC →
If the synchronization pattern comes when the shift is made, the second synchronization pattern decoder 6 always detects the synchronization pattern one reception clock after the first synchronization pattern decoder 5 detects the synchronization pattern. It has become.

Next, the output of the first pattern decoder 5 is delayed by one receive clock by the clock delay circuit 7, so that the signals A and B in FIG. 1 are simultaneously activated.

Here, based on the main synchronization circuit selection signal from the main synchronization selection circuit 8, the first synchronization detection circuit 10 is
When the side is the main synchronizing circuit, the first synchronizing pattern decoder 5 detects the synchronizing pattern, the synchronizing condition is satisfied in the first synchronizing detecting circuit 10, and the first frame pulse is output. The first frame pulse is selected by the selector 4 and is output as a frame position pulse to a reception data phase adjusting unit (ES) (not shown) or the like. On the other hand, the sub synchronization circuit (second synchronization detection circuit 1
On the 1) side, the main synchronization circuit (first synchronization detection circuit 1
In order to prevent synchronization at the synchronization position detected in 0), after the synchronization of the main synchronization circuit has been established, the synchronization pulse at the position where the main synchronization circuit is synchronized by the masking logic circuit 9 is Second synchronization detection circuit (sub-synchronization circuit) 11
It is masked so that it doesn't reach. Therefore, the sub synchronizing circuit always searches for a frame pulse position different from that of the main synchronizing circuit.

The switching between the main synchronization circuit and the sub-synchronization circuit is performed by the main synchronization selection circuit 8 at the time when the main synchronization circuit or the pseudo synchronization is determined as in the conventional case.
Further, when the second synchronization detection circuit 11 becomes the main synchronization circuit due to the switching, the synchronization pulse at the position where the main synchronization circuit is synchronized by the masking logic circuit 9 is now the first synchronization pulse. Synchronization detection circuit (sub-synchronization circuit) 1
Masked so that it does not reach 0.

[0013]

As described above, according to the present invention, since the main synchronizing circuit and the sub synchronizing circuit are entangled with each other, the sub synchronizing circuit never establishes synchronization with the same synchronization pattern as the main synchronizing circuit, and the pseudo synchronization is achieved. The probability of returning from can be significantly improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a frame synchronization circuit according to the present invention.

FIG. 2 is a configuration diagram of a conventional frame synchronization circuit.

[Explanation of symbols]

1, 10 ... First synchronization detection circuit, 2, 11 ...
Second synchronization detection circuit, 3 ... Frame storage shift register, 4 ... Selector, 5 ... First synchronization pattern decoder, 6 ... Second synchronization pattern decoder, 7 ...
Clock delay circuit, 8 ... Main synchronization selection circuit, 9 ... Masking logic circuit,

Claims (2)

[Claims] 1. A synchronous detection circuit for detecting the position of a frame bit transmitted, wherein one has a main synchronous circuit and the other has a sub synchronous circuit. When the main synchronous circuit is pseudo-synchronized, A frame synchronizing circuit for switching between a main synchronizing circuit and a sub synchronizing circuit, wherein the frame synchronizing circuit comprises masking means for masking the sub synchronizing circuit with respect to a synchronizing pulse at a position where the main synchronizing circuit is synchronized. Frame synchronization circuit. 2. The frame synchronizing circuit according to claim 1, wherein the masking means prevents the sub synchronizing circuit from synchronizing at a synchronizing position detected by the main synchronizing circuit.