JP3641411B2 - Frame synchronization circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a frame synchronization method in digital data transmission multiplexed by a time division multiplexing method.
[0002]
[Prior art]
In order to transmit data between transmission and reception in digital wireless transmission, it is essential to establish frame synchronization. In particular, in order to establish frame synchronization by transmitting data using a wireless transmission path, it is necessary to take measures against bit loss that occurs in the transmission path, and to take measures against out-of-synchronization protection and to prevent false pull-in that is mistakenly mistaken for synchronization. It is.
[0003]
For example, as disclosed in Japanese Patent Application Laid-Open No. 5-14336, it has been proposed that it is possible to prevent frame synchronization pseudo pull-in by weakening the synchronization characteristics for a certain time after synchronization pull-in. This will be explained by using the result of the synchronization determination circuit as a trigger to make a transition from the asynchronous state to the synchronous state as a trigger, and to detect that it is not a pseudo pull-in state by weakening the anti-synchronization protection characteristic for a certain period of time. It is a configuration.
[0004]
Next, an outline will be described based on the block diagram shown in FIG. A frame synchronization determination circuit including a bit comparison circuit, a synchronization pull-in protection circuit, an out-of-synchronization protection circuit, a synchronization determination circuit, and the like is provided with a timer circuit, and for a certain period of time after frame synchronization is pulled in by a control signal output from the timer circuit, The setting value of the mismatch number setting circuit for setting the number of mismatches in the out-of-synchronization protection circuit is made small to suppress the occurrence of pseudo pull-in.
[0005]
[Problems to be solved by the invention]
In the conventional frame synchronization circuit described above, the characteristics of the out-of-synchronization protection circuit are weakened for a certain period after the synchronization pull-in state in order to prevent the occurrence of pseudo pull-in.
[0006]
For this reason, in the case where a bit error occurs in the input data, the protection characteristic is weakened. Therefore, the probability that the synchronization error is caused by the bit error occurring on the transmission path is increased.
[0007]
This is considered that the frame synchronization circuit does not operate correctly depending on the state of the transmission line because it is not possible to distinguish between a bit error occurring on the transmission line and a frame bit error pulse due to pseudo pull-in.
[0008]
Accordingly, a main object of the present invention is to provide a frame synchronization circuit which is not affected by a bit error state occurring on a transmission line, avoids a pseudo pull-in phenomenon and does not impair backward protection characteristics.
[0009]
[Means for Solving the Problems]
According to the present invention, in a frame synchronization circuit for input data having a frame structure of a time division multiplexing synchronization method and having a frame synchronization pattern composed of n bits (n is an integer of 1 or more) in one frame, Frame synchronization bit generation circuit to be generated, and first to nth frame bit determinations that are provided corresponding to each of the n bits and that compare the input data with the generated frame synchronization bit and output a match / mismatch signal A first to n-th continuity determining circuit for determining the continuity of a mismatch signal output corresponding to each of the n bits and output from the frame bit determining circuit; The frame synchronization state is determined based on the coincidence / non-coincidence signal output from the frame bit determination circuit and the outputs of the first to nth continuity determination circuits. Further comprising a synchronization judgment circuit can be obtained frame synchronization circuit according to claim.
[0010]
Further, in any of the first to n-th continuity determination circuits, if any of the synchronization determination circuits determines N (N is greater than or equal to 2) continuity mismatches, the synchronization determination circuit determines that it is in a synchronized state. You may make it determine with a state.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
In order to clarify the above and other objects, features, and advantages of the present invention, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram of an embodiment of the present invention.
[0012]
The frame synchronization circuit according to the present invention compares each frame synchronization bit generated by the frame synchronization bit generation circuit 103 with n frames (n is assigned in one frame) in order to detect the frame synchronization bit multiplexed in the received data. Frame bit determination circuits 100-1 to 100-n and the determination result signals 100-1 to 100-n output from the respective frame bit determination circuits n The continuity determination circuits 101-1 to 101-n, the OR circuit 102 that takes the logical sum of the continuity detection results that are the results of the n continuity determination circuits, and the output of the OR circuit 102 are controlled. A synchronization judgment circuit 107, a logical sum circuit 104 for taking the logical sum by inputting the judgment results of the n frame bit judgment circuits 100-1 to 100-n, respectively, and a result of the logical sum circuit for the forward protection circuit 105 and the rear Based on the input to the protection circuit 106 Constituted by the synchronization determination circuit 107 to determine the frame synchronization state.
[0013]
Hereinafter, the operation of the present embodiment will be described with reference to the time chart of FIG. In the description, a process for establishing synchronization with received data in which 3 frame synchronization bits are assigned to one frame will be described. In addition, a signal very similar to the frame synchronization bit pattern is input to the received data in FIG. 2, and f1, *, and f3 are frame synchronized two bits before the original frame synchronization bit patterns F1, F2, and F3. It is assumed that it is inserted at the same cycle as the cycle. f1 is the same signal as F1, f3 is the same signal as F3, and * is a signal having a periodicity different from that of F2.
[0014]
The received data is input to the first frame bit determination circuit 100-1, the second frame bit determination circuit 100-2, and the third frame bit determination circuit 100-3. First, F1 is searched for searching for synchronization bits and establishing synchronization. In the first frame bit determination circuit 100-1 for searching for bits, the data is compared with the frame synchronization bit Sf1 generated by the frame synchronization bit generation circuit 103. The comparison result is output to the continuity determination circuit 101-1 and the OR circuit 104 as the output Sp10 of the first frame bit determination circuit. Similarly, for the F2 and F3 bit searches, the second frame bit determination circuit 100-2 and the third frame bit determination circuit 100-3 are input in the same manner as described above.
[0015]
In this case, the outputs of the first and third frame bit determination circuits are output as coincidence as shown in FIG. 2, and the output of the second frame bit determination circuit is output as disagreement. The output of the second frame bit determination circuit is input to the continuity determination circuit 101-2. The continuity determination circuits 101-1 to 101-3 are circuits for determining the continuity of the output signal of the frame bit determination circuit that is input. In FIG. 2, continuity is shown as two continuous detections. That is, the continuity determination circuit 101-2 outputs a determination result signal to the OR circuit when an error continues (disagrees) twice at the position of the F2 bit as shown at time t2 in FIG.
[0016]
Next, the rear protection circuit 106 will be described. The rear protection circuit 106 is a circuit provided for establishing frame synchronization. First, the position of F1 is detected, the positions of F2 and F3 are detected with reference to that position, and as described above, the logical sum is output by the logical sum circuit 104 of the output of the first, second and third F bit determination circuits, and the backward protection is performed. Input to the circuit 106. The backward protection circuit 106 determines that the frame is in a synchronized state (frame synchronized state) if two or more bits out of 3 bits (F1, F2, F3) constituting the frame are correct. The determination result is input to the synchronization determination circuit 107. In the case of FIG. 2, the output signal of the rear protection circuit 106 transitions from the asynchronous state to the synchronous state at time t1.
[0017]
The output of the OR circuit 102 is also input to the synchronization determination circuit 107, collated with the result of the rear and rear protection circuit 106, and output as a frame synchronization state signal. In the example shown in the time chart of FIG. 2, the determination result of the rear protection circuit 106 is in a synchronized state. The result of the continuity determination circuit 101-2 is determined to be asynchronous because a continuity error has occurred. As a result, the frame synchronization state signal 109 of the synchronization determination circuit 107 transitions from the synchronization state to the asynchronous state at time t2. In this way, pseudo pull-in can be avoided by the present invention.
[0018]
The frame synchronization state signal is input to the frame synchronization bit generation circuit 103, and the position of the F bit signal is changed and an F bit pattern is output so as to be compared with the received data again. Therefore, the bit F3 is compared at the correct position at time t3 in FIG. As a result, the continuity determination circuit 101-2 determines that there is no continuity error at time t4. At the same time, the frame synchronization state 109 transitions from the asynchronous state to the synchronous state.
[0019]
In addition, when the received data is wrong on the transmission line, there is very little continuity in the error that occurs (the probability of making a mistake of 2 bits or more is very small), so synchronization is established without the continuity judgment circuit operating incorrectly. Is possible.
[0020]
【The invention's effect】
As described above, according to the present invention, there is provided a frame synchronization circuit that does not detect erroneous synchronization using a pseudo frame synchronization signal other than a frame synchronization signal included in received data. Further, since the number of protection stages is not changed, a frame synchronization circuit that is not affected by bit errors included in the received data can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram of a frame synchronization circuit according to an embodiment of the present invention.
FIG. 2 is a timing chart in the case where 3 frame synchronization bits are assigned to one frame.
Fig. 3 Conventional example [Explanation of symbols]
100-1 1st F bit decision circuit 100-1 to 100-n nth frame bit decision circuit 101-1 continuity decision circuit 102 OR circuit 103 frame synchronization bit generation circuit

Claims (2)

In a frame synchronization circuit of input data having a frame structure of a time division multiplexing synchronization method and having a frame synchronization pattern composed of n bits (n is an integer of 1 or more) in one frame,
A frame synchronization bit generation circuit for generating a frame synchronization pattern;
First to nth frame bit determination circuits provided corresponding to each of the n bits and outputting a match / mismatch signal by comparing the input data and the generated frame synchronization bit;
First to n-th continuity determining circuits that are provided corresponding to each of the n bits and determine the continuity of the mismatch signal output from the frame bit determining circuit;
A synchronization determination circuit for determining a frame synchronization state based on a match / mismatch signal output from the first to n-th frame bit determination circuits and an output of the first to n-th continuity determination circuits; Frame synchronization circuit. In any of the first to n-th continuity determination circuits, if any one of N (N is 2 or more) continuity mismatches is detected, even if the synchronization determination circuit determines that it is in a synchronous state, this is regarded as an asynchronous state. 2. The frame synchronization circuit according to claim 1, wherein the determination is made.

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