JP3200535B2 - Block synchronization processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a block synchronization processing circuit, and more particularly, to serial data transfer using a clock signal and a data signal, a block identification code signal (BIC signal) for synchronization detection, and forward protection. The present invention relates to a block synchronization processing circuit that performs block synchronization determination using a circuit and a rear protection circuit.

[0002]

2. Description of the Related Art Conventionally, there has been known a communication system in which data is serially transferred using a clock signal and a data signal. As an example of such a communication system, for example, F
M multiplex broadcasting. In FM multiplex broadcasting, data is transmitted by being multiplexed with FM broadcasting (main broadcasting). In a receiver for FM multiplex broadcasting, data and a clock are reproduced from the multiplexed signal and processed. Data transmission is performed in packet units for each block. Each of the blocks is a predetermined block identification code (hereinafter referred to as “BIC”).
In M multiplex broadcasting, BICs having four types of patterns, BIC1 to BIC4, are used. ), The FM multiplex broadcast receiver detects a block break by extracting a BIC pattern from a received data string, and detects reception by detecting a plurality of times (forward protection times / backward protection times) of the BIC pattern. Determine block synchronization.

FIG. 6 is a timing chart showing a block synchronization process performed in a conventional FM multiplex broadcast receiver.

[0004] The block synchronization is based on the B generated in the receiver.
This is performed by measuring the number of times that the IC detection timing signal (corresponding to FIG. 6A) matches the detected BIC signal (corresponding to FIG. 6B). Two processes of forward protection and backward protection are performed to determine synchronization.

The backward protection is a process performed when synchronization is not established, and the BIC detection timing signal and the detected BIC signal are set a predetermined number of times (n
This is a process of determining that synchronization has been established when they match.

The forward protection is a process performed when synchronization is established, and is performed a predetermined number of times (m times).
This is a process for determining that synchronization has been lost because the BIC signal has never been detected during the IC detection timing signal.

In the example shown in FIG. 6, backward protection is performed between times t1 and t2, and at time t2 when the BIC detection timing signal (a) coincides with the detected BIC signal (b) n times. In, it has been determined that synchronization has been established. When synchronization is established, a block synchronization signal is output (FIG. 6).
(C)). In addition, forward protection is performed between times t3 and t4,
BI corresponding to m BIC detection timing signals (a)
Since the C signal (b) has never been detected, it is determined that synchronization is lost at time t4 (FIG. 6).
(C)).

The number n of BIC detection timing signals used in backward protection (hereinafter referred to as “backward protection times”) and the number m of BIC detection timing signals used in forward protection (hereinafter referred to as “forward protection times”) are each. Desired values were set at the time of design.

[0009]

However, the conventional FM multiplex broadcasting receiver has a problem that block synchronization is not properly performed. This is due to the following reasons.

If the block synchronization is determined with a relatively small number of backward protections at the time of circuit design, erroneous BIC detection is performed due to the same bit sequence and noise that occurred by chance in the data / parity sequence. Synchronization may occur.

On the other hand, if a relatively large number of back protections is set at the time of circuit design, BICs for the number of back protections set for block synchronization must be detected, so that the determination of block synchronization is delayed. . If the BIC signals for the set number of backward protections do not completely coincide with each other, block synchronization is not determined. Therefore, when there is a noise of a certain level or more, there is a possibility that correct block synchronization may be missed.

Further, there is a problem described below regarding the setting of the number of times of forward protection. Noise such as multipath / fading may be superimposed on the received signal during block synchronization, but the data pattern of the received BIC is garbled due to the data being garbled by the burst noise for a relatively short period (period during which the clock synchronization is not lost). May collapse several times in succession. If a relatively small number of forward protections is set during circuit design, a small number of BICs will not be detected,
Although the block synchronization is actually achieved, there may be a case where a wrong determination is made that the block synchronization is lost and the resynchronization detection process is started. In addition, there is a case where noise such as static electricity / power supply line noise enters the receiver.

On the other hand, if a relatively large number of forward protections are set in the circuit, the out-of-synchronization state occurs due to the relatively long burst noise (period in which the clock is out of synchronization) among the above-mentioned noises. In some cases, erroneous BIC detection may be performed due to the same bit sequence or noise as a BIC generated by chance in a data / parity sequence. In that case, the detection of the forward protection is initialized, and the detection of the BIC is continuously performed again by the number of times of the forward protection, so that the determination of the loss of the block synchronization is delayed.

FIG. 7 is a timing chart showing the process of forward protection when the number of forward protections is set to m.

Referring to FIG. 1, (a) shows a BIC detection timing signal generated in the receiver, and (b) shows a detected BIC signal.
(C) shows a block synchronization signal, and (d) shows a count value of a forward protection counter in the block synchronization determination circuit.

Referring to the figure, a first starting from time t1
During the second forward protection process, an incorrect BI
It is assumed that the C signal is detected. At this time, as shown in (d), the value of the forward protection counter is reset to m, whereby the second forward protection process is started from time t3. For this reason, a signal of synchronization establishment is output as a block synchronization signal until time t4 even though synchronization is lost after time t1. In the worst case, when the forward protection number is m, if the BIC erroneous detection occurs continuously within the interval of (m-1) times of the output of the BIC detection timing signal, the process cannot proceed to the resynchronization processing indefinitely. Will not be received.

The present invention has been made to solve the above problems, and has as its object to provide a block synchronization processing circuit capable of accurately performing block synchronization.

[0018]

According to a first aspect of the present invention, there is provided a block synchronization processing circuit for processing block synchronization of a received signal, the block identification processing circuit comprising:
No. of detection status storage times to sequentially store and store multiple detection statuses of signals
Path for detecting the block identification code
Based on the plurality of detection statuses stored in the detection status storage circuit.
The number of forward protections is set based on this.

The block synchronization processing circuit according to claim 2
When the detection status storage circuit detects the block identification code
To “1” when no block identification code is detected.
“0” is stored, and the stored value is stored.
Is added, and the forward protection time is calculated according to the value obtained by the addition.
It is characterized in that the number is set.

According to a third aspect of the present invention, in the block synchronization processing circuit, the state is changed from the out- of- synchronization state to the state in which block synchronization is established.
When a transition is made, the contents of the detection status storage circuit are reset.
It is characterized in that it is placed in a closed state.

According to a fourth aspect of the present invention, there is provided a block synchronization processing circuit for processing a block synchronization of a received signal.
The synchronization processing circuit detects a block identification code.
Addition operation is performed and the block identification code is not detected.
Equipped with a detection status counter that performs a subtraction operation when
The forward protection count is set based on the detection status counter value.
Perform settings .

According to a fifth aspect of the present invention, there is provided a block synchronization processing circuit for processing block synchronization of a received signal.
The synchronization processing circuit detects a block identification code.
Addition operation is performed and the block identification code is not detected.
Equipped with a forward protection counter that performs a subtraction operation when
Loss-of-synchronization status determination based on the value of the forward protection counter
The forward protection counter has an upper limit
It is characterized by the following.

[0023]

[Action] block synchronization processing circuit according to claim 1, blanking
The detection status of the lock identification code is sequentially stored, and plural
At the detection timing of the lock identification code,
Set the forward protection count based on multiple detection situations.
U.

According to a second aspect of the present invention, the block synchronization processing circuit outputs "1" when a block identification code is detected.
"0" when no lock identification code is detected.
The stored value is added and the added value is added.
The forward protection count is set according to the value obtained by the calculation.
U.

According to a third aspect of the present invention, the block synchronization processing circuit changes the state from the out- of- synchronization state to the state in which the block synchronization is established.
When a transition is made, the contents of the detection status storage circuit are reset.
State.

According to a fourth aspect of the present invention, the block synchronization processing circuit sets the forward protection count based on the value of the detection status counter.
Perform settings .

The block synchronization processing circuit according to the fifth aspect performs an addition operation when a block identification code is detected.
When the block identification code is not detected, the subtraction operation is performed.
Of the front protection counter
Loss-of-synchronization status is determined based on the
An upper limit is set for the counter.

[0028]

FIG. 1 is a block diagram showing a configuration of a block synchronization processing circuit according to a first embodiment of the present invention.

Referring to the figure, a block synchronization processing circuit includes a BIC detection circuit 3 for detecting a BIC signal from a received signal, and a backward protection number setting circuit 5 for setting the number of backward protection.
A forward protection count setting circuit 7a to 7n for setting N types of forward protection counts, a selection circuit 9 for selecting and outputting a desired forward protection count from the front protection count setting circuits 7a to 7n,
A block synchronization determination circuit 1 for determining block synchronization based on a BIC detection signal, a BIC detection timing generation circuit 11 for generating a BIC detection timing signal, and a BIC status determination circuit 100 for determining the status of a received BIC signal It is composed of The block synchronization processing circuit includes a reception signal input terminal 51 for inputting a signal to be received.
And a rear protection number input terminal 52 for inputting a signal for setting the rear protection number, and front protection number setting circuits 7a to 7a.
7n includes forward protection number input terminals 53a to 53n for setting the number of forward protection times for each of 7n, and a block synchronization signal output terminal 61 for outputting a block synchronization signal.

The BIC status determination circuit 100 comprises a BIC detection status storage circuit 101 comprising a FIFO (First in First out) for storing the presence or absence of BIC detection at one packet interval (BIC detection timing). Adder circuit 102 for adding all data in storage circuit 101
And a determination circuit 103 for determining the detection status of the BIC based on the output of the addition circuit 102, and threshold setting circuits 104a to 104m for storing thresholds for determining the BIC detection status. Also, threshold setting circuits 104a to 104m
Setting input terminal 56a for setting a threshold for each of
To 56 m.

The BIC detection status storage circuit 101 stores a BI of a sufficiently large number of blocks as compared with the largest forward protection number.
The detection status of C is stored.

A feature of the circuit in the present embodiment is that a plurality of types of forward protection which can be set conventionally only one type can be set, and a desired number of forward protections can be selected according to a reception state. That is. This function is realized by the forward protection number setting circuits 7a to 7n, the selection circuit 9, and the BIC status determination circuit 100.

FIG. 2 shows the BIC detection status storage circuit 10 of FIG.
FIG. 3 is a diagram showing a specific example of FIG. Referring to the figure, BIC detection status storage circuit 101 includes D flip-flops 200a to 200a-2.
00r, and a BIC detection timing signal of the BIC detection timing generation circuit 11 is input from the input terminal 72 as a clock.
A BIC detection signal of the detection circuit 3 is input from an input terminal 71. Further, a block synchronization signal from the block synchronization determination circuit 1 is input from an input terminal 73. The block synchronization signal is a low level signal when the block synchronization is not established, and becomes a high level signal when the synchronization is established. Therefore, in this circuit, the shift register is reset when the block synchronization is not achieved.

Next, the operation of the block synchronization processing circuit in this embodiment will be described with reference to FIGS.

The received signal input via the input terminal 51 is input to the BIC detection circuit 3. The BIC detection circuit 3 extracts a BIC signal from the reception signal, and extracts the extracted BIC signal.
The IC signal is input to the block synchronization determination circuit 1.

In the out-of-synchronization state, the BIC signal output from the BIC detection circuit 3 and the BIC detection timing signal generated by the BIC detection timing generation circuit 11 are compared by the block synchronization determination circuit 1, and the number of coincidences is rearward protected. When the number set by the number setting circuit 5 is reached, synchronization establishment is determined. When it is determined that synchronization has been established, the block synchronization determination circuit 1 outputs a block synchronization establishment signal (High) through the block synchronization signal output terminal 61.
Level signal) is output. At the same time, the block synchronization signal is input from the block synchronization determination circuit 1 to the BIC detection status storage circuit 101 in the BIC status determination circuit 100.

The block synchronization signal input to the BIC detection status storage circuit 101 is supplied to the D flip-flops 200a to 200r via the input terminal 73 as shown in FIG.
Are input to the respective reset terminals R. Therefore, when the block synchronization signal is not output, the values of the shift registers in the BIC detection status storage circuit 101 are all reset, and data storage is started with the block synchronization establishment signal output as an initial state. Flip-flops 200a to 200c included in the BIC detection circuit storage circuit 101
Each of the outputs 75a to 75r of 200r is
Is input to In the adder circuit 102, flip-flops 200a to 200 in the BIC detection status storage circuit 101
The outputs of each of r are added. The value added by the addition circuit 102 is input to the BIC detection status determination circuit 103. In the BIC detection status determination circuit 103, the addition circuit 10
2 and threshold setting circuits 104a to 104m
Is compared with the threshold value set in. The judgment output output from the BIC detection status judgment circuit 103 is the selection circuit 9
Is input to The selection circuit 9 selects a desired number of forward protections from the number of forward protections set in each of the forward protection number setting circuits 7a to 7n based on the input determination output,
The forward protection count is output to the block synchronization determination circuit 1.

Here, the threshold set in the threshold setting circuit 104a is y1, the threshold set in the threshold setting circuit 104b is y2, and the threshold set in the threshold setting circuit 104c is y3 (y1 <y2 <y3). The number of protections set in the forward protection number setting circuit 7a is x1, the number of protections set in the front protection number setting circuit 7b is x2, and the number of protections set in the front protection number setting circuit 7c is x.
3 (x1 <x2 <x3), the addition circuit 1
When the addition output data d from 02 is d <y1, x1 is selected as the forward protection count, when y1 ≦ d <y2, the value of x2 is selected as the forward protection count, and when y2 ≦ d, x3 is selected as the forward protection count. The signal is output to the block synchronization determination circuit 1 by the circuit 9.

When the block synchronization is established from the out-of-synchronization state, the value of the shift register in the BIC detection status storage circuit 101 in which all stages are set to “0” is added to the addition circuit 10.
2 is output. Therefore, when shifting from the out-of-synchronization state to the synchronization-established state, the set minimum value is used as the forward protection count. As a result, in the case of block erroneous synchronization, loss of synchronization is immediately determined.

In a state where synchronization is established, a BIC detection signal is supplied to a terminal 71 of the shift register in the BIC detection status storage circuit 101 shown in FIG.
Since the IC detection timing signal is input, the data of "1" is stored in the shift register when the BIC detection signal matches the BIC detection timing signal, and the shift register is used when the BIC detection signal does not match the BIC detection timing signal. Is input with data "0". As a result, the added output data d output from the adding circuit 102 becomes larger as the BIC detection status becomes better, and accordingly, a larger number of forward protections is selected.

FIG. 3 is a timing chart in the forward protection processing in this embodiment. Referring to FIG.
Assume that the number of forward protections n1 of the first forward protection is set to 1 in the forward protection counter m at 1. At this point, the block synchronization is not actually achieved, but the output (c) of the block synchronization signal is at a high level due to erroneous synchronization. At this time, the output (a) of the BIC detection timing signal until the value of the front protection counter becomes “0”;
The BIC detection signal (b) is compared. At time t3 before the value of the forward protection counter becomes “0”, an erroneous B
If a coincidence occurs between the BIC detection signal and the BIC detection timing signal by the IC signal, the value of the forward protection counter is reset. But at this time B
Since the data stored in the IC detection status storage circuit 101 is mostly “0”, the count value n2 of the forward protection counter set at time t3 is small. As a result, in the second process starting at time t4, a small value is used as the number of forward protections, so that erroneous synchronization is immediately determined.

That is, in the present embodiment, when the reception condition is poor (including when block synchronization occurs), a small value is set as the forward protection count, so that erroneous synchronization can be immediately determined. On the other hand, when the reception state is good, a large value is selected as the number of times of forward protection, so that the loss of synchronization hardly occurs.

In the present embodiment, a plurality of forward protection frequency setting circuits are provided, and a desired number of backward protection times is set from among them. Instead, a circuit for setting an initial value of the number of forward protection times is provided. By providing a circuit for calculating the desired number of forward protections based on the initial value, the number of forward protections may be set. Also, if the number of backward protections is set to be small, the synchronization is quickly established.

FIG. 4 is a diagram showing a BIC detection status counter of the block synchronization processing circuit according to the second embodiment of the present invention.

The feature of the block synchronization processing circuit according to the present embodiment is that the block synchronization processing circuit of the first embodiment of the present invention shown in FIG. , A BIC detection status counter (addition / subtraction circuit) is used. The other parts are substantially the same as those of the block synchronization processing circuit in the first embodiment, and thus description thereof will not be repeated.

Referring to FIG. 4, the BIC detection status counter includes an adder 220, a comparator 230, and an AND gate 2.
10a and 210b. As the adder 220, an adder having a count number sufficiently large or equivalent to the maximum number of forward protections is used.

Referring to the figure, the BIC detection signal input from input terminal 81 is input to the input terminal of AND gate 210b. The BIC detection signal input from the input terminal is input to the AND gate 210a after being inverted. The BIC detection timing signal input from the input terminal 82 is input to each of the AND gates 210a and 210b and the clock terminal (CLK) of the adder 220. The block synchronization signal input from the input terminal 83 is
0 is input after being inverted to the load terminal (LOAD). The output of the AND gate 210a is input to the subtraction terminal (DEC) of the adder 220, and the output of the AND gate 210b is input to the addition terminal (INC) of the adder 220. An initial value (for example, “0”) is input to the data input terminal (D) of the adder 220. The output Q of the adder 220 is input to the input terminal A of the comparator 230 and sent to the BIC detection status determination circuit 103 via the output terminal 85. The maximum value to be counted is input to input terminal B of comparator 230. Comparator 230 receives input data A and B
Of the AND gate 21 in response to the relation A = B
A high level signal is output to 0b. This signal is input to the AND gate 210b in an inverted state.

When the block synchronizing signal input through the block synchronizing signal input terminal 83 is at the high level by the circuit shown in FIG. 4, the BIC detection signal input from the BIC detection signal input terminal 81 and the BIC detection timing The adder 220 performs an adding operation when the BIC detection timing signal input from the signal input terminal 82 matches, and conversely, when the two signals do not match, the adder 2
20 performs a subtraction process. The data output from the output terminal Q of the adder 220 is compared with the maximum value set by the comparator 230. If the data output from the terminal Q matches the maximum value, no addition processing is performed. .

When the block is out of synchronization, the adder 220 is reset. As a result, if the state in which the BIC detection signal and the BIC detection timing signal match is large, a large number of data is sent to the BIC detection status determination circuit. A small number of data will be sent to the detection status determination circuit. This allows BIC
The detection status determination circuit can determine the reception status of the input signal. As in the first embodiment, when the reception status is poor, a small value of the number of forward protections is set, and when the reception status is good. Means that a large forward protection count is set.

In the circuit shown in FIG. 4, when the BIC detection signal coincides with the BIC detection timing signal, the adder 2
Although 20 is incremented by 1 and decremented by 1 when there is no match, any weight can be assigned to match / mismatch. For example, BIC detection signal and BI
The increment of + n1 may be performed when the signal coincides with the C detection timing signal, and the increment of -n2 may be performed when the signal does not coincide.

FIG. 5 is a flowchart showing processing in the block synchronization processing circuit according to the third embodiment of the present invention.

The block synchronization processing circuit in this embodiment is characterized in that the value counted by the front protection counter is changed according to the reception situation. Referring to the figure, when it is determined that block synchronization has been established, in step S101, the initial value n1 is substituted as the value (CNT) counted by the forward protection counter.

In step S102, it is determined whether it is time to detect the BIC. Y in step S102
If it is ES, it is determined in step S103 whether a BIC signal has been detected. YES in step S103
If so, in step S104, the count value (CNT) of the front protection counter is incremented by + m3.

In step S105, the count value (C
It is determined whether the value of (NT) exceeds the upper limit value m2 of the number of forward protections. If YES, the value of m2 is substituted for the count value (CNT) in step S106.

On the other hand, if NO in step S103, the count value (CNT) is decremented by -m4 in step S110. In step S111, it is determined whether the value of the count value (CNT) is 0 or less. If YES, it is determined that the block is out of synchronization.

If NO in step S102, the processing from step S102 is repeated. If NO in step S105 or step S111, the processing from step S102 is repeated.

As described above, by adopting the forward protection counter in this embodiment, the number of forward protections is set according to the reception status, so that the block synchronization processing which can more quickly determine block erroneous synchronization. A circuit can be provided.

In practicing the present invention, by adopting a small value as the number of backward protections, a block synchronization processing circuit which can quickly establish synchronization and can quickly perform an out-of-synchronization process for erroneous synchronization. Can be provided.

[0059]

In the block synchronization processing circuit according to the first to third aspects , a plurality of detection states stored in the detection state storage circuit are stored.
Since the number of times of forward protection can be set based on the situation , erroneous synchronization can be quickly released, and block synchronization processing can be properly performed.

[0060]

[0061]

The block synchronization processing circuit according to claim 4 sets the number of forward protections based on the value of the detection status counter.
Can be canceled quickly.
Block synchronization processing can be performed accurately.
You.

The block synchronization processing circuit according to claim 5 sets the number of forward protections based on the value of the forward protection counter.
Can be canceled quickly.
Block synchronization processing can be performed accurately.
You.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a block synchronization processing circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a specific example of a BIC detection status storage circuit 101 of FIG. 1;

FIG. 3 is a timing chart in a forward protection process according to the embodiment.

FIG. 4 is a diagram illustrating a BIC detection status counter of a block synchronization processing circuit according to a second embodiment of the present invention.

FIG. 5 is a flowchart illustrating a process in a block synchronization processing circuit according to a third embodiment of the present invention.

FIG. 6 is a timing chart showing a block synchronization process performed in a conventional FM multiplex broadcast receiver.

FIG. 7 is a timing chart showing processing in a conventional FM multiplex broadcasting receiver when the number of forward protections is set to m.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Block synchronization determination circuit 3 BIC detection circuit 5 Back protection number setting circuit 7 Forward protection number setting circuit 9 Selection circuit 11 BIC detection timing generation circuit 100 BIC status determination circuit 101 BIC detection status storage circuit 102 Addition circuit 103 BIC detection status determination circuit 104 threshold setting circuit 200 D flip-flop 210 AND gate 220 adder 230 comparator

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-75037 (JP, A) JP-A-6-326700 (JP, A) JP-A-62-245833 (JP, A) JP-A-4- 287442 (JP, A) JP-A-3-258049 (JP, A) JP-A-6-244830 (JP, A) JP-A-6-291758 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 7/08

Claims (5)

(57) [Claims] 1. A block synchronization processing circuit for processing block synchronization of a received signal, wherein a detection state of a block identification code is sequentially stored and stored.
A detection status storage circuit , wherein at the detection timing of the block identification code,
Based on multiple detection statuses stored in the status storage circuit,
A block synchronization processing circuit , wherein the number of protection times is set . 2. The apparatus according to claim 1, wherein said detection status storage circuit includes a block identification circuit.
When a code is detected, “1” is detected and the block identification code is detected.
When "0" is not output,
Is added to the stored value, and the added value is obtained.
The number of forward protections is set according to the value.
That, the block synchronization processing circuit according to claim 1. 3. Block synchronization is established from an out-of-sync state.
When the state is shifted to the
3. The block synchronization processing circuit according to claim 2, wherein the contents are reset . 4. Processing of block synchronization of a received signal.
A block synchronization processing circuit that performs an addition operation when a block identification code is detected,
Performs subtraction when no block identification code is detected.
A detection status counter.
A block synchronization processing circuit that sets the number of forward protections based on a value . 5. Processing of block synchronization of a received signal.
A block synchronization processing circuit that performs an addition operation when a block identification code is detected,
Performs subtraction when no block identification code is detected.
A forward protection counter for determining an out-of-synchronization state based on the value of the forward protection counter.
Separately, the forward protection counter has an upper limit set
A block synchronization processing circuit.