JP2684466B2 - Frame synchronization judgment circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization judgment circuit in digital radio transmission.

[0002]

2. Description of the Related Art In digital radio transmission, it is necessary to establish frame synchronization for transmitting and receiving data. As the frame synchronization method, a 1-bit shift hunting method and a reset type series method are known. Figure 1
9 illustrates a bit shift hunting type synchronization determination circuit. In the figure, the bit comparison circuit 1 compares the frame synchronization pattern a with the input data b, and if the comparison results do not match, shifts the input data by 1 bit and hunts them again. The 1-bit shift hunting circuit is not shown. In the 1-bit shift hunting method, a match is detected by this repetition and frame synchronization is established.

Here, a protection function is provided for the comparison result c in order to prevent out-of-synchronization due to a bit error in the transmission line and erroneous pull-in. The protection functions include synchronization pull-in protection and out-of-sync protection, which are realized by the synchronization pull-in protection circuit 2 and the out-of-sync protection circuit 3, respectively. The sync pull-in protection circuit 2 counts the number of coincidences of the comparison result c,
When the value set by the coincidence number setting circuit 4 is reached, the pull-in determination information d is transmitted. On the other hand, the out-of-synchronization protection circuit 3 counts the number of mismatches in the comparison result c, and when it reaches the value set by the mismatch count setting circuit 5, sends out the out-of-sync determination information e. Both the pull-in determination information d and the disconnection determination information e are input to the synchronization determination circuit 6 and the frame synchronization information f is output.

[0004]

In the above-described conventional frame synchronization determination circuit, since the value set by the mismatch setting circuit 5 is fixed, a pseudo pull-in phenomenon (pulling in to an incorrect data position in the process of establishing frame synchronization). Even if (phenomenon) occurs, if the value of the mismatch is smaller than the value set by the mismatch number setting circuit 5, there is a problem that the pseudo pull-in cannot be escaped. An object of the present invention is to provide a frame synchronization determination circuit that suppresses the occurrence of the pseudo pull-in phenomenon.

[0005]

A frame synchronization judgment circuit of the present invention is a timer circuit which outputs a control signal for reducing a set value set in an out-of-sync protection circuit for a certain period of time after a frame synchronization pull-in. Is provided. That is,
The non-coincidence setting circuit is configured to reduce the set value for a fixed time by the control signal from the timer circuit.

[0006]

According to the present invention, after the frame synchronization pull-in,
By reducing the setting value of the number of out-of-frame mismatches for a certain period of time, pseudo pull-in can be prevented.

[0007]

Next, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention, and the same components as those shown in FIG. 2 are designated by the same reference numerals. That is, the bit comparison circuit 1 uses the frame synchronization pattern a.
And input data b are bit-compared to generate a comparison result c. The comparison result c is input to the sync pull-in protection circuit 2 and the out-of-sync protection circuit 3. The synchronization pull-in protection circuit 2 counts the number of matches of the comparison result c, and when the number reaches the value set by the match number setting circuit 4, sends out the pull-in determination information d. On the other hand, the out-of-synchronization protection circuit 3 counts the number of mismatches in the comparison result c, and when it reaches the value set by the mismatch count setting circuit 5, sends out the out-of-sync determination information e. Both the pull-in determination information d and the disconnection determination information e are input to the synchronization determination circuit 6, and the frame synchronization information f is output.

A part of the frame synchronization information f is input to the timer circuit 7 provided in the present invention. The timer circuit 7 operates for a certain time after the frame synchronization is pulled in,
It is configured to output a control signal for reducing the set value of the mismatch count setting circuit 5 that sets the mismatch count of the out-of-sync protection circuit 3.

By providing the timer circuit 7,
Since the set value of the mismatch number setting circuit 5 is reduced for a fixed time by the control signal from the timer circuit 7, the count value of the mismatch number can easily exceed the set value even if the pseudo pull-in phenomenon occurs. The out-of-synchronization protection circuit 3 easily sends out-of-synchronization determination information e, re-pull-in is performed based on this out-of-synchronization determination information e, and then frame synchronization is established. At this time, if the pull-in is normal, no mismatch occurs. Therefore, even if the set value of the mismatch number is temporarily reduced by the control signal from the timer circuit 7, the establishment of frame synchronization is not adversely affected.

[0010]

As described above, according to the present invention, the possibility of the pseudo pull-in phenomenon is reduced by reducing the set value of the number of mismatches for a certain period of time after pulling in the frame sync by the frame sync information f. can do.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a frame synchronization determination circuit of the present invention.

FIG. 2 is a block diagram of an example of a conventional frame synchronization determination circuit.

[Explanation of symbols]

 1-bit comparison circuit 2 Sync pull-in protection circuit 3 Out-of-sync protection circuit 4 Match count setting circuit 5 Mismatch count setting circuit 6 Sync determination circuit 7 Timer circuit

Claims (2)

(57) [Claims] 1. A bit comparison circuit for bit-comparing a frame synchronization pattern with input data, a sync pull-in protection circuit for counting the number of coincidences of bit comparison results and comparing with a set value, and outputting pull-in determination information, and the number of coincidences. Matching number setting circuit that sets the count value of, the sync loss protection circuit that counts the number of mismatches of the bit comparison result and outputs the deviation determination information by comparing with the set value, and the number of mismatches that sets the count value of the mismatch number A setting circuit, a synchronization determination circuit for determining a frame synchronization state from the pull-in determination information and the disconnection determination information, and the mismatch number setting circuit for a certain period of time after the frame synchronization pull-in.
And a timer circuit that outputs a control signal for reducing the set value of the number of mismatches by the frame synchronization determination circuit. 2. The frame synchronization determination circuit according to claim 1, wherein the mismatch setting circuit is configured to reduce a set value for a fixed time by a control signal from a timer circuit.